CN202948923U

CN202948923U - CMOS circuit structure, OLED and display apparatus

Info

Publication number: CN202948923U
Application number: CN 201220687165
Authority: CN
Inventors: 任章淳
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2012-12-12
Filing date: 2012-12-12
Publication date: 2013-05-22
Anticipated expiration: 2022-12-12

Abstract

The utility model discloses a CMOS circuit structure, an OLED and a display apparatus, wherein in a CMOS circuit structure, a PMOS area is provided with an LTPS TFT structure, i.e., a PMOS semiconductor layer is prepared by a P-type doped polysilicon material, an NMOS area is provided with an Oxide TFT structure, i.e., the NMOS semiconductor layer is prepared by an oxide material, and the NMOS area replaces the prior polysilicon material with an oxide material to prepare an NMOS semiconductor layer, thereby omitting the three doping process steps of the NMOS area through using the TLPS process, simplifying the manufacture flow of the CMOS circuit structure, and reducing the production cost. The NMOS semiconductor layer of the NMOS area can be prepared by the oxide material, through only performing crystallization on the PMOS semiconductor layer of the PMOS area, thereby prolonging the service life of a laser tube, and reducing the production cost.

Description

A kind of cmos circuit structure, OLED and display unit

Technical field

The utility model relates to the circuit manufacturing technology field, relates in particular to a kind of cmos circuit structure, OLED and display unit.

Background technology

Complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal Oxide Semiconductor) by P type NMOS N-channel MOS N (PMOS, Positive channel Metal Oxide Semiconductor) and N-type NMOS N-channel MOS N (NMOS, Negative channel-Metal-Oxide-Semiconductor) is common consists of.

At present, be all generally to adopt low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) technology to prepare respectively the semiconductor layer in PMOS zone and nmos area territory in cmos circuit, its preparation technology's relative complex, the concrete technology step is as follows:

Step 1: on underlay substrate 01, utilize composition technique to form to be positioned at the figure of the PMOS semiconductor layer 02 of PMOS zone A, and the figure that is positioned at the NMOS semiconductor layer 03 of nmos area territory B, as shown in Figure 1a;

Wherein, the preparation process of PMOS semiconductor layer 02 and NMOS semiconductor layer 03 is specially: form one deck a-Si material on underlay substrate 01, through the polycrystalline silicon material that forms after laser crystallization, then form the figure of PMOS semiconductor layer 02 and NMOS semiconductor layer 03 by composition technology utilization polysilicon.

Step 2: form gate insulation layer 04 on PMOS semiconductor layer 02 and NMOS semiconductor layer 03, and on gate insulation layer 04 deposition of gate material, be positioned at the figure of the PMOS grid 05 of PMOS zone A by a composition technique formation, and the figure that is positioned at the NMOS grid 06 of nmos area territory B, as shown in Fig. 1 b;

Step 3: PMOS semiconductor layer 01 is carried out P type ion doping, particularly, cover the figure of the doping blocking layer 07 of nmos area territory B by a composition technique formation on NMOS grid 06, as Fig. 1 c; Then, the underlay substrate 01 with doping blocking layer 07 is injected P type ion, form P type doped polycrystalline silicon in the zone that PMOS semiconductor layer 01 is not blocked by PMOS grid 05, as Fig. 1 d; After injecting P type ion, peel off doping blocking layer 07.

Step 4: NMOS semiconductor layer 02 is carried out the N-type ion doping, and its concrete technology is identical with P type ion doping, does not do detailed description at this;

Step 5: the NMOS semiconductor layer is carried out LDD doping and Ch doping process successively, due to LDD doping and Ch doping process and P type ion doping technique similar, do not do detailed description at this;

Step 6: utilize the figure of a composition technique formation interlayer dielectric layer 08 on PMOS grid and NMOS grid, as shown in Fig. 1 e;

Step 7: utilize composition technique to form to be positioned at the figure of the PMOS source-drain electrode 09 of PMOS zone A on interlayer dielectric layer 08, and the figure that is positioned at the NMOS source-drain electrode 10 of nmos area territory B, as shown in Fig. 1 f.

Particularly, above-mentioned cmos circuit is completed above-mentioned steps 1 to step 7 when being applied to oled panel, also need to carry out following steps:

Step 8: utilize a composition technique to form the figure of passivation layer 11 on PMOS source-drain electrode 09 and NMOS source-drain electrode 10, and utilize the figure of a composition technique formation flatness layer 12 on passivation layer 11, as shown in Fig. 1 g;

Step 9: utilize a composition technique formation as the figure of the pixel layer of anode on flatness layer, source electrode or the drain electrode of this pixel layer and PMOS source-drain electrode are electrical connected, as shown in Fig. 1 h;

Step 10: utilize a composition technique to form the figure that pixel limits layer on pixel layer, as shown in Fig. 1 i.

In the above-mentioned LTPS of utilization technique prepares the process of cmos circuit, need to use photoresist mask plate and the doping process more than at least 4 times (P type ion doping, N-type ion doping, LDD doping and Ch doping) more than at least 10 times, the making flow process is complicated, production cost is higher, and, need the a-Si material laser crystallization with whole layer in step 1, to obtain polycrystalline silicon material, the laser crystallization process can increase the production cost of product for a long time, and can reduce the useful life of laser tube, also increase production cost.

The utility model content

The utility model embodiment provides a kind of cmos circuit structure, OLED and display unit, in order to optimize cmos circuit structure of the prior art and to optimize its fabrication processing, reduces production costs.

A kind of cmos circuit structure that the utility model embodiment provides, have PMOS zone and nmos area territory, comprise: be positioned at successively PMOS semiconductor layer, gate insulation layer, PMOS grid and NMOS grid, the first interlayer dielectric layer, NMOS semiconductor layer, the second interlayer dielectric layer and PMOS source-drain electrode and NMOS source-drain electrode on underlay substrate, wherein

Described PMOS semiconductor layer, PMOS grid and PMOS source-drain electrode are positioned at the PMOS zone; Described PMOS semiconductor layer is made by P type doped polycrystalline silicon materials;

Described NMOS semiconductor layer, NMOS grid and NMOS source-drain electrode are positioned at the nmos area territory; Described NMOS semiconductor layer is made by oxide material.

A kind of OLED that the utility model embodiment provides comprises the cmos circuit structure that the utility model embodiment provides.

A kind of display unit that the utility model embodiment provides comprises the cmos circuit structure that the utility model embodiment provides.

The beneficial effect of the utility model embodiment comprises:

a kind of cmos circuit structure that the utility model embodiment provides, OLED and display unit, the PMOS zone is LTPS TFT structure in the cmos circuit structure, namely use P type doped polycrystalline silicon materials to prepare the PMOS semiconductor layer, the nmos area territory is Oxide TFT structure, namely use oxide material to prepare the NMOS semiconductor layer, replace existing polycrystalline silicon material to prepare the NMOS semiconductor layer at nmos area territory use oxide material, can save when adopting TLPS technique three doping processs to the nmos area territory, can simplify the making flow process of cmos circuit structure, reduce production costs.In addition, the nmos area territory is designed to bottom gate type TFT structure, can saves the step that doping blocking layer is set when the P type Implantation of PMOS zone, simplified the making flow process.And, owing to adopting oxide material to make the NMOS semiconductor layer in nmos area territory, only need the PMOS semiconductor layer in PMOS zone is carried out crystallization, also can extend the useful life of laser tube, reduce production costs.

Description of drawings

The schematic diagram of each step when Fig. 1 a-Fig. 1 i prepares traditional cmos circuit structure for use TLPS method;

The schematic diagram of the cmos circuit structure that Fig. 2 provides for the utility model embodiment;

The preparation method's of the cmos circuit structure that Fig. 3 provides for the utility model embodiment flow chart;

The schematic diagram of each step when the cmos circuit structure prepares that Fig. 4 a-Fig. 4 h provides for the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing, the embodiment of cmos circuit structure, OLED and the display unit that the utility model embodiment is provided is described in detail.

In accompanying drawing, each regional shape and size do not reflect the true ratio of cmos circuit structure, and purpose is signal explanation the utility model content just.

A kind of cmos circuit structure that the utility model embodiment provides, as shown in Figure 2, have PMOS zone C and nmos area territory D, comprise: be positioned at successively PMOS semiconductor layer 22, gate insulation layer 23, PMOS grid 24 and NMOS grid 25, the first interlayer dielectric layer 26, NMOS semiconductor layer 27, the second interlayer dielectric layer 28 and PMOS source-drain electrode 29 and NMOS source-drain electrode 30 on underlay substrate 21, wherein

PMOS semiconductor layer 22, PMOS grid 24 and PMOS source-drain electrode 29 are positioned at PMOS zone A; PMOS semiconductor layer 22 is made by P type doped polycrystalline silicon materials;

NMOS semiconductor layer 27, NMOS grid 25 and NMOS source-drain electrode 30 are positioned at nmos area territory B; NMOS semiconductor layer 27 is made by oxide material.

Particularly, as shown in Figure 2, PMOS source-drain electrode 29 is connected with PMOS semiconductor layer 22 by via hole; NMOS source-drain electrode 30 is connected with NMOS semiconductor layer 27 by via hole.

In the above-mentioned cmos circuit structure that the utility model embodiment provides, the PMOS zone is the LTPSTFT structure, namely use P type doped polycrystalline silicon materials to prepare the PMOS semiconductor layer, the nmos area territory is Oxide TFT structure, namely use oxide material to prepare the NMOS semiconductor layer, replace existing polycrystalline silicon material to prepare the NMOS semiconductor layer at nmos area territory use oxide material, can save when adopting TLPS technique three doping processs to the nmos area territory, can simplify the making flow process of cmos circuit structure, reduce production costs.In addition, the nmos area territory is designed to bottom gate type TFT structure, can saves the step that doping blocking layer is set when the P type Implantation of PMOS zone, simplified the making flow process.And, owing to adopting oxide material to make the NMOS semiconductor layer in nmos area territory, only need the PMOS semiconductor layer in PMOS zone is carried out crystallization, also can extend the useful life of laser tube, reduce production costs.

In the specific implementation, the oxide material of preparation NMOS semiconductor layer 27 can use the materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), does not do restriction at this.

Further, in above-mentioned cmos circuit structure, cause the characteristic variation for fear of direct the contact with underlay substrate 21 of PMOS semiconductor layer 22 of adopting the polycrystalline silicon material preparation, as shown in Figure 2, can also between lower underlay substrate 21 and PMOS semiconductor layer 22, resilient coating 31 be set.

Particularly, the above-mentioned cmos circuit structure applications that provides at the utility model embodiment as shown in Figure 2, can also comprise following film layer structure during in oled panel:

Be positioned at successively on PMOS source-drain electrode 29 and NMOS source-drain electrode 30 flatness layer 32 and as the pixel layer 33 of anode, wherein, pixel layer 33 is electrical connected by source electrode or the drain electrode of via hole and PMOS source-drain electrode 29.

In the specific implementation, flatness layer 32 can be prepared by organic resin material.

Further, as shown in Figure 2, can also comprise: the pixel that is positioned on pixel layer 33 limits layer 34, is used for limiting pixel region.

The above-mentioned cmos circuit structure that the utility model embodiment provides can be applied in active matrix organic light-emitting device, also can be applied to not do restriction at this in TFT-LCD.

Based on same utility model design, the utility model embodiment also provides a kind of OLED, comprise the above-mentioned cmos circuit structure that the utility model embodiment provides, the enforcement of this OLED can referring to the embodiment of above-mentioned cmos circuit structure, repeat part and repeat no more.

Based on same utility model design, the utility model embodiment also provides a kind of display unit, comprise the above-mentioned cmos circuit structure that the utility model embodiment provides, the enforcement of this display unit can referring to the embodiment of above-mentioned cmos circuit structure, repeat part and repeat no more.

Particularly, this liquid crystal indicator can be the LCD of TN type, FFS type, IPS type or ADS type, the display unit such as OLED.This display unit also can comprise: any product or parts with Presentation Function such as oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.

Based on same utility model design, the utility model embodiment also provides a kind of preparation method of above-mentioned cmos circuit structure, as shown in Figure 3, specifically comprises the steps:

S301, form the figure of the PMOS semiconductor layer 22 be positioned at PMOS zone C on underlay substrate 21, as shown in Fig. 4 a; This PMOS semiconductor layer 22 is made by polycrystalline silicon material;

Preferably, before the figure that forms the PMOS semiconductor layer 22 that is positioned at PMOS zone C on underlay substrate 21, as shown in Fig. 4 a, can also first form resilient coating 31 on underlay substrate 21, to avoid adopting direct the contact with underlay substrate 21 of PMOS semiconductor layer 22 meetings of polycrystalline silicon material preparation to cause the characteristic variation.

Particularly, form the step of the figure of the PMOS semiconductor layer 22 that is positioned at PMOS zone C on underlay substrate 21, in the specific implementation, can first form the figure of a-Si layer on underlay substrate 21; Then, can utilize the mode of u-crystallization, laser annealing, selective laser sintering, metal-induced crystallization (MIC:metal inducedcrystallization), metal induced lateral crystallization or continuous granular crystal silicon with a-Si layer crystal formation PMOS semiconductor layer 22, because the mode of above-mentioned crystallization belongs to prior art, do not do detailed description at this.

S302, form gate insulation layer 23 on PMOS semiconductor layer 22, and form the figure of the PMOS grid 24 that is positioned at PMOS zone C on gate insulation layer 23, and the figure that is positioned at the NMOS grid 25 of nmos area territory D, as shown in Fig. 4 b;

S303, PMOS semiconductor layer 22 is carried out P type ion doping, as shown in Fig. 4 c;

Particularly, owing to also not forming the NMOS semiconductor layer in the nmos area territory, therefore, can directly inject in the zone P type ion to PMOS in underlay substrate 21, save the technique that doping blocking layer is set in the nmos area territory.

S304, form the figure of the first interlayer dielectric layer 26 on PMOS grid 24 and NMOS grid 25; And form the figure of the NMOS semiconductor layer 27 be positioned at the nmos area territory on the first interlayer dielectric layer 26, as shown in Fig. 4 d, this NMOS semiconductor layer 27 is made by oxide material;

Particularly, when forming the figure of the NMOS semiconductor layer 27 that is positioned at nmos area territory D on the first interlayer dielectric layer 26, specifically can adopt the mode of sputter, ald or Organometallic Chemistry vapor phase deposition to form this NMOS semiconductor layer 27, because the mode of above-mentioned formation NMOS semiconductor layer 27 belongs to prior art, do not do detailed description at this.

S305, form the figure of the second interlayer dielectric layer 28 on NMOS semiconductor layer 27, as shown in Fig. 4 e;

S306, form the figure of the PMOS source-drain electrode 29 be positioned at PMOS zone C on the second interlayer dielectric layer 28, and the figure that is positioned at the NMOS source-drain electrode 30 of nmos area territory D, as shown in Fig. 4 f.

In the specific implementation, above-mentioned cmos circuit is completed above-mentioned steps S301 to step S306 when being applied to oled panel, as shown in Figure 3, also need to carry out following steps:

S307, form the figure of flatness layer 32 on PMOS source-drain electrode 29 and NMOS source-drain electrode 30, as shown in Fig. 4 g;

S308, form the figure as the pixel layer 33 of anode on flatness layer 32, pixel layer 33 is electrical connected with source electrode or the drain electrode of PMOS source-drain electrode 29, as shown in Fig. 4 h;

S309, form the figure that pixel limits layer 34 on pixel layer 33, as shown in Figure 2.

Obviously, those skilled in the art can carry out various changes and modification and not break away from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model also is intended to comprise these changes and modification interior.

Claims

1. cmos circuit structure, have PMOS zone and nmos area territory, it is characterized in that, comprise: be positioned at successively PMOS semiconductor layer, gate insulation layer, PMOS grid and NMOS grid, the first interlayer dielectric layer, NMOS semiconductor layer, the second interlayer dielectric layer and PMOS source-drain electrode and NMOS source-drain electrode on underlay substrate, wherein

2. cmos circuit structure as claimed in claim 1, is characterized in that, described oxide material is indium gallium zinc oxide IGZO, zinc oxide ZnO, indium zinc oxide IZO, indium tin zinc oxide ITZO.

3. cmos circuit structure as claimed in claim 1, is characterized in that, also comprises: the resilient coating between described underlay substrate and described PMOS semiconductor layer.

4. cmos circuit structure as claimed in claim 1, is characterized in that, described PMOS source-drain electrode is connected with described PMOS semiconductor layer by via hole; Described NMOS source-drain electrode is connected with described NMOS semiconductor layer by via hole.

5. cmos circuit structure as described in claim 1-4 any one, it is characterized in that, also comprise: be positioned at successively on described PMOS source-drain electrode and NMOS source-drain electrode flatness layer and as the pixel layer of anode, described pixel layer is electrical connected by source electrode or the drain electrode of via hole and described PMOS source-drain electrode.

6. cmos circuit structure as claimed in claim 5, is characterized in that, also comprises: the pixel that is positioned on described pixel layer limits layer.

7. an OLED, is characterized in that, comprises cmos circuit structure as described in claim 1-6 any one.

8. a display unit, is characterized in that, comprises cmos circuit structure as described in claim 1-6 any one.