CN202929190U - Relay protection tester inspection device - Google Patents
Relay protection tester inspection device Download PDFInfo
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- CN202929190U CN202929190U CN 201220696308 CN201220696308U CN202929190U CN 202929190 U CN202929190 U CN 202929190U CN 201220696308 CN201220696308 CN 201220696308 CN 201220696308 U CN201220696308 U CN 201220696308U CN 202929190 U CN202929190 U CN 202929190U
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- 238000007689 inspection Methods 0.000 title abstract 3
- 230000003750 conditioning effect Effects 0.000 claims abstract description 41
- 230000001360 synchronised effect Effects 0.000 claims abstract description 29
- 238000001914 filtration Methods 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 9
- 230000003068 static effect Effects 0.000 claims description 7
- 230000011664 signaling Effects 0.000 claims description 2
- 238000012360 testing method Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 14
- 238000005070 sampling Methods 0.000 description 11
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- 238000006243 chemical reaction Methods 0.000 description 6
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- 238000013461 design Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
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- 238000011161 development Methods 0.000 description 1
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Abstract
The utility model discloses a relay protection tester inspection device capable of carrying out testing on the performance of a relay protection tester. The relay protection tester inspection device comprises a voltage signal conditioning module, a current signal conditioning module, an AD synchronous converter, a phase-locked loop module and a control module. An input end of the AD synchronous converter is respectively connected with output ends of the voltage signal conditioning module and the current signal conditioning module. A signal input end of the phase-locked loop module is connected with the output end of the voltage signal conditioning module. An output end of the phase-locked loop module is connected with a clock input channel of the AD synchronous converter. A signal output channel of the control module is connected with another signal input channel of the phase-locked loop module. The control module is in data connection with the AD synchronous converter.
Description
Technical field
The utility model relates to a kind of verifying attachment, is specifically related to a kind of relay-protection tester verifying attachment.Belong to electric signal and check the field.
Background technology
Whether the voltage transformer (VT) (PT) of relay-protection tester simulation measurand, the secondary side signal of current transformer (CT) input to protective relaying device, work with the check protective relaying device.In actual use, relay-protection tester equipment is simple, and is powerful, and easy to operate characteristics have been brought into play huge effect in the relay protection test field.But due to development ability and working condition different, so the tester of each producer has larger gap at aspects such as overall performance, quality, structure, techniques.Some tester has problems at aspects such as Software for Design, load capacity, precision, job stability and reliabilities.But also there is no special verifying attachment for relay-protection tester now.The utility model proposes a kind of verifying attachment for relay-protection tester for above-mentioned phenomenon, with the performance difference of check relay-protection tester.
The utility model content
The purpose of this utility model is for overcoming above-mentioned the deficiencies in the prior art, a kind of relay-protection tester verifying attachment is provided, and this relay-protection tester verifying attachment can be tested the performance of relay-protection tester.
For achieving the above object, the utility model adopts following technical proposals:
A kind of relay-protection tester verifying attachment, comprise a voltage signal conditioning module, a current signal conditioning module, an AD synchronous converter, a phase-locked loop module and a control module, the input end of described AD synchronous converter is connected output terminal and is connected with the current signal conditioning module with described voltage signal conditioning module; A signal input part of described phase-locked loop module is connected with the output terminal of voltage signal conditioning module, and the output terminal of described phase-locked loop module is connected with the clock input channel of AD synchronous converter; The signal output channels of described control module is connected with another signal input channel of described phase-locked loop module, and described control module is connected with described AD synchronous converter data.
Described voltage signal conditioning module is connected with the Voltage-output signaling interface of relay-protection tester, and described current signal conditioning module is connected with the current output signal interface of relay-protection tester.
Described relay-protection tester verifying attachment also comprises a high speed static buffer memory (SRAM), and it is connected with described control module, and is connected with described AD synchronous converter data.
Described relay-protection tester verifying attachment also comprises a communication module, and described communication module is communicated by letter with control module.
Described current signal conditioning module comprises that a buffer circuit and holds the resistance filtering circuit.
Described voltage signal conditioning module comprises that a buffer circuit and holds the resistance filtering circuit.
Described phase-locked loop module comprises a sine square waveform change-over circuit and a square wave frequency multiplier circuit.
Principle of work of the present utility model:
The utility model can be realized automatic measurement, also can manually boot measurement.After startup; control module output control signal is to the AD synchronous converter; the acquisition channel of AD synchronous converter while gate voltage signal and current signal; the voltage signal of relay-protection tester is delivered to phase-locked loop module after the conditioning of overvoltage signal conditioning module; phase-locked loop module carries out producing after filtering a square-wave signal with the line voltage same frequency to the received signal; this square wave signal is transported to the square wave frequency multiplier circuit; produce the clock signal of AD synchronized sampling according to the control signal of control module, be delivered to the input end of clock mouth of AD synchronous converter.
The startup of AD synchronous converter deposits the signal that collects in high speed static buffer memory (SRAM) in, by control module, data is read after gathering end.Control module is carried out the integrated conduct methods such as digital filtering, first-harmonic extraction, phase place discriminating and is processed to the voltage and current data that collect, calculate input voltage, electric current frequency, differ, amplitude etc.
The beneficial effects of the utility model are; relay-protection tester verifying attachment of the present utility model has solved does not also have special this problem of verifying attachment for relay-protection tester at present, has realized the test and check to the main performance of relay-protection tester.
Description of drawings
Fig. 1 is structured flowchart of the present utility model;
Fig. 2 is the circuit diagram of current signal conditioning module;
Fig. 3 is voltage signal conditioning module circuit diagram;
Fig. 4 is sinusoidal wave square wave conversion circuit figure in phase-locked loop module;
Fig. 5 is square wave frequency multiplier circuit figure in phase-locked loop module;
Fig. 6 is the circuit diagram of AD synchronous converter;
Fig. 7 is the circuit diagram of control module;
Fig. 8 is the circuit diagram of storer in control module;
Wherein, 2. voltage signal conditioning module, 4. current signal conditioning module; 5. phase-locked loop module; 6.AD synchronous converter, 7. control module, 8. communication module; 9. high speed static buffer memory (SRAM); 11. the three-phase voltage output signal of relay-protection tester, the three-phase current output signal of 12. relay-protection testers, 51. operational amplifier I; 52. operational amplifier II, 53. comparers.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further set forth, should be noted that following explanation is only in order to explain the utility model, its content not to be limited.
As shown in Figure 1, the utility model comprises voltage signal conditioning module 2, current signal conditioning module 4, phase-locked loop module 5, AD synchronous converter 6, control module 7, communication module 8, high speed static buffer memory (SRAM) 9.Wherein, the three-phase voltage output signal 11 of voltage signal conditioning module 2 access relay-protection testers and the three-phase current output signal 12 of relay-protection tester, this three road Voltage-outputs signal and current output signal are respectively after the conditioning of overvoltage signal conditioning module 2 and current signal conditioning module 4, enter AD synchronous converter 6, that is to say, three road signal output channels of voltage signal conditioning module 2, three road signal output channels of current signal conditioning module 4 are connected with six road signal input channels of AD synchronous converter 6 respectively; The signal output channels of voltage signal conditioning module 2 is connected with the first signal input channel of phase-locked loop module 5, and the signal output channels of this phase-locked loop module 5 is connected with the clock input channel of AD synchronous converter 6; The data bus of this AD synchronous converter 6 is connected respectively with the data bus of the data bus of control module, high speed static buffer memory (SRAM) 9, the passage control interface of control module 7 is connected with the passage control interface of high speed static buffer memory (SRAM) 9, control module 7 is communicated by letter with communication module 8, in the present embodiment, the Ethernet interface of control module 7 is connected with outside industrial computer 8 with optical fiber interface, and the signal output channels of control module 7 is connected with the secondary signal input channel of phase-locked loop module 5.
The current signal conditioning module comprises buffer circuit and the appearance resistance filtering that mainly is comprised of linear optical coupling, and its detailed circuit as shown in Figure 2.Diode D204 is Transient Suppression Diode TSMB6.8CA, plays the effect of transition and surge protection.Diode D205 is voltage twin zener dioder GBLC03, and input voltage is limited in 3V.U204 is low-noise accurate operational amplifier OP27, and effect is the isolation transmission of settling signal.Resistance R 210, resistance R 211, resistance R 212 consist of in-phase amplifier, and enlargement factor is 2 times, and the output CT_AnaInPut1 of U201 follows the variation of input voltage CT_Input1.
The voltage signal conditioning module comprises buffer circuit and the appearance resistance filtering circuit that mainly is comprised of voltage transformer (VT), and its detailed circuit as shown in Figure 3.U202 in Fig. 4 is accurate AC voltage transformer TV1013, and its input and output current rating is 2mA, plays the isolation transmitting effect of signal.Because input voltage value is about 220V, so design resistance R 204 is resettable fuse, diode D202 is the gas-discharge tube of 250V, has both played release Lightning Transient excess current and over-voltage effect.Resistance R 203 is sampling resistor, when value is 100K Ω, can be the current signal that voltage signal voltage _ Input0+ of 220V converts 2.2mA to input value, passes to rear class by mutual inductor.Resistance R 208 is the secondary side sampling resistor of mutual inductor TV1013, and value is 249 Ω, and making mutual inductor secondary side output voltage ratings is U=2mA * 249 ≈ 0.5V.D203 is Transient Suppression Diode TSMB6.8CA, for the amplifier of rear class plays the overvoltage protection effect.
Because output voltage will be as the reference voltage of phaselocked loop, therefore higher to the accuracy requirement of voltage, select the U203 conduct in figure to be high-precision meter amplifier AD8221, and adopted the differential pair connected mode at input end, to improve the precision of voltage signal transmission, reduce phase deviation.Resistance R 209 is adjustable gain resistance, and when its value was 49.9 Ω, gaining was 49.9k/49.9k+1=2, and namely the specified amplitude of last output voltage voltage _ Input0 is 1V.Resistance R 206, resistance R 207 and capacitor C 200, capacitor C 201 consists of low-pass filters, selects the suitable resistance can filtering useful band signal in addition.
The effect of phase-locked loop module is to obtain the real-time grid frequency by the output of voltage secondary side, then by after phaselocked loop and process of frequency multiplication as the clock of AD synchronous converter 6, thereby realization is integer-period sampled to voltage, electric current, one road voltage signal of voltage signal conditioning module 2 outputs as the input of phase-locked loop module 5, is the square-wave signal of mains frequency integral multiple through output frequency after phaselocked loop and process of frequency multiplication.Therefore, phase-locked loop module 5 comprises sinusoidal wave square wave conversion circuit and square wave frequency multiplier circuit two parts.
Fig. 4 has shown the sinusoidal wave square wave conversion circuit figure in phase-locked loop module 5, this sine wave square wave conversion circuit comprises operational amplifier I51, operational amplifier II52 and comparer 53, the output terminal of operational amplifier I51 is through resistance R 226, resistance R 227 connects the positive input of operational amplifier II52, the negative input of operational amplifier I51 connects the output terminal of operational amplifier I51, node between resistance R 226 and resistance R 227 connects negative input and the output terminal of operational amplifier II52 through capacitor C 207, the node of resistance R 227 and operational amplifier II52 is through capacitor C 204 ground connection, the negative input of the output termination comparer 53 of operational amplifier II52, the positive input of this comparer 53 is through resistance R 233 ground connection, the positive input of this comparer 53 connects the output terminal of this comparer 53 through resistance R 234, the output terminal of this comparer 53 connects+3V3D through resistance R 232, the AIN interface of the phase-locked loop chip U502 of the output termination square wave frequency multiplier circuit of this comparer 53.In Fig. 4, U200A and U200B are two passages of operational amplifier I51 and operational amplifier II52, U200A plays the effect of isolated amplifier, resistance R 226, resistance R 227, capacitor C 207, capacitor C 204 and U200B have consisted of second-order low-pass filter, R226=15K, R227=15K, C207=0.1uF, C204=0.22uF in the present embodiment, its cutoff frequency is 70Hz, meets the requirement of low-pass filtering.Comparer 53, resistance R 233 and resistance R 234 have formed the bipolarity zero-crossing comparator, and sine wave shaped is become square-wave signal PwrFrqIn, with the input signal as the rear class frequency multiplier circuit.Resistance R 232 is the pull-up resistor of output terminal, and value is 200 ohm, and comparer 53 output level PwrFrqIn are 0-3.3V, with the incoming level coupling of the CD4046 of rear class.
Fig. 5 has shown the square wave frequency multiplier circuit figure in phase-locked loop module 5, U502 is phase-locked loop intergrated circuit chip CD4046, its principle of work is to complete two signal phases synchronous automatic Control loop systems by the voltage controlled oscillator that includes and phase comparator, realize output voltage and input voltage same-phase, realize the Phase Tracking function.14 pin of U502 are input voltage PwrFrqIn, and 4 pin are output voltage AD_Clk, as the clock of AD converter.Due to the employing of CD4046 phaselocked loop is RC type voltage controlled oscillator, so resistance R 502, resistance R 504, capacitor C 503 are as the external element that discharges and recharges, the resistance of resistance R 502 and capacitor C 503 has determined the surge frequency range of chip, as resistance R 502=30k Ω, during capacitor C 503=40pF, the vibration highest frequency is 1/RC=8.3MHz.Resistance R 504, resistance R 505, capacitor C 505 are adjusted its resistance size and can be realized exporting the stable of square wave as external low-pass filter.U501 is frequency divider 74HC4040, connects different pins by jumper cap and can realize different sample frequency, to satisfy different sampling requests.Because input signal is 50Hz, so be respectively 25KHz, 50KHz, 100KHz, 200KHz when the AD clock frequency that connects 4,13,12, realize during 14 pin.
Fig. 6 has shown the circuit diagram of AD synchronous converter 6, and in figure, 3,4, No. 5 pins are the over-sampling selecting side, and the over-sampling corresponding with LPC2292 in control module 7 selects output pin to be connected respectively, carries out over-sampling and selects; No. 6 pins are that the AD7606-6 interface mode is selected, and select the parallel output mode when connecing low level, connect high level and select serial output mode, connect low level in the design and select parallel mode; Whether No. 7 pins are controlled AD7606-6 by control module and are hung up, Low level effective for hanging up pin; No. 8 pins are that RANGE selects input end, connect 100K resistance R 500 ground connection, are connected with the AD_RangeSel pin of control module LPC2292 simultaneously, when the RANGE input end is low level, sample range is ± 5V that when the RANGE input end was high level, sample range was ± 10V; No. 23 pins are the VDRIE pin, adopt 3.3V; 9, No. 10 pins are first three road, rear three tunnel sample frequency input pins; No. 11 pin are the RST pin, before the AD7606-6 normal operation, need to carry out reset operation to it, are controlled by control module; 12,13 pin are respectively read signal input pin and the chip selection signal input pin that reads AD7606-6 when controlling data; No. 14 pin are the interrupt output pin, and each sampling is completed, and AD7606-6 will export look-at-me notice LPC2292 sampling and finish; No. 15 pin is FirstData sign pin, is used for serial output mode and plays the mark effect; 44,45 pin are respectively first three road, rear three road reference capacitance pins, meet pin AGND No. 46 after connecing 10uF capacitor C 504, guarantee reference voltage waveform stabilization in sampling process.
Although above-mentionedly by reference to the accompanying drawings embodiment of the present utility model is described; but be not the restriction to the utility model protection domain; on the basis of the technical solution of the utility model, those skilled in the art do not need to pay various modifications that creative work can make or distortion still in protection domain of the present utility model.
Claims (7)
1. relay-protection tester verifying attachment, comprise a voltage signal conditioning module, a current signal conditioning module, an AD synchronous converter, a phase-locked loop module and a control module, it is characterized in that, the input end of described AD synchronous converter is connected output terminal and is connected with the current signal conditioning module with described voltage signal conditioning module; A signal input part of described phase-locked loop module is connected with the output terminal of voltage signal conditioning module, and the output terminal of described phase-locked loop module is connected with the clock input channel of AD synchronous converter; The signal output channels of described control module is connected with another signal input channel of described phase-locked loop module, and described control module is connected with described AD synchronous converter data.
2. a kind of relay-protection tester verifying attachment according to claim 1; it is characterized in that; described voltage signal conditioning module is connected with the Voltage-output signaling interface of relay-protection tester, and described current signal conditioning module is connected with the current output signal interface of relay-protection tester.
3. a kind of relay-protection tester verifying attachment according to claim 1, is characterized in that, described relay-protection tester verifying attachment also comprises a high speed static buffer memory, and it is connected with described control module, and be connected with described AD synchronous converter data.
4. a kind of relay-protection tester verifying attachment according to claim 1, is characterized in that, described relay-protection tester verifying attachment also comprises a communication module, and described communication module is communicated by letter with control module.
5. a kind of relay-protection tester verifying attachment according to claim 1, is characterized in that, described current signal conditioning module comprises that a buffer circuit and holds the resistance filtering circuit.
6. a kind of relay-protection tester verifying attachment according to claim 1, is characterized in that, described voltage signal conditioning module comprises that a buffer circuit and holds the resistance filtering circuit.
7. a kind of relay-protection tester verifying attachment according to claim 1, is characterized in that, described phase-locked loop module comprises a sine square waveform change-over circuit and a square wave frequency multiplier circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220696308 CN202929190U (en) | 2012-12-14 | 2012-12-14 | Relay protection tester inspection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220696308 CN202929190U (en) | 2012-12-14 | 2012-12-14 | Relay protection tester inspection device |
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| CN202929190U true CN202929190U (en) | 2013-05-08 |
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| CN 201220696308 Expired - Lifetime CN202929190U (en) | 2012-12-14 | 2012-12-14 | Relay protection tester inspection device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103033788A (en) * | 2012-12-14 | 2013-04-10 | 山东电力集团公司电力科学研究院 | Relay protection tester testing device |
| CN106154200A (en) * | 2016-06-15 | 2016-11-23 | 贵州电网有限责任公司六盘水供电局 | Portable GIS local discharge high frequency sensors test device and method of testing |
-
2012
- 2012-12-14 CN CN 201220696308 patent/CN202929190U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103033788A (en) * | 2012-12-14 | 2013-04-10 | 山东电力集团公司电力科学研究院 | Relay protection tester testing device |
| CN106154200A (en) * | 2016-06-15 | 2016-11-23 | 贵州电网有限责任公司六盘水供电局 | Portable GIS local discharge high frequency sensors test device and method of testing |
| CN106154200B (en) * | 2016-06-15 | 2023-04-07 | 贵州电网有限责任公司六盘水供电局 | Portable GIS partial discharge high-frequency sensor testing device and testing method |
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Granted publication date: 20130508 |