CN202889607U

CN202889607U - Three-dimensional speaker box

Info

Publication number: CN202889607U
Application number: CN 201220541218
Authority: CN
Inventors: 陈昌宏
Original assignee: DONGGUAN EARSON AUDIO TECHNOLOGY Co Ltd
Current assignee: DONGGUAN EARSON AUDIO TECHNOLOGY Co Ltd
Priority date: 2012-10-22
Filing date: 2012-10-22
Publication date: 2013-04-17
Anticipated expiration: 2022-10-22

Abstract

The utility model relates to a three-dimensional speaker box comprising two loudspeakers and an audio processing circuit; the audio processing circuit comprises a signal switching and volume controlling circuit, a TSS (Time-Sharing System) module circuit and a left/right sound channel PWM (Pulse-Width Modulation) amplifying circuit; the signal switching and volume controlling circuit is used for converting a sound current signal into a left/right sound channel current signal to be transmitted to the TSS module circuit; the TSS module circuit comprises an A/D (Analog-to-Digital) converter, a DSP (Digital Signal Processor) and a TSS module MCU (Microprogrammed Control Unit); after being processed by the TSS module circuit, a common left/right sound channel current signal is converted into a three-dimensional sound signal by the TSS module MCU, and then, the three-dimensional sound signal is transmitted to the left/right sound channel PWM amplifying circuit; and the two loudspeakers are respectively connected with the left/right sound channel PWM amplifying circuit. By using the three-dimensional speaker box, the common sound signal is converted into the three-dimensional sound signal through the DSP, and the sound signal is amplified and played through a later-stage power amplifying circuit and the loudspeakers, so that the better 3D sound is produced.

Description

A kind of solid sound box

Technical field

The utility model relates to a kind of audio amplifier, specifically, relates to a kind of solid sound box.

Background technology

Along with the fast development of electronic product, electronic product is more and more universal.And along with the raising of people's living standard, people require more and more higher to the tonequality of electronic product; In order to improve the tonequality of electronic product, such as computer, television set etc., people have adopted the audio amplifier of configurational formula, namely adopt a plurality of loudspeaker at the local sounding of difference, thereby simulate three dimensional sound, allow the people experience to have stronger stereo; It is 200820303587.3 Chinese utility model patent such as the patent No., this patent discloses a kind of multitone territory surround speaker and has adjusted structure, it comprises a body, and body is microscler solid sound box, the place ahead of body, rear, side and below select the position and be provided with several loudspeaker; Come the simulated sound surrounding effect by a plurality of loudspeaker.And in reality, generally only be provided with two common audio amplifiers, be difficult to simulate stereo-circulation sound.

Summary of the invention

The purpose of this utility model is to solve the deficiencies in the prior art, and a kind of solid sound box is provided, and this solid sound box is by the processing to audio signal, so that two common audio amplifiers can obtain stereo preferably.

For achieving the above object, the technical solution adopted in the utility model is:

A kind of solid sound box comprises two loudspeaker and audio frequency processing circuit, and described audio frequency processing circuit comprises signal switching and volume control circuit, TSS modular circuit, left and right acoustic channels PWM amplifying circuit; Described signal switching and volume control circuit change the acoustic current-meter signal that receives into the left and right acoustic channels current signal and pass to the TSS modular circuit, described TSS modular circuit comprises the A/D analog to digital converter, DSP digital signal processor and TSS module MCU, the A/D analog to digital converter changes the left and right acoustic channels current signal that receives into digital audio and video signals, and this digital audio and video signals passed to the DSP digital signal processor, described DSP digital signal processor is processed into the 3 D stereo acoustical signal with digital audio and video signals, and this 3 D stereo acoustical signal passed to TSS module MCU, TSS module MCU passes to left and right acoustic channels PWM amplifying circuit with the 3 D stereo acoustical signal, and described two loudspeaker are connected with left and right acoustic channels PWM amplifying circuit respectively.

Here TSS represents true surround sound, namely truly around sound.

Further, described A/D converter comprises conversion chip ES7240, and this conversion chip ES7240 is provided with pin MO, MALK, VDDP, SDOUT, GNDD, VDDD, SCLK, LRCK, RESETB, AINL, REFQ, AINR, VDDA, GNDA, REFP, M1; Described pin MO, the equal ground connection of M1, described pin VDDP connects the 3.3V_VP supply terminals, described pin VDDD is connected with the 3.3V_VD supply terminals, and be provided with capacitor C 49 between pin VDDP and the VDDD, C50, C51, C52; One end of described capacitor C 51, the end of C52 are connected with pin VDDD respectively, the other end of capacitor C 51, the equal ground connection of the other end of C52, one end of described capacitor C 49, the end of C50 are connected with pin VDDP respectively, the other end of described capacitor C 49, the equal ground connection of the other end of C50; Described pin VDDA connects the 3.3V_VA supply terminals, described pin GNDA ground connection, and be provided with capacitor C in parallel 39, C40 between pin VDDA and the pin GNDA; Described pin REFP is connected with the capacitance group C41_42 that is comprised of capacitor C 41 and C42, the termination pin REFP of capacitance group C41_42, the other end ground connection of capacitance group C41_42; Described pin REFQ is connected with the capacitance group C44_45 that is comprised of C44 and C45, and the end of capacitance group C44_45 is connected with pin REFQ, the other end ground connection of capacitance group C44_45; Described pin AINL is connected with capacitor C 71, resistance R 41, and an end of described capacitor C 71 is connected with pin AINL, and the other end of capacitor C 71 is connected with an end of resistance R 41, and the other end of described resistance R 41 is connected with the LOUT terminals; Described pin AINR is connected with capacitor C 72, resistance R 42, and an end of described capacitor C 72 is connected with pin AINR, and the other end of capacitor C 72 is connected with an end of resistance R 42, and the other end of resistance R 42 is connected with the ROUT terminals; Described A/D converter also comprises resistance R 13, R14, R43, R44 and capacitor C 69, C70, and an end of described resistance R 44, an end of capacitor C 69 are connected with an end of described resistance R 41, the equal ground connection of the other end of the other end of described resistance R 44, capacitor C 69; One end of described resistance R 43, an end of capacitor C 70 are connected with an end of described resistance R 42, the equal ground connection of the other end of the other end of described resistance R 43, capacitor C 70; One end of described resistance R 13 is connected with an end of described resistance R 41, another termination L_IN terminals of described resistance R 13, and an end of described resistance R 14 is connected with an end of described resistance R 42, and the other end of described resistance R 14 connects the R_IN terminals; Described pin MALK is connected with the MCLK terminals, and pin LRCK is connected with the LRCK terminals, and is in series with resistance R 28 between pin LRCK and the LRCK terminals; Pin SCLK is connected with the SCLK terminals, and be in series with resistance R 27 between pin SCLK and the SCLK terminals, pin SDOUT is connected with between SDIN terminals and pin SDOUT and the SDIN terminals and is in series with resistance R 17, also comprise resistance R 29 and 3.3V_VP terminals, one end of resistance R 29 is connected with the SDOUT terminals, and the other end of resistance R 29 is connected with the 3.3V_VP terminals.

Further, described DSP digital signal processor comprises process chip BAT631H, and described process chip BAT631H is provided with pin PWMVDD1, PWM0, PWM1, PWM2, PWM3, PWMGND1, PWMVDD2, PWM4, PWM5, PWM6, PWM7, PWMGND2, SPDIFRX, SPDIFTX, TEST, IRQA, IRQB, PGND, RVDD1, PSCURR, PSTEMP, PR00, PR01, PR02, SCK2, STD2, SC22, MCLK, CVDD, CGND, RGND, RVDD2, SCK, TI01, MIS0, MOSI, SCL, SDA, TI00, NRESET, NRSTOUT, CVDD1, CGND1, NSS, PLLAVDD, XTAL0, XTAL1, PLLAGND; Wherein, pin SCK2 is connected with the SCLK terminals, pin STD2 is connected with the SDIN terminals, pin SC22 is connected with the LRCK terminals, described pin MCLK is connected with resistance R 31, capacitor C 23, wherein the two ends of resistance R 31 are connected with the MCLK terminals with pin MCLK respectively, and an end of capacitor C 23 is connected with pin MCLK, the other end ground connection of capacitor C 23; Pin CVDD is connected with DSP_1.8V, pin CGND ground connection, and be provided with capacitor C 24, C25 between pin CVDD and the pin CGND, an end of capacitor C 24, the end of C25 are connected with pin CVDD respectively, and the other end of capacitor C 24, the other end of C25 are connected with CGND respectively; Pin RVDD2 is connected with DSP_3.3V, and be provided with capacitor C in parallel 27, C35 between pin RVDD2 and the pin CGND, one end of capacitor C 27, the end of C35 are connected with pin CGND respectively, and the other end of capacitor C 27, the other end of C35 are connected with RVDD2 respectively; Described pin TI01 is provided with resistance R 19 outward, the two ends of R19 are connected with the MUTE terminals with pin TI01 respectively, pin SPDIFRX is connected with terminals SPDIFRX, pin SPDIFTX is by resistance R 1 ground connection, pin TEST is by resistance R 32 ground connection, pin IRQA, be provided with resistance R 45 between the IRQB, R46, R47, R48, R49, R72, an end of resistance R 45 wherein, the end of R48 is connected with pin IRQA respectively, one end of resistance R 46, the end of R47 is connected with pin IRQB respectively, one end of resistance R 49 is connected with the DSP_3.3V terminals, the other end of resistance R 45, the other end of R46, the other end of R49 is connected with an end of resistance R 72 respectively, the other end of resistance R 72 is connected with the BOOT_INT_I2C terminals, the other end of described resistance R 47, the equal ground connection of the other end of R48; Described pin PGND ground connection, pin RVDD1 is connected with the DSP_3.3v terminals, and is in series with capacitor C 36 between pin PGND and the pin RVDD1; Pin PSCURR is connected with the NERROR terminals, and be in series with resistance R 50 between pin PSCURR and the DSP_3.3V, pin PSTEMP is connected with the DSP_3.3V terminals by resistance R 54, pin PR00 is connected with the DSP_3.3V terminals by resistance R 53, pin PR01 is connected with the DSP_3.3V terminals by resistance R 52, pin PR02 is connected with the DSP_3.3V terminals by resistance R 51, and pin PSTEMP is by resistance R 55 ground connection; Pin PWMVDD1 is connected with the PWMVDD terminals, and pin PWMVDD1 is connected with the DSP_3.3V terminals by resistance R 56, pin PWM0 is connected with terminals PWM1H by resistance R 4, pin PWM1 is connected with terminals PWM1L by resistance R 5, pin PWM2 is connected with terminals PWM2H by resistance R 7, pin PWM3 is connected with terminals PWM2L by resistance R 8, pin PWM4 is connected with terminals PWM_SUB+ by resistance R 9, pin PWM5 is connected with terminals PWM_SUB-by resistance R 10, pin PWM6 is connected with terminals PWM_LINE_L by resistance R 11, pin PWM7 is connected with terminals PWM_LINE_R by resistance R 12, pin PWMGND1, the equal ground connection of PWMGND2, be in series with capacitor C 46 between pin PWMVDD2 and the PWMGND2, pin PWMVDD1 is by capacitor C 13 in parallel, C37 is connected with pin PWMGND1, pin PLLAGND ground connection, pin XTAL1 is by capacitor C 53 ground connection, pin XTAL0 is by capacitor C 48 ground connection, and pin XTAL1 is connected with pin XTAL0 by crystal oscillator, pin PLLAVDD is connected with the DSP_1.8V terminals by inductance FB1, and pin PLLAVDD is by capacitor C 54 in parallel, C47 ground connection; Pin CGND1 ground connection, pin CVDD1 is connected with the DSP_1.8V terminals, and pin CVDD1 is by capacitor C 56 ground connection, described DSP digital signal processor also comprises the BAT54A chip, the AT24C16 chip, the BAT54A chip is provided with the first terminals and the second terminals and the 3rd terminals, described the first terminals are connected with the DSP_3.3V terminals, the first terminals also are connected with the DSP_REST terminals by resistance R 57, described the second terminals are connected with end pin NRSTOUT, described the 3rd terminals respectively with DSP_REST, NRESET connects, and the 3rd terminals are successively by resistance R 58, capacitor C 57 ground connection, described AT24C16 chip is provided with pin A0, A1, A2, GND, VCC, WP, SCL, SDA, pin A0, A1, A2, the equal ground connection of GND, pin VCC is connected with the DSP_3.3V terminals, pin WP is by resistance R 40 ground connection, the pin SCL of AT24C16 chip is connected with the pin SCL of BAT631H chip, and the pin SCL of AT24C16 chip is connected with the I2C_SCL terminals by resistance R 16, the pin SDA of AT24C16 chip is connected with the pin SDA of BAT631H chip, and the pin SDA of AT24C16 chip is connected with the I2C_SDA terminals by resistance R 2.

Further, described TSS module MCU comprises the BT1960 chip, the BT1960 chip is provided with end pin P00, P01, P02, P03, P04, P05, P06, P07, P12, P62, P63, P64, PF0, PF1, PF2, VSS, PG2, PG1, VCC, C, described end pin P12 is connected with the DBG terminals, described end pin P07 is connected with the IR terminals, described end pin P06 is connected with the I2C_SDA terminals, described end pin P05 is connected with the I2C_SCL terminals, described end pin P04 is connected with the INT04/ANO4/SIN terminals, described end pin P03 is connected with the INT03/AN03/SOT terminals, described end pin P02 is connected with the INT02/AN02/SCK/KEY terminals, described end pin P01 is connected with the P01/AN01/POWER terminals, described end pin P00 is connected with the P00/AN00 terminals, described end pin P64 is connected with the P64/EC1 terminals, and end pin P12 is connected with the MCU_3.3V terminals by resistance R 85, end pin P06 is connected with the MCU_3.3V terminals by resistance R 80, end pin P05 is connected with the MCU_3.3V terminals by resistance R 81, end pin P02 is connected with the MCU_3.3V terminals by resistance R 3; Pin PF1 is connected with the PF0/X0 terminals, and pin PF0 is connected with the PF1/X1 terminals, and pin PG2 is connected with the A terminals, and pin PG1 is connected with the B terminals, and pin PF2 is connected with the RES terminals, and pin P62 is connected with the MUTE terminals; Pin VSS ground connection, pin VCC is connected with the MCU_3.3V terminals by inductance FB8, and pin VCC passes through capacitor C 30 ground connection, and pin PF2 passes through resistance R 71 and is connected with the MCU_3.3V terminals; Pin C is by capacitor C 10 ground connection, and pin P63 is connected with the DSP_REST terminals by resistance R 84, and pin P63 is connected with the RESETB terminals by R88.

Further, described TSS modular circuit also comprises power circuit, and described this power circuit provides 3.3V voltage for A/D converter DSP digital signal processor, TSS module MCU.

Further, described a kind of solid sound box also comprises subwoofer channel pwm power amplifying circuit and bass horn, and described pwm power amplifying circuit is connected with the TSS modular circuit.

Further, described a kind of solid sound box also comprises the main control MCU circuit, and described main control MCU circuit is provided with audio decoding circuit, and the main control MCU circuit and signal switches and the volume control circuit signal connects, and described MUC circuit is provided with USB interface, SD card interface.

All there are production in described process chip BAT631H, BAT54A chip, AT24C16 chip, BT1960 chip Shenzhen hundred safe Industrial Co., Ltd.s, and on sale for a long time.

The beneficial effects of the utility model are: the utility model becomes common voice signal the voice signal with three-dimensional stereopsis by the DSP digital signal processor, and the power amplification circuit by rear class and loudspeaker amplify voice signal and play, thereby produce preferably 3D stereo sound.

Description of drawings

Fig. 1 is the A/D converter circuit diagram of TSS module of the present utility model.

Fig. 2 is the circuit diagram of the DSP digital signal processor of TSS module of the present utility model.

Fig. 3 is the circuit diagram of the TSS module MCU of TSS module of the present utility model.

Fig. 4 is workflow diagram of the present utility model.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is described further.

Embodiment 1: referring to accompanying drawing 1 to Fig. 4.

A kind of solid sound box comprises two loudspeaker and audio frequency processing circuit, and described audio frequency processing circuit comprises signal switching and volume control circuit, TSS modular circuit, left and right acoustic channels PWM amplifying circuit; Described signal switching and volume control circuit change the acoustic current-meter signal that receives into the left and right acoustic channels current signal and pass to the TSS modular circuit, described TSS modular circuit comprises the A/D analog to digital converter, DSP digital signal processor and TSS module MCU, the A/D analog to digital converter changes the left and right acoustic channels circuit signal that receives into digital audio and video signals, and this digital audio and video signals passed to the DSP digital signal processor, described DSP digital signal processor is processed into the 3 D stereo acoustical signal with digital audio and video signals, and this 3 D stereo acoustical signal passed to TSS module MCU, TSS module MCU passes to left and right acoustic channels PWM amplifying circuit with the 3 D stereo acoustical signal, and described two loudspeaker are connected with the left and right acoustic channels amplifying circuit respectively.

Here TSS represents true surround sound, namely truly around sound.

The utility model is when implementing, at first switched by signal and volume control circuit receives sound circuit signal (receiving by AUX outer signal interface) from electronic product, signal switches and volume control circuit passes through Channel-shifted, the stereophonic signal of two sound channels about it is become, and pass to the TSS modular circuit by the left and right acoustic channels current signal, this TSS modular circuit changes simulated audio signal (being the left and right acoustic channels current signal) into digital audio and video signals by the A/D converter of itself, digital audio is through the DSP digital signal processor processes, formation has the 3 D stereo acoustical signal, the 3 D stereo acoustical signal has also comprised surround sound signal except left and right sound track signals; The DSP digital signal processor sends to TSS module MCU with the 3 D stereo acoustical signal of handling well, TSS module MCU passes to the 3 D stereo acoustical signal left and right acoustic channels PWM amplifying circuit and two loudspeaker again, just can play out by two loudspeaker to have stronger relief sound.

Further, described A/D converter comprises conversion chip ES7240, and this conversion chip ES7240 is provided with pin MO, MALK, VDDP, SDOUT, GNDD, VDDD, SCLK, LRCK, RESETB, AINL, REFQ, AINR, VDDA, GNDA, REFP, M1; Described pin MO, M1 connect and ground connection, and described pin VDDP connects the 3.3V_VP supply terminals, and described pin VDDD is connected with the 3.3V_VD supply terminals, and be provided with capacitor C 49 between pin VDDP and the VDDD, C50, C51, C52; The end of described capacitor C 51, C52 is connected with pin VDDD respectively, the equal ground connection of the other end of capacitor C 51, C52, and the end of described capacitor C 49, C50 is connected with pin VDDP respectively, the equal ground connection of the other end of described capacitor C 49, C50; Described pin VDDA connects the 3.3V_VA supply terminals, described pin GNDA ground connection, and be provided with capacitor C in parallel 39, C40 between pin VDDA and the pin GNDA; Described pin REFP is connected with capacitance group C41_42, the termination pin REFP of capacitance group C41_42, the other end ground connection of capacitance group C41_42; Described pin REFQ is connected with capacitance group C44_45, and the end of described capacitance group C44_45 is connected with pin REFQ, the other end ground connection of capacitance group C44_45; Described pin AINL is connected with capacitor C 71, resistance R 41, and an end of described capacitor C 71 is connected with pin AINL, and the other end of capacitor C 71 is connected with an end of resistance R 41, and the other end of described resistance R 41 is connected with the LOUT terminals; Described pin AINR is connected with capacitor C 72, resistance R 42, and an end of described capacitor C 72 is connected with pin AINR, and the other end of capacitor C 72 is connected with an end of resistance R 42, and the other end of resistance R 42 is connected with the ROUT terminals; Described A/D converter also comprises resistance R 13, R14, R43, R44 and capacitor C 69, C70, and an end of described resistance R 44, capacitor C 69 is connected with an end of described resistance R 41, the equal ground connection of the other end of described resistance R 44, capacitor C 69; One end of described resistance R 43, capacitor C 70 is connected with an end of described resistance R 42, the equal ground connection of the other end of described resistance R 43, capacitor C 70; One end of described resistance R 13 is connected with an end of described resistance R 41, another termination L_IN terminals of described resistance R 13, and an end of described resistance R 14 is connected with an end of described resistance R 42, and the other end of described resistance R 14 connects the R_IN terminals; Described pin MALK is connected with the MCLK terminals, and pin LRCK is connected with the LRCK terminals, and is in series with resistance R 28 between pin LRCK and the LRCK terminals; Pin SCLK is connected with the SCLK terminals, and be in series with resistance R 27 between pin SCLK and the SCLK terminals, pin SDOUT is externally connected with SDIN terminals, resistance R 17, resistance R 29 and 3.3V_VP terminals, wherein an end of resistance R 17 is connected with the SDOUT terminals, the other end of resistance R 17 is connected with the SDIN terminals, one end of resistance R 29 is connected with the SDOUT terminals, and the other end of resistance R 29 is connected with the 3.3V_VP terminals.

This A/D converter receives the left and right acoustic channels current signal by terminals R_IN and L_IN, by processing, is converted to digital audio and video signals, and externally exports by terminals ROUT and LOUT.

The DSP digital signal processor is recorded in respectively the surround sound (reflected sound and reverberation sound) that can embody presence in the stereophonic signal in the left and right sound channels, the DSP digital signal processor produces a resultant signal (R+L) with R, two signal plus of L, here R, L represent respectively right-channel signals, left channel signals, below roughly the same; And then the mutual underproduction of two signals are given birth to two differential signals (R-L) and (L-R), the resultant signal after the DSP digital signal processor will be processed, differential signal and environmental information on every side (reflecting sound field and reverberant field) offer people's ear.For microphone and conventional stero set and since the differential signal microphone of " L-R " and " R-L " " listen " less than, stereo component system can not copy, so playback time does not have spatial impression.The DSP digital signal processor will be processed differential signal and resultant signal, and final sound meets people's auditory system and spatial information is recovered.Thereby by to the recovery of true performance environment, strengthened stereophonic sound image, made the people from subjective dimensional orientation and the distribution of feeling acoustic image.

TSS has satisfied effect after treatment for on-the-spot recorded program (concert, film).If itself does not just give the ambient sound of people's presence in the program source of playing, as adopting the synthetic CD sheet of making of multichannel pre-recording and later stage, or computer synthesized voice, effect are just so obvious unlike live concerts.TSS can play the normal stereo program source, also can play the Dolby Surround coded program, also can process the monophonic signal source, builds the surrounding stereophonic field with spatial impression with stereo power amplifier and two audio amplifiers.

The audio amplifier of TSS is put and not restriction of listening location, even two audio amplifiers are put very closely, or walks about arbitrarily in the room, can hear the surrounding sound field that spatial impression is very strong.TSS can be combined into the sound equipment that a cover has surrounding sound with existing various stero sets.Practice shows the sound equipment that class is higher, more can embody the effect of TSS.We think, a pair of hundreds of unit has resource integrated audio amplifier to mix the TSS processor can to become 3 very high dimension surround sound home theater sound equipment systems of a cover cost performance, definitely meet state's human consumption principle preferably.

Further, described TSS module MCU comprises the BT1960 chip, the BT1960 chip is provided with end pin P00, P01, P02, P03, P04, P05, P06, P07, P12, P62, P63, P64, PF0, PF1, PF2, VSS, PG2, PG1, VCC, C, described end pin P12, P07, P06, P05, P04, P03, P02, P01, P00, P64 respectively with the DBG terminals, the IR terminals, the I2C_SDA terminals, the I2C_SCL terminals, the INT04/ANO4/SIN terminals, the INT03/AN03/SOT terminals, the INT02/AN02/SCK/KEY terminals, the P01/AN01/POWER terminals, the P00/AN00 terminals, the P64/EC1 terminals connect, and end pin P12, P06, P02 is respectively by resistance R 85, R80, R81, R3 is connected with the MCU_3.3V terminals, pin PF0, PF1, PG2, PG1, PF2, P62 respectively with the PF0/X0 terminals, the PF1/X1 terminals, the A terminals, the B terminals, the RES terminals, the MUTE terminals connect; Pin VSS ground connection, pin VCC is connected with the MCU_3.3V terminals by inductance FB8, and pin VCC passes through capacitor C 30 ground connection, and pin PF2 passes through resistance R 71 and is connected with the MCU_3.3V terminals; Pin C is by capacitor C 10 ground connection, and pin P63 is connected with DSP_REST terminals, RESETB terminals by resistance R 84, R88 respectively.

Subwoofer channel pwm power amplifying circuit and bass horn form the stereo power amplifier of bass; This solid sound box also can be processed the monophonic signal source except playing the normal stereo program source; After setting up stereo power amplifier, and two loudspeaker are built the surrounding stereophonic field with spatial impression.

By the main control MCU circuit is set, can be so that solid sound box can read storage music or audio files in the memory device by USB interface or SD card interface, after reading, carry out audio decoder by audio decoding circuit, be converted into the left and right acoustic channels decoded signal and export to signal switching and volume control circuit, in the present embodiment, audio decoding circuit can be decoded for 5 kinds of music formats.

The below is further described operation principle of the present utility model:

After the solid sound box start, switch and volume control circuit to signal by AUX outer signal interface input audio signal, or read music file in the memory device that is attached thereto by master control MUC, by audio decoding circuit it is decoded, and be converted into voice signal and pass to that signal switches and volume control circuit, signal switches and volume control circuit changes its processing into A/D converter that the left and right acoustic channels current signal passes to the TSS modular circuit again, A/D converter changes simulated audio signal (being the left and right acoustic channels current signal) into digital audio and video signals, and digital audio and video signals passed to the DSP digital signal processor, the DSP digital signal processor is again according to people's physiological characteristic, signal to input is made decomposition operation, the a series of processing such as time-delay, simulate except the front left and right sound channel signal, and fictionalize the rear surround sound signal, then deliver to the power amplification circuit of rear class by TSS module MCU, at last by 2.1 common audio amplifier reproduced sound, can't adopt multiple loudspeaker or adjust left at some, the right horn position produces in the stereosonic situation, can produce broader, grander sound field, make the people that a kind of sense of reality on the spot in person be arranged, it has utilized the principle of acoustics, different to the reflection of the signal in each space according to people's ear, reflected sound to two channel stereo signal, although the signal signal of echo is from the place ahead, what the people heard remains from from all directions.It has the advantage of a maximum is exactly only with two common audio amplifiers, also need the Doby coding, just can produce the playback effect of imitating 3D surround sound five-sound channel, and no matter where the hearer is sitting in, and all can experience the effect of the sort of shock of music hall.

Solid sound box of the present utility model is put and not restriction of listening location, even two audio amplifiers are put very closely, or the hearer walks about arbitrarily in the room, can hear the surrounding sound field that spatial impression is very strong.Can be combined into the sound equipment that a cover has surrounding sound with existing various stero sets.Practice shows the sound equipment that class is higher, more can embody the effect of TSS.

Below only be the application's preferred embodiment, equivalent technical solutions on this basis still falls into the application protection range.

Claims

1. a solid sound box comprises two loudspeaker and audio frequency processing circuit, it is characterized in that: described audio frequency processing circuit comprises signal switching and volume control circuit, TSS modular circuit, left and right acoustic channels PWM amplifying circuit; Described signal switching and volume control circuit change the acoustic current-meter signal that receives into the left and right acoustic channels current signal and pass to the TSS modular circuit, described TSS modular circuit comprises the A/D analog to digital converter, DSP digital signal processor and TSS module MCU, the A/D analog to digital converter changes the left and right acoustic channels current signal that receives into digital audio and video signals, and this digital audio and video signals passed to the DSP digital signal processor, described DSP digital signal processor is processed into the 3 D stereo acoustical signal with digital audio and video signals, and this 3 D stereo acoustical signal passed to TSS module MCU, TSS module MCU passes to left and right acoustic channels PWM amplifying circuit with the 3 D stereo acoustical signal, and described two loudspeaker are connected with left and right acoustic channels PWM amplifying circuit respectively.

2. a kind of solid sound box according to claim 1, it is characterized in that: described A/D converter comprises conversion chip ES7240, and this conversion chip ES7240 is provided with pin MO, MALK, VDDP, SDOUT, GNDD, VDDD, SCLK, LRCK, RESETB, AINL, REFQ, AINR, VDDA, GNDA, REFP, M1; Described pin MO, the equal ground connection of M1, described pin VDDP connects the 3.3V_VP supply terminals, described pin VDDD is connected with the 3.3V_VD supply terminals, and be provided with capacitor C 49 between pin VDDP and the VDDD, C50, C51, C52; One end of described capacitor C 51, the end of C52 are connected with pin VDDD respectively, the other end of capacitor C 51, the equal ground connection of the other end of C52, one end of described capacitor C 49, the end of C50 are connected with pin VDDP respectively, the other end of described capacitor C 49, the equal ground connection of the other end of C50; Described pin VDDA connects the 3.3V_VA supply terminals, described pin GNDA ground connection, and be provided with capacitor C in parallel 39, C40 between pin VDDA and the pin GNDA; Described pin REFP is connected with the capacitance group C41_42 that is comprised of capacitor C 41 and C42, the termination pin REFP of capacitance group C41_42, the other end ground connection of capacitance group C41_42; Described pin REFQ is connected with the capacitance group C44_45 that is comprised of C44 and C45, and the end of capacitance group C44_45 is connected with pin REFQ, the other end ground connection of capacitance group C44_45; Described pin AINL is connected with capacitor C 71, resistance R 41, and an end of described capacitor C 71 is connected with pin AINL, and the other end of capacitor C 71 is connected with an end of resistance R 41, and the other end of described resistance R 41 is connected with the LOUT terminals; Described pin AINR is connected with capacitor C 72, resistance R 42, and an end of described capacitor C 72 is connected with pin AINR, and the other end of capacitor C 72 is connected with an end of resistance R 42, and the other end of resistance R 42 is connected with the ROUT terminals; Described A/D converter also comprises resistance R 13, R14, R43, R44 and capacitor C 69, C70, and an end of described resistance R 44, an end of capacitor C 69 are connected with an end of described resistance R 41, the equal ground connection of the other end of the other end of described resistance R 44, capacitor C 69; One end of described resistance R 43, an end of capacitor C 70 are connected with an end of described resistance R 42, the equal ground connection of the other end of the other end of described resistance R 43, capacitor C 70; One end of described resistance R 13 is connected with an end of described resistance R 41, another termination L_IN terminals of described resistance R 13, and an end of described resistance R 14 is connected with an end of described resistance R 42, and the other end of described resistance R 14 connects the R_IN terminals; Described pin MALK is connected with the MCLK terminals, and pin LRCK is connected with the LRCK terminals, and is in series with resistance R 28 between pin LRCK and the LRCK terminals; Pin SCLK is connected with the SCLK terminals, and be in series with resistance R 27 between pin SCLK and the SCLK terminals, pin SDOUT is connected with between SDIN terminals and pin SDOUT and the SDIN terminals and is in series with resistance R 17, also comprise resistance R 29 and 3.3V_VP terminals, one end of resistance R 29 is connected with the SDOUT terminals, and the other end of resistance R 29 is connected with the 3.3V_VP terminals.

3. a kind of solid sound box according to claim 1, it is characterized in that: described DSP digital signal processor comprises process chip BAT631H, and described process chip BAT631H is provided with pin PWMVDD1, PWM0, PWM1, PWM2, PWM3, PWMGND1, PWMVDD2, PWM4, PWM5, PWM6, PWM7, PWMGND2, SPDIFRX, SPDIFTX, TEST, IRQA, IRQB, PGND, RVDD1, PSCURR, PSTEMP, PR00, PR01, PR02, SCK2, STD2, SC22, MCLK, CVDD, CGND, RGND, RVDD2, SCK, TI01, MIS0, MOSI, SCL, SDA, TI00, NRESET, NRSTOUT, CVDD1, CGND1, NSS, PLLAVDD, XTAL0, XTAL1, PLLAGND; Wherein, pin SCK2 is connected with the SCLK terminals, pin STD2 is connected with the SDIN terminals, pin SC22 is connected with the LRCK terminals, described pin MCLK is connected with resistance R 31, capacitor C 23, wherein the two ends of resistance R 31 are connected with the MCLK terminals with pin MCLK respectively, and an end of capacitor C 23 is connected with pin MCLK, the other end ground connection of capacitor C 23; Pin CVDD is connected with DSP_1.8V, pin CGND ground connection, and be provided with capacitor C 24, C25 between pin CVDD and the pin CGND, an end of capacitor C 24, the end of C25 are connected with pin CVDD respectively, and the other end of capacitor C 24, the other end of C25 are connected with CGND respectively; Pin RVDD2 is connected with DSP_3.3V, and be provided with capacitor C in parallel 27, C35 between pin RVDD2 and the pin CGND, one end of capacitor C 27, the end of C35 are connected with pin CGND respectively, and the other end of capacitor C 27, the other end of C35 are connected with RVDD2 respectively; Described pin TI01 is provided with resistance R 19 outward, the two ends of R19 are connected with the MUTE terminals with pin TI01 respectively, pin SPDIFRX is connected with terminals SPDIFRX, pin SPDIFTX is by resistance R 1 ground connection, pin TEST is by resistance R 32 ground connection, pin IRQA, be provided with resistance R 45 between the IRQB, R46, R47, R48, R49, R72, an end of resistance R 45 wherein, the end of R48 is connected with pin IRQA respectively, one end of resistance R 46, the end of R47 is connected with pin IRQB respectively, one end of resistance R 49 is connected with the DSP_3.3V terminals, the other end of resistance R 45, the other end of R46, the other end of R49 is connected with an end of resistance R 72 respectively, the other end of resistance R 72 is connected with the BOOT_INT_I2C terminals, the other end of described resistance R 47, the equal ground connection of the other end of R48; Described pin PGND ground connection, pin RVDD1 is connected with the DSP_3.3v terminals, and is in series with capacitor C 36 between pin PGND and the pin RVDD1; Pin PSCURR is connected with the NERROR terminals, and be in series with resistance R 50 between pin PSCURR and the DSP_3.3V, pin PSTEMP is connected with the DSP_3.3V terminals by resistance R 54, pin PR00 is connected with the DSP_3.3V terminals by resistance R 53, pin PR01 is connected with the DSP_3.3V terminals by resistance R 52, pin PR02 is connected with the DSP_3.3V terminals by resistance R 51, and pin PSTEMP is by resistance R 55 ground connection; Pin PWMVDD1 is connected with the PWMVDD terminals, and pin PWMVDD1 is connected with the DSP_3.3V terminals by resistance R 56, pin PWM0 is connected with terminals PWM1H by resistance R 4, pin PWM1 is connected with terminals PWM1L by resistance R 5, pin PWM2 is connected with terminals PWM2H by resistance R 7, pin PWM3 is connected with terminals PWM2L by resistance R 8, pin PWM4 is connected with terminals PWM_SUB+ by resistance R 9, pin PWM5 is connected with terminals PWM_SUB-by resistance R 10, pin PWM6 is connected with terminals PWM_LINE_L by resistance R 11, pin PWM7 is connected with terminals PWM_LINE_R by resistance R 12, pin PWMGND1, the equal ground connection of PWMGND2, be in series with capacitor C 46 between pin PWMVDD2 and the PWMGND2, pin PWMVDD1 is by capacitor C 13 in parallel, C37 is connected with pin PWMGND1, pin PLLAGND ground connection, pin XTAL1 is by capacitor C 53 ground connection, pin XTAL0 is by capacitor C 48 ground connection, and pin XTAL1 is connected with pin XTAL0 by crystal oscillator, pin PLLAVDD is connected with the DSP_1.8V terminals by inductance FB1, and pin PLLAVDD is by capacitor C 54 in parallel, C47 ground connection; Pin CGND1 ground connection, pin CVDD1 is connected with the DSP_1.8V terminals, and pin CVDD1 is by capacitor C 56 ground connection, described DSP digital signal processor also comprises the BAT54A chip, the AT24C16 chip, the BAT54A chip is provided with the first terminals and the second terminals and the 3rd terminals, described the first terminals are connected with the DSP_3.3V terminals, the first terminals also are connected with the DSP_REST terminals by resistance R 57, described the second terminals are connected with end pin NRSTOUT, described the 3rd terminals respectively with DSP_REST, NRESET connects, and the 3rd terminals are successively by resistance R 58, capacitor C 57 ground connection, described AT24C16 chip is provided with pin A0, A1, A2, GND, VCC, WP, SCL, SDA, pin A0, A1, A2, the equal ground connection of GND, pin VCC is connected with the DSP_3.3V terminals, pin WP is by resistance R 40 ground connection, the pin SCL of AT24C16 chip is connected with the pin SCL of BAT631H chip, and the pin SCL of AT24C16 chip is connected with the I2C_SCL terminals by resistance R 16, the pin SDA of AT24C16 chip is connected with the pin SDA of BAT631H chip, and the pin SDA of AT24C16 chip is connected with the I2C_SDA terminals by resistance R 2.

4. a kind of solid sound box according to claim 1, it is characterized in that: described TSS module MCU comprises the BT1960 chip, the BT1960 chip is provided with end pin P00, P01, P02, P03, P04, P05, P06, P07, P12, P62, P63, P64, PF0, PF1, PF2, VSS, PG2, PG1, VCC, C, described end pin P12 is connected with the DBG terminals, described end pin P07 is connected with the IR terminals, described end pin P06 is connected with the I2C_SDA terminals, described end pin P05 is connected with the I2C_SCL terminals, described end pin P04 is connected with the INT04/ANO4/SIN terminals, described end pin P03 is connected with the INT03/AN03/SOT terminals, described end pin P02 is connected with the INT02/AN02/SCK/KEY terminals, described end pin P01 is connected with the P01/AN01/POWER terminals, described end pin P00 is connected with the P00/AN00 terminals, described end pin P64 is connected with the P64/EC1 terminals, and end pin P12 is connected with the MCU_3.3V terminals by resistance R 85, end pin P06 is connected with the MCU_3.3V terminals by resistance R 80, end pin P05 is connected with the MCU_3.3V terminals by resistance R 81, end pin P02 is connected with the MCU_3.3V terminals by resistance R 3; Pin PF1 is connected with the PF0/X0 terminals, and pin PF0 is connected with the PF1/X1 terminals, and pin PG2 is connected with the A terminals, and pin PG1 is connected with the B terminals, and pin PF2 is connected with the RES terminals, and pin P62 is connected with the MUTE terminals; Pin VSS ground connection, pin VCC is connected with the MCU_3.3V terminals by inductance FB8, and pin VCC passes through capacitor C 30 ground connection, and pin PF2 passes through resistance R 71 and is connected with the MCU_3.3V terminals; Pin C is by capacitor C 10 ground connection, and pin P63 is connected with the DSP_REST terminals by resistance R 84, and pin P63 is connected with the RESETB terminals by R88.

5. a kind of solid sound box according to claim 1, it is characterized in that: described TSS modular circuit also comprises power circuit, described this power circuit provides 3.3V voltage for A/D converter DSP digital signal processor, TSS module MCU.

6. a kind of solid sound box according to claim 1, it is characterized in that: described a kind of solid sound box also comprises subwoofer channel pwm power amplifying circuit and bass horn, described pwm power amplifying circuit is connected with the TSS modular circuit.

7. a kind of solid sound box according to claim 1, it is characterized in that: described a kind of solid sound box also comprises the main control MCU circuit, described main control MCU circuit is provided with audio decoding circuit, the main control MCU circuit and signal switches and the volume control circuit signal connects, and described MUC circuit is provided with USB interface, SD card interface.