CN202886795U - Array substrate, peripheral circuit thereof and display device - Google Patents
Array substrate, peripheral circuit thereof and display device Download PDFInfo
- Publication number
- CN202886795U CN202886795U CN 201220601606 CN201220601606U CN202886795U CN 202886795 U CN202886795 U CN 202886795U CN 201220601606 CN201220601606 CN 201220601606 CN 201220601606 U CN201220601606 U CN 201220601606U CN 202886795 U CN202886795 U CN 202886795U
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- circuit
- layer
- base palte
- array base
- protecting layer
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Abstract
The utility model discloses an array substrate, a peripheral circuit thereof and a display device, belonging to the field of display technology, and aiming at avoiding the peripheral circuit being damaged by static electricity and improving the yield of the display device. The peripheral circuit of the array substrate comprises a circuit layer which is on the peripheral area on the substrate, and at least one circuit protecting layer which is formed on the substrate and is used for protecting the circuit layer, wherein the outmost circuit protecting layer formed on the substrate is an organic layer.
Description
Technical field
The utility model relates to the display technique field, relates in particular to a kind of peripheral circuit, array base palte and display device of array base palte.
Background technology
Show (Thin Film Transistor-Liquid Crystal Display at tft liquid crystal; TFT-LCD) in the peripheral circuit of array base palte; the equal matcoveredn of peripheral circuit that comprises controlling grid scan line and data signal line; after tft array substrate and color membrane substrates are to box technique; also comprise along the line of cut of color membrane substrates color film is cut away a part; make the peripheral circuit on the array base palte exposed outside, in order to carry out follow-up chip crimping supervisor.
Controlling grid scan line in the peripheral circuit and the protective seam of data signal line are generally the outer field passivation layer of TFT, and protective seam is thinner, and thickness is generally about several nanometers, and the passivation protection layer is monox or silicon nitride dielectric layer, and the hardness of this class insulation course is lower.Therefore; the passivation protection layer of and thinner thickness lower for hardness; after tft array substrate and color membrane substrates are to box; line of cut along color membrane substrates cuts color film; when exposing the peripheral circuit on the array base palte below it; easily data signal line and controlling grid scan line below the passivation protection layer are cut off, cause being connected chip and the TFT disconnection that the terminal place is connected with controlling grid scan line with data signal line, the reduction of liquid crystal indicator yields.
The more important thing is, along with display device resolution is more and more higher, the wiring on the array base palte is more and more; more and more intensive; for the TFT on the array base palte, the phenomenon that static discharges (Electro-Staticdischarge, ESD) damage peripheral circuit usually can occur.In the process of cutting color membrane substrates or in other situations, extraneous factor is larger on the impact of the data signal line below the protective seam or controlling grid scan line, in the situation that especially protective seam is thinner, and the easier stored charge of data signal line or controlling grid scan line.When data signal line and controlling grid scan line are not cut in the disconnected situation, electric charge on the TFT electrode easily runs up to higher voltage levvl, when the electrostatic charge on the electrode runs up to a certain degree, the source electrode, the drain electrode that separate TFT, just possible breakdown with the insulating thin layer of gate electrode, cause being short-circuited between source electrode, gate electrode, the drain electrode, even it is breakdown that the insulating thin layer between source electrode and the gate electrode does not have, also can cause source electrode and gate electrode to have voltage differences, so that the operating characteristic of TFT changes.
Prior art is by the protective seam of passivation layer as peripheral circuit, and at first thickness is not enough to protect peripheral circuit, easily causes ESD damage TFT; passivation layer is insulation course in addition; hardness is lower, easily damages peripheral circuit, causes reducing the yields of liquid crystal indicator.
The utility model content
The utility model embodiment provides a kind of peripheral circuit, array base palte and display device of array base palte, in order to avoid the peripheral circuit electrostatic damage, improves the yields of display device.
The peripheral circuit of a kind of array base palte that the utility model embodiment provides; comprise: be formed on the circuit layer that is positioned at outer peripheral areas on the substrate; also comprise: be formed on the described substrate at least one deck circuit protecting layer for the protection of described circuit layer; wherein, being formed on the circuit protecting layer that is positioned at outermost one deck on the described substrate is organic layer.
Preferably, the described thickness that is formed on all circuit protecting layer on the substrate is not more than the thick difference with circuit layer thickness of liquid crystal cell.
Preferably, all circuit protecting layer that are formed on the substrate are two-layer, are the first circuit protecting layer and second circuit protective seam;
Described the first circuit protecting layer is to be formed on the circuit protecting layer that is positioned at outermost one deck on the described substrate;
Described second circuit protective seam is the circuit protecting layer between described the first circuit protecting layer and circuit layer.
Preferably, described second circuit protective seam arranges with layer with the passivation layer that covers the thin film transistor (TFT) on the array base palte.
Preferably, described the first circuit protecting layer covers the whole outer peripheral areas of array base palte, or described the first circuit protecting layer covers the zone corresponding with described circuit layer.
Preferably, the photoresist layer of described the first circuit protecting layer for being made by organic material.
Preferably, described second circuit protective seam is silicon nitride or membranous layer of silicon oxide.
A kind of array base palte that the utility model embodiment provides comprises the peripheral circuit of described array base palte.
A kind of display device that the utility model embodiment provides comprises described array base palte.
The peripheral circuit of a kind of array base palte that the utility model embodiment provides comprises at least one deck circuit protecting layer that covers successively on the described peripheral circuit, and wherein, one deck circuit protecting layer is organic layer at least.Multi-protective layer can effectively protect peripheral circuit to avoid electrostatic influence.And protective seam can be organic layer, can effectively prevent from causing peripheral circuit to damage when the cutting color membrane substrates.
Description of drawings
The peripheral circuit schematic top plan view of the array base palte that Fig. 1 provides for the utility model embodiment;
The array base palte shown in Figure 1 that Fig. 2 provides for the utility model embodiment A-B to schematic cross-section;
Fig. 3 has the schematic cross-section of second circuit protective seam for what the utility model embodiment provided in array base palte increase shown in Figure 2;
The peripheral circuit cross-sectional view of the two-layer wiring of the array base palte that Fig. 4 provides for the utility model embodiment;
The individual layer wiring of the array base palte that Fig. 5 provides for the utility model embodiment comprises the peripheral circuit cross-sectional view of controlling grid scan line;
The second circuit protective seam that Fig. 6 provides for the utility model embodiment covers the array base palte schematic top plan view of whole outer peripheral areas;
The second circuit protective seam that Fig. 7 provides for the utility model embodiment covers the array base palte schematic top plan view of peripheral circuit.
Embodiment
The utility model embodiment provides a kind of peripheral circuit, array base palte and display device of array base palte, in order to avoid in color membrane substrates cutting technique process, the destruction of the peripheral circuit on the pair array substrate, and avoid peripheral circuit to be subjected to electrostatic influence and destroy, improve the yields of liquid crystal indicator.
Referring to Fig. 1, be color membrane substrates and the array base palte array base palte schematic top plan view after involutory, comprise array base palte 1 and color membrane substrates 2, the area of color membrane substrates 2 is less than the area of array base palte 1, color membrane substrates 2 is connected with array base palte by sealed plastic box 3 connections, the zone that is positioned at sealed plastic box 3 is viewing area 5, the zone that is positioned at outside the sealed plastic box 3 is outer peripheral areas 4, peripheral circuit is arranged on outer peripheral areas, peripheral circuit comprises circuit layer at least, described circuit layer comprises metal lead wire 40, and this metal lead wire can be controlling grid scan line or data signal line.
Array base palte shown in Figure 1 is the array base palte behind the cutting color membrane substrates.Being used in the circuit layer of peripheral circuit exposes out with the PAD zone 6 of chip crimping, and PAD zone 6 is shown in dotted line inner structure closed among Fig. 1.
The circuit layer of peripheral circuit is distributed with controlling grid scan line and data signal line at least.Controlling grid scan line is comprised of the lead-in wire that the grid of the TFT of pixel region on the array base palte extracts, data signal line is comprised of the lead-in wire that source electrode or the drain electrode of described TFT extracts, outer peripheral areas and PAD zone that controlling grid scan line and data signal line are positioned at array base palte expose outside, in order to carry out follow-up chip crimping, electric circuit inspection or make module (Module) etc.
The circuit layer outermost layer of existing peripheral circuit all has layer protective layer, but this protective seam is thinner, and hardness is lower.The utility model embodiment; by on the circuit layer of existing peripheral circuit, increasing at least one deck circuit protecting layer; to increase the thickness of circuit protecting layer on the peripheral circuit; avoid the destruction of the peripheral circuit on color membrane substrates cutting technique or other extraneous factor pair array substrates, and avoid the TFT on the ESD damage array base palte.
Specify the technical scheme that the utility model embodiment provides below by accompanying drawing.
Referring to Fig. 2, for array base palte shown in Figure 1 A-B to schematic cross-section.
Peripheral circuit comprises: be formed on the circuit layer 7 that is positioned at outer peripheral areas on the array base palte 1 and be positioned on the array base palte 1 the first circuit protecting layer 8 for the protection of circuit layer 7.
Be filled with liquid crystal molecule 9 between array base palte 1 and the color membrane substrates 2, consist of together the liquid crystal cell of sealing between array base palte 1 and color membrane substrates 2 and the sealed plastic box 3.
Preferably, this first circuit protecting layer 8 is organic layer, namely is made by organic material.The first circuit protecting layer that organic material is made can effectively protect peripheral circuit to avoid the impact of static, and the peripheral circuit that is positioned at the first circuit protecting layer below is not easy the static electricity gathered lotus.
In specific implementation process; preferably; the first circuit protecting layer is to be made after the every other functional film layer on having made array base palte; for example; apply the photoresist layer of one deck preset thickness at the tft array substrate that is formed with passivation layer, by exposure, developing process flow process, the photoresist layer of viewing area on the array base palte is developed to fall; the photoresist layer of outer peripheral areas stays, as the utility model the first circuit protecting layer.
Described photoresist layer is made by organic material.For example photoresist layer mainly is made by organic resin (resin).Organic resin can be benzocyclobutene (BCB), polyamide, acrylate resin, also can be other organic materials.
Preferably, referring to Fig. 3, peripheral circuit also comprises: the second circuit protective seam 10 between the first circuit protecting layer 8 and circuit layer 7.
Preferably, this second circuit protective seam 10 can be insulation course, for example can be gate insulator or passivation layer in making the TFT process, perhaps is the lamination of the two.
Preferably, described second circuit protective seam arranges with layer with the passivation layer that covers the thin film transistor (TFT) on the array base palte.
Preferably; the circuit protecting layer of the outermost one deck on the circuit layer 7; the thickness of the first circuit protecting layer 8 as shown in Fig. 2 or 3 is not more than the thick difference with circuit layer thickness of liquid crystal cell; preferably, the thickness of the first circuit protecting layer 8 is slightly less than liquid crystal cell thick (liquid crystal cell is thick also be between color membrane substrates 2 and the array base palte 1 vertical range).Because because liquid crystal cell is thick generally in micron dimension, such as several microns, and the thickness of the circuit layer of peripheral circuit is in nanometer scale, such as tens nanometers.
The utility model; can effectively protect peripheral circuit not to be subjected to the interference of external electromagnetic signal for thickness several microns circuit protecting layer; and the impact that is not subjected to static; be not easy to gather electrostatic charge on data signal line in the peripheral circuit or the controlling grid scan line, the TFT that links to each other with controlling grid scan line with data signal line on the array base palte is not easy by electrostatic breakdown.In addition, when can effectively preventing from cutting color membrane substrates, several microns circuit protecting layer will be positioned at circuitry cuts below the circuit protecting layer for thickness.
The circuit protecting layer that the utility model embodiment provides is positioned at the respective regions except the chip crimp region on the circuit layer.Such as Fig. 2 and Fig. 3, the chip crimp region is exposed outside, is convenient to and the chip crimping.
The lead-in wire that comprises the circuit layer of data signal line and controlling grid scan line has two kinds of wire laying modes, double-deck alternately wire laying mode and individual layer wire laying mode.
The below is elaborated to circuit layer and the double-deck alternately circuit layer of wiring of the individual layer wiring that the utility model embodiment provides.
Referring to Fig. 4, the circuit layer of the two-layer equation wiring that provides for the utility model embodiment, this circuit layer be on the array base palte shown in Figure 1 C-D to sectional view, comprising:
Be formed on the controlling grid scan line 11 that is positioned at the circuit layer zone on the array base palte 1, be positioned at the gate insulator 12 on the controlling grid scan line 11, and be positioned at the data signal line 13 on the gate insulator 12;
Be positioned at the second circuit protective seam 10 on the data signal line 13;
Be positioned at the first circuit protecting layer 8 on the second circuit protective seam 10;
Wherein, in the crack of data signal line 13 between controlling grid scan line 11, and be positioned at different layers with controlling grid scan line 11, such structure can be avoided crosstalking of data signal line 13 and controlling grid scan line 11 circuit signals.
In the process of actual fabrication circuit layer, described two-layer wiring formula circuit layer also comprises: the semiconductor layer between gate insulator 12 and data signal line 13, because this semiconductor layer is not applied in any signal, also can be used as insulation course, as the semiconductor layer of insulation course, do not affect the work of peripheral circuit.
Referring to Fig. 5, the circuit layer that the single-layer type that provides for the utility model embodiment connects up comprises:
Be positioned at the controlling grid scan line 11 of outer peripheral areas on the array base palte 1;
Be positioned at the gate insulator 12 on the controlling grid scan line 11;
Be positioned on the array base palte 1 or the data signal line 13 of gate insulator 12;
Controlling grid scan line 11 and data signal line 13 are positioned at the zones of different of array base palte 1.
Be positioned at the second circuit protective seam 10 on controlling grid scan line 11 and the data signal line 13;
Be positioned at the first circuit protecting layer 8 on the second circuit protective seam 10;
Second circuit protective seam 10 and the first circuit protecting layer 8 be cover gate sweep trace 11 and data signal line 13 all.
Be positioned at the second circuit protective seam 10 on the data signal line 13, this protective seam can be the insulation courses such as silicon nitride layer or silicon oxide layer (SiNx layer or SiOx layer).
Can find out that data signal line 13 has two-layer protective seam, second circuit protective seam 10 and the first circuit protecting layer 8.Controlling grid scan line 11 has the three-layer protection layer, except second circuit protective seam 10 and the first circuit protecting layer 8, also comprises the gate insulator 12 that is positioned on the controlling grid scan line 11.Only have layer protective layer and controlling grid scan line that the circuit layer of two-layer protective seam is arranged with respect to the prior art data signal line, obviously increased the thickness of protective seam.Effectively avoid in the process of cutting color membrane substrates, the lead-in wire in the circuit layer being cut off, and effectively reduce static to the impact of the peripheral circuit of protective seam below, improve the yields of tft array substrate.
Certainly, individual layer wiring data signal line and controlling grid scan line not necessarily are arranged on the same side of the outer peripheral areas of array base palte, can be arranged on the not homonymy in array substrate peripheral zone.
Preferably, the set-up mode of the first circuit protecting layer in the array substrate peripheral zone that provide of the utility model embodiment can have multiple.
Referring to Fig. 6, the first circuit protecting layer 8 can cover the whole outer peripheral areas of array base palte, but does not cover the PAD zone of circuit layer.Such set-up mode, the first circuit protecting layer can pair array substrate peripheral zone other circuit or other structures play certain protective role.
Referring to Fig. 7, the first circuit protecting layer 8 only covers zone corresponding to circuit layer.
Perhaps the first circuit protecting layer only covers zone corresponding with data signal line in the circuit layer and/or the corresponding zone of controlling grid scan line.
A kind of array base palte that the utility model embodiment provides comprises the peripheral circuit of described array base palte.A kind of display device that the utility model embodiment provides comprises described array base palte.This display device can be the display device such as liquid crystal panel, liquid crystal display, LCD TV, oled panel, OLED display, OLED TV or Electronic Paper.
In sum, the utility model embodiment provides a kind of peripheral circuit of array base palte, comprises the circuit layer of outer peripheral areas, and this circuit layer comprises multilayer peripheral circuit protective seam at least, and the peripheral circuit protective seam is thicker, avoids extraneous factor to the damage of peripheral circuit.Wherein, one deck circuit protecting layer is organic layer at least.Multi-protective layer can effectively protect peripheral circuit to avoid electrostatic influence.And protective seam can be organic layer, can effectively prevent from causing peripheral circuit to damage when the cutting color membrane substrates, and organic layer belongs to insulation course, avoids the damage of static pair array substrate TFT, has improved the yield rate of LCD.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (9)
1. the peripheral circuit of an array base palte; comprise: be formed on the circuit layer that is positioned at outer peripheral areas on the substrate; it is characterized in that; also comprise: be formed on the described substrate at least one deck circuit protecting layer for the protection of described circuit layer; wherein, being formed on the circuit protecting layer that is positioned at outermost one deck on the described substrate is organic layer.
2. peripheral circuit according to claim 1 is characterized in that, the described thickness that is formed on all circuit protecting layer on the substrate is not more than the thick difference with circuit layer thickness of liquid crystal cell.
3. peripheral circuit according to claim 2 is characterized in that, all circuit protecting layer that are formed on the substrate are two-layer, is the first circuit protecting layer and second circuit protective seam;
Described the first circuit protecting layer is to be formed on the circuit protecting layer that is positioned at outermost one deck on the described substrate;
Described second circuit protective seam is the circuit protecting layer between described the first circuit protecting layer and circuit layer.
4. peripheral circuit according to claim 3 is characterized in that, described second circuit protective seam arranges with layer with the passivation layer that covers the thin film transistor (TFT) on the array base palte.
5. peripheral circuit according to claim 1 is characterized in that, described the first circuit protecting layer covers the whole outer peripheral areas of array base palte, or described the first circuit protecting layer covers the zone corresponding with described circuit layer.
6. according to claim 3 or 4 described peripheral circuits, it is characterized in that the photoresist layer of described the first circuit protecting layer for being made by organic material.
7. according to claim 3 or 4 described peripheral circuits, it is characterized in that, described second circuit protective seam is silicon nitride or membranous layer of silicon oxide.
8. an array base palte is characterized in that, comprises the described peripheral circuit of the arbitrary claim of claim 1-7.
9. a display device is characterized in that, comprises array base palte claimed in claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220601606 CN202886795U (en) | 2012-11-14 | 2012-11-14 | Array substrate, peripheral circuit thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220601606 CN202886795U (en) | 2012-11-14 | 2012-11-14 | Array substrate, peripheral circuit thereof and display device |
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| Publication Number | Publication Date |
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| CN202886795U true CN202886795U (en) | 2013-04-17 |
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| CN 201220601606 Expired - Lifetime CN202886795U (en) | 2012-11-14 | 2012-11-14 | Array substrate, peripheral circuit thereof and display device |
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| CN (1) | CN202886795U (en) |
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| CN104078469A (en) * | 2014-06-17 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method, display panel and display device |
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| CN104834143A (en) * | 2015-06-03 | 2015-08-12 | 合肥京东方光电科技有限公司 | Array substrate, preparation method of array substrate and display device |
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| CN108508663A (en) * | 2018-03-14 | 2018-09-07 | 深圳市华星光电技术有限公司 | Array substrate, display panel and display device |
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- 2012-11-14 CN CN 201220601606 patent/CN202886795U/en not_active Expired - Lifetime
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| CN104078469B (en) * | 2014-06-17 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method, display panel and display device |
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| CN104834143A (en) * | 2015-06-03 | 2015-08-12 | 合肥京东方光电科技有限公司 | Array substrate, preparation method of array substrate and display device |
| US9946105B2 (en) | 2015-06-03 | 2018-04-17 | Boe Technology Group Co., Ltd. | Opposed substrate, method for fabricating the same and display device |
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| WO2017045367A1 (en) * | 2015-09-15 | 2017-03-23 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| CN108508663A (en) * | 2018-03-14 | 2018-09-07 | 深圳市华星光电技术有限公司 | Array substrate, display panel and display device |
| CN109659324A (en) * | 2018-12-18 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and preparation method thereof |
| CN109659324B (en) * | 2018-12-18 | 2021-01-15 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
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Granted publication date: 20130417 |