CN202838910U - Led display screen - Google Patents

Led display screen Download PDF

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Publication number
CN202838910U
CN202838910U CN2012203742705U CN201220374270U CN202838910U CN 202838910 U CN202838910 U CN 202838910U CN 2012203742705 U CN2012203742705 U CN 2012203742705U CN 201220374270 U CN201220374270 U CN 201220374270U CN 202838910 U CN202838910 U CN 202838910U
Authority
CN
China
Prior art keywords
poe
management system
display screen
led display
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2012203742705U
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Chinese (zh)
Inventor
叶华杰
张超龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN2012203742705U priority Critical patent/CN202838910U/en
Application granted granted Critical
Publication of CN202838910U publication Critical patent/CN202838910U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Control Of El Displays (AREA)

Abstract

Disclosed in the utility model is an LED display screen that comprises an FPGA core control circuit (1), an LED dot matrix display screen (2), an EEPROM memory (3), an SDRAM internal memory (4), a clock management system (5), an ethernet controller (6), and an ethernet interface (7). The ethernet interface is connected with the ethernet controller (6); the ethernet controller is connected with the FPGA core control circuit (1); and the FPGA core control circuit is respectively connected with the LED dot matrix display screen (2), the EEPROM memory (3), the SDRAM internal memory (4), and the clock management system (5). In addition, the LED display screen also includes a POE and a DC-DC system (8), a lithium battery (9), and a power and battery management system (10); the POE and a DC-DC system (8) is connected with the ethernet interface (7) and the power and battery management system (10); and the power and battery management system (10) is connected with the lithium battery (9). The provided LED display screen is based on the POE system and can work normally without the need of connection of an external power supply.

Description

LED display
Technical field
The utility model relates to LED display.
Background technology
LED display is a kind of display mode of passing through the control semiconductor light-emitting-diode, is comprised of a lot of normally red light emitting diodes, leans on the light on and off of lamp to show character.Be used for the display screen of the various information such as display text, figure, image, animation.
Along with the progress of science and technology, the LED display technology is also constantly updating.Common LED display only has the function of demonstration, and some LED display has network communication function at present, can network and revise the displaying contents of LED display, and it is quite convenient to operate.But at present the LED display of networking is connected with common router by netting twine, and needing simultaneously to connect external power source could work, and comes LED display is powered by external power source during work, causes complexity of internal circuit, and aerial lug is more in disorder.
The utility model content
The technical problems to be solved in the utility model is that a kind of LED display based on the POE system is provided.
Technical solution of the present utility model is, a kind of LED display with following structure is provided, comprise the FPGA(field programmable gate array) core control circuit, LED dot matrix display screen curtain, eeprom memory (EEPROM (Electrically Erasable Programmable Read Only Memo)), SDRAM(synchronous dynamic random) internal memory, Clock management system, ethernet controller, Ethernet interface, lithium battery and power supply and battery management system; Described Ethernet interface is connected with ethernet controller, described ethernet controller is connected with the fpga core control circuit, and described fpga core control circuit is connected with LED dot matrix display screen curtain, eeprom memory, sdram memory and Clock management system respectively; Comprise that also (POE is based on electric power system or the active Ethernet of LAN (Local Area Network) for POE and DC-DC system, sometimes also be called POE for short, this is the newest standards standard that transmits data and electric power when utilizing existing standard ethernet transmission cable, and has kept the compatibility with existing Ethernet system and user); Described POE is connected with Ethernet interface with the DC-DC system, and described POE is connected with power supply with the DC-DC system and is connected with battery management system, and described power supply is connected with lithium battery with battery management system.
After adopting above structure, LED display of the present utility model compared with prior art, has the following advantages:
Because LED display of the present utility model also comprises POE and DC-DC system, during use, by netting twine Ethernet interface is connected with the POE router, the POE router can be to POE equipment transmission data and transferring electric power, so that need not to connect external power supply, the utility model LED display just can work, thereby so that internal wiring is simpler, external connection is cleaner and tidier; Described accumulator is back-up source, and when POE network normal power supply, if LED display is closed or during underloading, the POE network can charge to accumulator, when the POE network was stopped power supply, battery discharging can work on LED display.
Description of drawings
Fig. 1 is the circuit block diagram of LED display of the present utility model.
Shown in the figure: 1, fpga core control circuit, 2, LED dot matrix display screen curtain, 3, eeprom memory, 4, sdram memory, 5, Clock management system, 6, ethernet controller, 7, Ethernet interface, 8, POE and DC-DC system, 9, lithium battery, 10, power supply and battery management system.
Embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
See also shown in Figure 1, LED display of the present utility model comprises fpga core control circuit 1, LED dot matrix display screen curtain 2, eeprom memory 3, sdram memory 4, Clock management system 5, ethernet controller 6, Ethernet interface 7, POE and DC-DC system 8, lithium battery 9 and power supply and battery management system 10.
Described Ethernet interface 7 is connected with ethernet controller 6, described ethernet controller 6 is connected with fpga core control circuit 1, and described fpga core control circuit 1 is connected with the Clock management system with LED dot matrix display screen curtain 2, eeprom memory 3, sdram memory 4 respectively and is connected.Described POE is connected with the DC-DC system and is connected with Ethernet interface 7, and described POE is connected with the DC-DC system also to be connected with battery management system with power supply and is connected, and described power supply is connected with battery management system and is connected with lithium battery 9.
During use, by netting twine Ethernet interface is connected with the POE router, during POE network normal power supply, to LED display the transmission of data and electric power, if LED display is closed or during underloading, the POE network charges to accumulator; When the POE network was stopped power supply, battery discharging worked on LED display.

Claims (1)

1. a LED display comprises fpga core control circuit (1), LED dot matrix display screen curtain (2), eeprom memory (3), sdram memory (4), Clock management system (5), ethernet controller (6), Ethernet interface (7); Described Ethernet interface (7) is connected with ethernet controller (6), described ethernet controller (6) is connected with fpga core control circuit (1), and described fpga core control circuit (1) is connected 5 with LED dot matrix display screen curtain (2), eeprom memory (3), sdram memory (4) with the Clock management system respectively) be connected; It is characterized in that: also comprise POE and DC-DC system (8), lithium battery (9) and power supply and battery management system (10); Described POE is connected 8 with the DC-DC system) be connected with Ethernet interface (7), described POE is connected 8 with the DC-DC system) also be connected 10 with power supply with battery management system) be connected, described power supply is connected 10 with battery management system) be connected with lithium battery (9); POE in described POE and the DC-DC system (8) refers to the electric power system based on LAN (Local Area Network).
CN2012203742705U 2012-07-31 2012-07-31 Led display screen Expired - Fee Related CN202838910U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012203742705U CN202838910U (en) 2012-07-31 2012-07-31 Led display screen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012203742705U CN202838910U (en) 2012-07-31 2012-07-31 Led display screen

Publications (1)

Publication Number Publication Date
CN202838910U true CN202838910U (en) 2013-03-27

Family

ID=47950556

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012203742705U Expired - Fee Related CN202838910U (en) 2012-07-31 2012-07-31 Led display screen

Country Status (1)

Country Link
CN (1) CN202838910U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107578745A (en) * 2016-07-04 2018-01-12 上海和辉光电有限公司 FPGA device and the AMOLED display circuits using the device
US10389540B2 (en) 2014-10-17 2019-08-20 Extremely Low Energy Limited Power over ethernet devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10389540B2 (en) 2014-10-17 2019-08-20 Extremely Low Energy Limited Power over ethernet devices
CN107578745A (en) * 2016-07-04 2018-01-12 上海和辉光电有限公司 FPGA device and the AMOLED display circuits using the device

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130327

Termination date: 20130731