CN202818314U - RRU clock test window - Google Patents
RRU clock test window Download PDFInfo
- Publication number
- CN202818314U CN202818314U CN2012204750342U CN201220475034U CN202818314U CN 202818314 U CN202818314 U CN 202818314U CN 2012204750342 U CN2012204750342 U CN 2012204750342U CN 201220475034 U CN201220475034 U CN 201220475034U CN 202818314 U CN202818314 U CN 202818314U
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- test
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- clock
- rru
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Abstract
The utility model discloses an RRU clock test window, which comprises a signal transceiver board interface circuit used for accessing test signals output by an RRU transceiver board and a test window interface circuit connected with the signal transceiver board interface circuit and used for accessing the test signals and outputting the test signals to external test equipment for external test. According to the utility model, the recovery performance of a clock is tested through the RRU clock test window without the need to open an RRU housing, and wire flying is carried out on the signal transceiver board; and meanwhile the signal damage is reduced, the test difficulty and the environment construction difficulty are lowered, and the test efficiency and the reliability of test results are greatly improved. Moreover, when the network management operation and maintenance receives a clock-related warning, the test window can be served as a detection port of clock-related faults, an RRU does not need to be disassembled, related faults can be positioned by a portable instrument, and the cost of engineering maintenance can be reduced.
Description
Technical field
The present invention relates to wireless telecommunication system, particularly base station radio frequency remoter unit external interface function and definition.
Background technology
Distributed base station mainly is comprised of baseband processing unit BBU and radio frequency remote unit RRU.RRU (Remote Radio Unit) needs and BBU or RRU (in the RRU cascade situation) carry out clock synchronous, so that all basic station over network is synchronous, synchronous reference signal mainly is 61.44MHz and 10ms.61.44MHz be used for the detection of frequency accuracy and stability, 10ms is used for detecting lock in time.After the frequency deviation of clock signal and phase deviation acquire a certain degree, system can't work, and other co-frequency cell is produced interference.
At present, without the clock test window, can not support the clock interface of testing on the RRU 26S Proteasome Structure and Function.As testing the RRU net synchronization capability, take the RRU shell apart, take transmitting-receiving letter veneer apart, contrast schematic diagram and PCB find the pin of 61.44MHz and 10ms, manual fly line, the welding standard interface is from the port slits such as LMT and the external testing Instrument connection; Or directly draw by unnecessary hardware resource in the LMT interface.Every RRU complete machine to be measured is all repeated this work, and after RRU support cascade, difficulty of test will increase severely.According to existence conditions, the Commercial deployment test also can't be able to strong checking to the index of declaring of clock synchronous, is unfavorable for the strong competition of advantage index.Open after the station arranges net, when the webmaster Operation and Maintenance receives the relevant alarm of base station clock and affects, can only dismantle the position of standing firm under the complete machine, engineering maintenance difficulty and cost are larger.
Summary of the invention
The purpose of this utility model is to provide a kind of RRU clock test window, come the test clock restorability by RRU clock test window, do not need to open the RRU shell, at the board for receiving and sending message fly line, reduced simultaneously signal impairment, reduce difficulty of test and environmental structure difficulty, greatly improved the reliability of testing efficiency and test result; And after the webmaster Operation and Maintenance received the relevant alarm of clock, this testing window can be used as the detection port of clock dependent failure, need not to dismantle RRU, can utilize portable apparatus location dependent failure, had reduced the engineering maintenance expense.
According to an aspect of the present utility model, a kind of RRU clock test window is provided, comprising:
The board for receiving and sending message interface circuit is used for the test signal that access RRU board for receiving and sending message is exported;
The testing window interface circuit that connects described board for receiving and sending message interface circuit is used for accessing described test signal, and exports it to external test facility, in order to carry out external testing.
Further, described board for receiving and sending message interface circuit comprises time external interface and frequency external interface.
Preferably, described time external interface comprises:
The 10ms external interface that connects board for receiving and sending message FPGA is for the test signal of the 10ms that accesses FPGA output;
The PLL61.44MHz external interface that connects board for receiving and sending message first order phase-locked loop circuit is for the test signal of the debounce that accesses the output of first order phase-locked loop circuit.
Preferably, described frequency external interface comprises:
Connect successively the FPGA of board for receiving and sending message and the FPGA61.44MHz external interface of clock buffer, be used for the test signal of the 61.44MHz of access FPGA output;
The local oscillator LO external interface that connects the board for receiving and sending message frequency mixer is used for the test signal that the access frequency mixer is exported.
Further, described testing window interface circuit comprises time detecting interface and frequency detecting interface.
Preferably, described time detecting interface comprises:
The 10ms that connects described 10ms external interface by the clock cable detects interface, is used for exporting the test signal of described 10ms to external test facility;
The PLL61.44MHz that connects described PLL61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described debounce to external test facility.
Preferably, described frequency detecting interface comprises:
The FPGA61.44MHz that connects described FPGA61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described 61.44MHz to external test facility;
The local oscillator LO that connects described local oscillator LO external interface by the clock cable detects interface, is used for exporting the test signal of described frequency device output to external test facility.
Preferably, described board for receiving and sending message interface circuit is arranged on the veneer.
Preferably, described testing window interface circuit is positioned on the RRU shell.
Preferably, described testing window interface circuit is positioned at RRU upper half shell handle one side.
Compared with prior art, the beneficial effects of the utility model are:
1. come the test clock restorability by RRU clock test window, do not need to open the RRU shell, at the board for receiving and sending message fly line.
2. behind the employing standard interface, so that the signal transmission path impedance obtains coupling, reduce signal impairment, also reduced difficulty of test and environmental structure difficulty simultaneously.
3. in product maintenance, Commercial deployment test and version test, improved greatly the reliability of testing efficiency and test result.
4. after the webmaster Operation and Maintenance received the relevant alarm of clock, this testing window can be used as the detection port of clock dependent failure, need not to dismantle RRU, can utilize portable apparatus location dependent failure, had reduced the engineering maintenance expense.
Description of drawings
Fig. 1 is a kind of RRU clock test window construction figure that the utility model provides;
Fig. 2 is a kind of board for receiving and sending message and the test window connection layout that the utility model provides.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present utility model is elaborated, should be appreciated that following illustrated preferred embodiment only is used for description and interpretation the present invention, and be not used in restriction the utility model.
Fig. 1 has shown that the utility model embodiment provides a kind of RRU clock test window construction figure, as shown in Figure 1, the utility model proposes a kind of clock test window design: the clock test window is positioned at upper half shell handle one side of RRU, and signal is directly drawn from the wiring of transmitting-receiving letter veneer.As shown in Figure 2, in this window, there are FPGA61.44MHz, PLL61.44MHz, local oscillator LO and 10ms to detect interface.Wherein PLL61.44MHz and 10ms detect and are used for synchronism detection; Two signals in FPGA61.44MHz and local oscillator LO and front are finished fault location jointly; In the RRU housing, be connected with board for receiving and sending message by clock line, guide clock signal to be measured into veneer edge interface (interface position is not limited to the veneer edge, can in any position of veneer) by PCB cabling and clock signal buffer in the board for receiving and sending message.As illustrated in fig. 1 and 2.26S Proteasome Structure and Function to each interface is described as follows:
The 61.44MHz output of FPGA61.44MHz:FPGA output is by the clock buffer with phase-locked loop, tell one the tunnel as clock rate testing signal FPGA61.44MHz, clock cable is caused the external interface of certain point in edge or the plate by PCB veneer cabling, link to each other with clock test window interface by clock line, the interface of testing window can link to each other in external meters and test.
PLL61.44MHz:PLL61.44MHz directly draws from the output of first order phase-locked loop, detect through the clock signal situation after the first order phase-locked loop debounce, clock cable is caused the external interface of certain point in edge or the plate by PCB veneer cabling, link to each other with clock test window interface by clock line, the interface of testing window can link to each other in external meters and test.
Local oscillator LO: the test port of frequency mixer local oscillation signal is connected up directly by transmitting-receiving letter veneer, cause the external interface of certain point in edge or the plate, link to each other with clock test window interface by clock line, the interface of testing window can link to each other in external meters and test.
10ms detects: FPGA is generated the clock signal of 10ms, by the wiring of transmitting-receiving letter veneer, cause the external interface of certain point in edge or the plate, link to each other with clock test window interface by clock line, the interface of testing window can be tested in external meters is continuous.
Fig. 2 has shown that the utility model provides a kind of board for receiving and sending message and test window connection layout, and as shown in the figure, a kind of board for receiving and sending message and test window connection layout comprise:
The board for receiving and sending message interface circuit is used for the test signal that access RRU board for receiving and sending message is exported;
The testing window interface circuit that connects described board for receiving and sending message interface circuit is used for accessing described test signal, and exports it to external test facility, in order to carry out external testing.
Further, described board for receiving and sending message interface circuit comprises time external interface and frequency external interface.
Preferably, described time external interface comprises:
The 10ms external interface that connects board for receiving and sending message FPGA is for the test signal of the 10ms that accesses FPGA output;
The PLL61.44MHz external interface that connects board for receiving and sending message first order phase-locked loop circuit is for the test signal of the debounce that accesses the output of first order phase-locked loop circuit.
Preferably, described frequency external interface comprises:
Connect successively the FPGA of board for receiving and sending message and the FPGA61.44MHz external interface of clock buffer, be used for the test signal of the 61.44MHz of access FPGA output;
The local oscillator LO external interface that connects the board for receiving and sending message frequency mixer is used for the test signal that the access frequency mixer is exported.
Further, described testing window interface circuit comprises time detecting interface and frequency detecting interface.
Preferably, described time detecting interface comprises:
The 10ms that connects described 10ms external interface by the clock cable detects interface, is used for exporting the test signal of described 10ms to external test facility;
The PLL61.44MHz that connects described PLL61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described debounce to external test facility.
Preferably, described frequency detecting interface comprises:
The FPGA61.44MHz that connects described FPGA61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described 61.44MHz to external test facility;
The local oscillator LO that connects described local oscillator LO external interface by the clock cable detects interface, is used for exporting the test signal of described frequency device output to external test facility.
Be elaborated below in conjunction with drawings and Examples:
Case study on implementation 1, the 10ms phase information detects, as depicted in figs. 1 and 2:
Step 1: on transmitting-receiving letter veneer, directly RRU interface FPGA corresponding pin PCB layout is drawn, at the veneer edge or inner by interface output, directly be connected with clock test window pin by clock line again.
Step 2: the 10ms output port links to each other with oscilloscope input bnc interface by the test cable, as measured signal.
Case study on implementation 2,10ms is as next stage RRU 10ms reference.As depicted in figs. 1 and 2:
Step 1: the 10ms signal by the test cable, is connected to oscillographic bnc interface.
Step 2: the trigger port that is input as that this passage is set at oscilloscope.
Case study on implementation 3, test FPGA61.44MHz, as depicted in figs. 1 and 2:
Step 1: by transmitting-receiving letter veneer PCB layout, the 61.44MHz signal that FPGA recovers is drawn, by a clock buffer one-to-two, wherein one tunnel route to veneer edge or other positions, link to each other with the FPGA61.44MHz test interface by interface.
Step 2: the FPGA61.44MHz interface is connected with external meters, as measured signal.
Case study on implementation 4, PLL61.44MHz, as depicted in figs. 1 and 2:
Step 1: by transmitting-receiving letter veneer PCB layout, the output wiring of frequently combining system's first order debounce phase-locked loop is drawn, link to each other with the PLL61.44MHz test port by clock line.
Step 2: the PLL61.44MHz interface is connected with external meters, as measured signal.
Case study on implementation 5, local oscillator LO test, as depicted in figs. 1 and 2:
Step 1: by transmitting-receiving letter veneer PCB layout, transmitting-receiving altogether local oscillator situation can, directly by clock buffer along separate routes after, directly draw.In transmitting-receiving not altogether in the local oscillator, emission local oscillator and receive local oscillator and jointly draw realizes transmitting and receiving the switching of local oscillator by diverter switch, and the output direct wiring of switch links to each other it by clock line to the veneer edge or other positions with the LO test pin.
Step 2: local oscillator LO test interface directly links to each other with serial data analysis instrument SDA by becoming the directrix cable, finishes the measurement of phase noise, and then analyzes it to the influence degree of radio-frequency (RF) index.
Case study on implementation 6, the clock failure location, as depicted in figs. 1 and 2:
Step 1: utilize portable apparatus, whether the frequency accuracy of test FPGA61.44MHz signal satisfies design objective.
Step 2: utilize portable apparatus, whether the frequency accuracy of test PLL61.44MHz signal satisfies design objective.
Step 3: utilize portable apparatus, whether frequency accuracy and the frequency range of test local oscillator LO signal satisfy design objective.
Although above the utility model is had been described in detail, the utility model is not limited to this, and those skilled in the art of the present technique can carry out various modifications according to principle of the present invention.Therefore, all modifications of doing according to the principle of the invention all should be understood to fall into protection scope of the present invention.
Claims (10)
1. a RRU clock test window is characterized in that, comprising:
The board for receiving and sending message interface circuit is used for the test signal that access RRU board for receiving and sending message is exported;
The testing window interface circuit that connects described board for receiving and sending message interface circuit is used for accessing described test signal, and exports it to external test facility, in order to carry out external testing.
2. RRU clock test window according to claim 1 is characterized in that, described board for receiving and sending message interface circuit comprises time external interface and frequency external interface.
3. RRU clock test window according to claim 2 is characterized in that, described time external interface comprises:
The 10ms external interface that connects board for receiving and sending message FPGA is for the test signal of the 10ms that accesses FPGA output;
The PLL61.44MHz external interface that connects board for receiving and sending message first order phase-locked loop circuit is for the test signal of the debounce that accesses the output of first order phase-locked loop circuit.
4. RRU clock test window according to claim 3 is characterized in that, described frequency external interface comprises:
Connect successively the FPGA of board for receiving and sending message and the FPGA61.44MHz external interface of clock buffer, be used for the test signal of the 61.44MHz of access FPGA output;
The local oscillator LO external interface that connects the board for receiving and sending message frequency mixer is used for the test signal that the access frequency mixer is exported.
5. RRU clock test window according to claim 4 is characterized in that, described testing window interface circuit comprises time detecting interface and frequency detecting interface.
6. RRU clock test window according to claim 5 is characterized in that, described time detecting interface comprises:
The 10ms that connects described 10ms external interface by the clock cable detects interface, is used for exporting the test signal of described 10ms to external test facility;
The PLL61.44MHz that connects described PLL61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described debounce to external test facility.
7. RRU clock test window according to claim 6 is characterized in that, described frequency detecting interface comprises:
The FPGA61.44MHz that connects described FPGA61.44MHz external interface by the clock cable detects interface, is used for exporting the test signal of described 61.44MHz to external test facility;
The local oscillator LO that connects described local oscillator LO external interface by the clock cable detects interface, is used for exporting the test signal of described frequency device output to external test facility.
8. the described RRU clock test of any one window is characterized in that according to claim 1-7, and described board for receiving and sending message interface circuit is arranged on the veneer.
9. the described RRU clock test of any one window is characterized in that according to claim 1-7, and described testing window interface circuit is positioned on the RRU shell.
10. RRU clock test window according to claim 9 is characterized in that, described testing window interface circuit is positioned at RRU upper half shell handle one side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204750342U CN202818314U (en) | 2012-09-18 | 2012-09-18 | RRU clock test window |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204750342U CN202818314U (en) | 2012-09-18 | 2012-09-18 | RRU clock test window |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202818314U true CN202818314U (en) | 2013-03-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012204750342U Expired - Lifetime CN202818314U (en) | 2012-09-18 | 2012-09-18 | RRU clock test window |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202818314U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016058395A1 (en) * | 2014-10-17 | 2016-04-21 | 中兴通讯股份有限公司 | Information output method, diagnosis method and device, and sealing module |
| CN111294071A (en) * | 2018-12-06 | 2020-06-16 | 中国移动通信集团福建有限公司 | State data management method, device, equipment and medium for radio remote unit |
-
2012
- 2012-09-18 CN CN2012204750342U patent/CN202818314U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016058395A1 (en) * | 2014-10-17 | 2016-04-21 | 中兴通讯股份有限公司 | Information output method, diagnosis method and device, and sealing module |
| CN111294071A (en) * | 2018-12-06 | 2020-06-16 | 中国移动通信集团福建有限公司 | State data management method, device, equipment and medium for radio remote unit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: SANECHIPS TECHNOLOGY Co.,Ltd. Assignor: ZTE Corp. Contract record no.: 2015440020319 Denomination of utility model: RRU clock test window Granted publication date: 20130320 License type: Common License Record date: 20151123 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130320 |