CN202815822U - Exploring device for data consistency maintenance - Google Patents
Exploring device for data consistency maintenance Download PDFInfo
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- CN202815822U CN202815822U CN 201220304439 CN201220304439U CN202815822U CN 202815822 U CN202815822 U CN 202815822U CN 201220304439 CN201220304439 CN 201220304439 CN 201220304439 U CN201220304439 U CN 201220304439U CN 202815822 U CN202815822 U CN 202815822U
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Abstract
An exploring device for data consistency maintenance is suitable for a data processing unit, and is used for maintaining consistency between high-speed caching of the data processing unit set equipment and internal data storage in an external main memory of the data processing unit. When a first main controller of the data processing unit set equipment is to update stored data of the external main memory, the first main controller issues a request address to the exploring device, the exploring device searches an updating address which is combined with the request address in the high-speed caching according to the request address so as to update the stored data of the high-speed caching, so that the consistency between the external main memory and the stored data in the high-speed caching can be maintained to prevent failed data being accessed in the high-speed cashing by a second main controller or other main controller in the data processing unit.
Description
Technical field
The utility model is relevant for a kind of technology of memory data access, espespecially a kind of conforming search unit of service data that the high-speed cache store data is upgraded by search unit.
Background technology
High-speed cache is arranged at a kind of high-speed internal memory between computer and disc driver.The set primary controller of computer is (such as central processing unit, Central Processing Unit, CPU) during the data in reading disk driver or CD-ROM drive, because related data normally is placed on continuous position, so disc driver is after the data that read a certain zone, the action that the next one reads usually is next continuous zone, in order to reduce the number of times of reading disk driver, can the data that a part is extra deposit in the high-speed cache, may be with obtaining during in order to next time access, if the data of the access of wanting next time have left in the impact damper, be called cache hit, its speed is than fast thousands of times of the speed of the actual search of magnetic head magnetic fan access, therefore can effectively accelerate the efficient that the Winchester disk drive inputoutput data is processed, that is when must be with slower internal memory (such as the external main memory of computer) during as the data access interface of primary controller, the running speed of one-piece computer system will be along with slack-off, and this is because the work period of primary controller goes up many more than the data address access time of external main memory soon; High-speed cache is generally in order to use as the data working area, therefore, satisfy much smaller than external main memory its required storage area that has, therefore, the high-speed cache of general usefulness uses lower but static RAM (the Static Random Access Memory that read or write speed is fast of storage density mostly, SRAM) as memory element, and but dynamic RAM (Dynamic Random Access Memory, DRAM) that storage density larger slow with read or write speed is as the memory element of external main memory; Yet, though use high-speed cache can increase the speed of primary controller reading disk archives, but use high-speed cache also to have the problem of data consistency, because of external main memory take dynamic RAM as memory element, stored data must periodically be upgraded by primary controller in it, otherwise will make loss of data because of the charge leakage in the dynamic RAM memory internal lattice, if the data that primary controller is wanted to upgrade in external main memory are also hit in high-speed cache, order by data access, primary controller differentiates whether there are its required data that read in the high-speed cache in advance, if have, then directly from high-speed cache, read these data, if these data were before externally upgraded in the primary memory by other primary controllers, these these data that namely represent the access of existing primary controller institute are failed data, thereby will produce the inconsistent problem of reading out data, and cause the running of computer system to have problems, as network processing unit (Network Processor) inside be respectively equipped with one first primary controller, the second primary controller and high-speed cache, and be connected with an external main memory, in this framework, the first primary controller mainly carries out the data access operation to external main memory, the second primary controller then with high-speed cache as data access interface, as previously mentioned, high-speed cache internal storage data are to obtain and be the highest data of the second primary controller access times from external main memory; From the above, the first primary controller can't be from high-speed cache reading out data, it only reads from external main memory, that is the store data of high-speed cache is only carried out access by the second primary controller, so when the first primary controller writes data to external main memory, with regard to current practice, the first primary controller can't upgrade inner identical with the external main memory writing address store data of high-speed cache synchronously, thereby so that external main memory can't be consistent with high-speed cache internal storage data, also even after the stored data of second this writing address of primary controller access, for network processing unit, these data lost efficacy, if the result who continues to read will cause the running of network processing unit to produce mistake.
Technical solution for caching data consistency commonly used has broadcasting (Broadcasting), non-high-speed cache is specified the modes such as (Non-cacheable memory designation) and cache flush (Cache flushing), wherein non-high-speed cache is specified and the cache flush dual mode will lower data cached hit rate (Cache hit rate) and affect the speed of data access, though and the data cached hit rate of the unlikely attenuating of broadcast mode, but because of its employed circuit comparatively complicated, satisfying will be so that the encapsulation volume of primary controller thereby increase, in addition complicated circuit also will produce the problem of thermal diffusivity again, therefore, how not affecting data cached hit rate and being aided with easy logical circuit and can reaching caching data consistency, be the technical matters of demanding urgently at present overcoming.
The utility model content
In view of the shortcoming of above-mentioned prior art, fundamental purpose of the present utility model is to provide a kind of service data conforming search unit, and it can safeguard external main memory and high-speed cache internal storage data's consistency by a simple logical circuit.
Another purpose of the present utility model is to provide a kind of service data conforming search unit, it can be when the first primary controller wish be upgraded the store data of external main memory, in the lump high-speed cache is upgraded, with after avoiding second or other primary controllers situation of getting fail data at cache memory occur.
For reaching above-mentioned purpose, the utility model namely provides a kind of service data conforming search unit.
The conforming search unit of a kind of service data is applicable in the data processing unit, this data processing unit comprises the first primary controller, the second primary controller and high-speed cache, and be connected with a primary memory, the writing address when this search unit upgrades the store data of primary memory by this first primary controller wish upgrades the store data of high-speed cache simultaneously.
Search unit of the present utility model is applicable in the network processing unit, this network processing unit also comprises: the first primary controller, the second primary controller, catalogue internal memory, multiplexer, high-speed cache and memory arbitrator, this network processing unit also is connected with an external main memory via memory arbitrator, wherein, as data access interface, the data access interface of the second primary controller then is high-speed cache to this first primary controller with external main memory.
The conforming search unit of service data of the present utility model, it is inner to be mounted on this network processing unit, it includes in addition: (a) comparison module hunts out the scheduler that combines with this writing address according to the first primary controller via the writing address that the catalogue internal memory compares in high-speed cache; (b) update module, the scheduler that can provide according to comparison module, the data content that the first primary controller wish is upgraded external main memory upgrades in high-speed cache in the lump.
Can just can safeguard data cached consistance not affecting data cached hit rate and be aided with on the basis of easy logical circuit by the utility model embodiment.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present utility model, consists of the application's a part, does not consist of restriction of the present utility model.In the accompanying drawings:
Fig. 1 is that a calcspar is that inner contained each functional module of search unit of the present utility model and network processing unit links the inner structure synoptic diagram when carrying out the data consistency upkeep operation;
Fig. 2 is that a process flow diagram is the search method of search unit of the present utility model carries out the data consistency upkeep operation at a network processing unit flow chart of steps.
The simple declaration of each component symbol among the figure:
10 ... network processing unit 11 ... the first primary controller
12 ... the second primary controller 13 ... the catalogue internal memory
14 ... search unit 141 ... comparison module
142 ... update module 15 ... multiplexer
16 ... high-speed cache 17 ... memory arbitrator
20 ... external main memory
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
Following embodiment further describes viewpoint of the present invention, but is not to limit anyways category of the present utility model.
Fig. 1 is a calcspar, it links the inside structure synoptic diagram when carrying out the data consistency upkeep operation in order to show search unit of the present utility model 14 and network processing unit 10 inner contained each functional module, as shown in the figure, in following embodiment, the conforming search unit of the utility model service data is applied to a network processing unit (Network Processor) 10, whereby so that 10 groups of high-speed caches of establishing 16 of network processing unit and the external main memory 20 internal storage data's consistencies that connected thereof are safeguarded, yet, should be noted at first that again the utility model is not only to can be used on the network processing unit, the utility model can be applicable to data processing unit to carrying out between external main memory and high-speed cache in the operation of data access and maintenance, in order to maintaining cached and external main memory internal storage data's consistency.
Search unit 14 of the present utility model is mounted on network processing unit 10 inside, also comprises a comparison module 141 and update module 142 in it; This network processing unit 10 includes the first primary controller 11 in addition, it can be a medium access controller (Media Access Control, MAC), the second primary controller 12, it can be a central processing unit (Central Processing Unit, CPU), catalogue internal memory (Tag RAM) 13, multiplexer 15, high-speed cache 16 and memory arbitrator 17, wherein, this memory arbitrator 17 externally is connected to an external main memory 20 (the following primary memory 20 that slightly is called) in addition, and these primary memory 20 employed memory components are a dynamic RAM (the following DRAM that slightly is called).
Primary memory 20 internal storage have arrogant capacity storage device, such as the partial data that hard disk (not shown) reads, these data be the second primary controller 12 network processing unit 10 start or operation process in, the required data that read and carry out; In the operation process of network processing unit 10, the first primary controller 11 carries out access according to its work is required to the data on the external main memory 20, the second primary controller 12 is the store data of accessing cache 12 only then, yet, in fact the frequency of the second primary controller 12 is all far faster than external main memory 20, therefore, if the second primary controller 12 is wanted when external main memory 20 consecutive access data, then must wait for a plurality of frequency periods, cause the speed of the second primary controller 12 access datas slack-off, therefore need by a high-speed cache 16, to improve the speed of the second primary controller 12 access datas; This high-speed cache 16 is an accelerator, generally be static RAM (SRAM), this is because SRAM has faster access speed, its operation principles be use faster high-speed cache 16 keep a from storage device (such as external main memory 20) at a slow speed the copying of sense data, that is high-speed cache 16 data that the second primary controller 12 frequencies of access are higher are read and are kept from external main memory 20, with when the second primary controller 12 needs to use these data next time, can directly at high-speed cache 16 enterprising line access, can improve the access data speed of the second primary controller 12; Data such as the 12 required uses of the second primary controller are not deposited in high-speed cache 16, then it need see through a memory arbitrator 17 required data of access to the external main memory 20, this memory arbitrator 17 is measurable and read in advance the second primary controller 12 required data that read, use the efficient that improves the second primary controller 12 access datas, certainly, memory arbitrator 17 is known technology, so its principle is not given unnecessary details at this.
External main memory 20 employed memory components are a dynamic RAM, this is because the cost of DRAM is lower and density is higher, be suitable in the zonule of computer system, storing a large amount of data, but, the data that are stored among the DRAM must periodically be upgraded it by the first primary controller 11, in order to avoid make loss of data because of the charge leakage among the DRAM, when the first primary controller 11 wishs are upgraded the store data of external main memory 20, to read target memory 13 interior stored destination address data in advance, by the corresponding word line data combination in these destination address data and the high-speed cache 16, whether hit (Hit) to differentiate buffer memory whereby, that is first primary controller 11 writing address of wanting to carry out in the primary memory 20 externally Data Update whether also be present in the target memory 13, if this writing address is not present in the target memory 13, that is represent that the first primary controller 11 is not in high-speed cache 16 interior cache hit, be present in the target memory 13 such as this writing address, the first primary controller 11 then transmits one through target memory 13 and includes the request address signal of request address to search unit 14, this request address signal is received and is processed by 14 interior groups of comparison modules of establishing of search unit 141, to make this comparison module 141 in high-speed cache 16, hunt out the scheduler that combines with this request address, when comparison module 141 finds with request address is combined scheduler, even the data in the high-speed cache 16 are upgraded by this scheduler with update module 142, to make the first primary controller 11 when the store data of external main memory 20 is upgraded, also can upgrade in high-speed cache 16 inter-syncs identical writing address, with maintaining cached 16 and external main memory 20 in the consistance of storage data, and can avoid the second primary controller 12 after the Data Update of external main memory 20, the still situation generation of fail data of access from high-speed cache 16, make network processing unit 10 be able to normal operation, to reach the conforming purpose of service data.
Fig. 2 is a process flow diagram, carries out every program step of data consistency upkeep operation in a network processing unit 10 in order to search method of the present invention to be described; As shown in the figure, when the first primary controller 11 wishs are upgraded the store data of external main memory 20, read the destination address data in the catalogue internal memory 13 in advance, use and differentiate writing address that institute's wish upgrades whether in high-speed cache 16 is interior, if data buffer storage hits, proceed to immediately step S2, as no, directly proceed to step S5.
In step S2, the first primary controller 11 sends a request address signal to search unit 14 via catalogue internal memory 13, the store data of high-speed cache 16 is upgraded according to this request address signal to make this search unit 14, then proceeds to step S3.
In step S3, the comparison module 141 that makes these search unit 14 inner groups establish hunts out the scheduler that combines with request address in high-speed cache 16, then proceed to step S4.
In step S4, after this comparison module 141 hunts out scheduler, even the update module 142 that these search unit 14 inner groups are established is upgraded the data of depositing in the high-speed cache 16 by this scheduler, proceed at last step S5.
In step S5, by the first primary controller 11 by the address of wanting to write the data of external main memory 20 internal storage are upgraded.
In sum, the conforming search unit of service data of the present utility model can be when the first primary controller wish be upgraded the external main memory internal storage data, the store data content of the same writing address of in the lump high-speed cache inside being kept in by an easy logical circuit is upgraded, just can be maintaining cached and external main memory internal storage data's consistency, and can avoid after the second primary controller or other primary controllers in the situation generation of the inner access of high-speed cache fail data.
Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is embodiment of the present utility model; and be not used in and limit protection domain of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (7)
1. conforming search unit of service data, it is characterized in that, be applicable in the data processing unit, this data processing unit comprises the first primary controller, the second primary controller and high-speed cache, and be connected with a primary memory, writing address when this search unit upgrades the store data of primary memory by this first primary controller wish upgrades the store data of high-speed cache simultaneously.
2. search unit as claimed in claim 1 is characterized in that, this data processing unit is a network processing unit.
3. search unit as claimed in claim 1 is characterized in that, this first primary controller is a multimedia access controller.
4. search unit as claimed in claim 1 is characterized in that, this second primary controller is a central processing unit.
5. search unit as claimed in claim 1 is characterized in that, this primary memory is an external main memory.
6. search unit as claimed in claim 1 is characterized in that, this data processing unit includes a catalogue internal memory, multiplexer and internal memory moderator in addition.
7. search unit as claimed in claim 6 is characterized in that, whether whether this first primary controller compares first writing address and be present in the catalogue internal memory, hit in order to differentiate buffer memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304439 CN202815822U (en) | 2012-06-26 | 2012-06-26 | Exploring device for data consistency maintenance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304439 CN202815822U (en) | 2012-06-26 | 2012-06-26 | Exploring device for data consistency maintenance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202815822U true CN202815822U (en) | 2013-03-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220304439 Expired - Lifetime CN202815822U (en) | 2012-06-26 | 2012-06-26 | Exploring device for data consistency maintenance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202815822U (en) |
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2012
- 2012-06-26 CN CN 201220304439 patent/CN202815822U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN XINLI ELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER NAME: HAINAN XINLI SEMICONDUCTOR CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 518040 A, block 13Z, Fortune Plaza, 7060 Shennan Road, Shenzhen, Guangdong, Futian District Patentee after: SHENZHEN XINLI ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 403 room 571924, incubator of Hainan eco Software Park, hi tech demonstration zone, Hainan old city Patentee before: HNXLI SEMICONDUCTOR Co.,Ltd. |
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| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Beijing HENGBANG Science & Technology Co.,Ltd. Assignor: SHENZHEN XINLI ELECTRONIC TECHNOLOGY Co.,Ltd. Contract record no.: 2014990000934 Denomination of utility model: Exploring device for data consistency maintenance Granted publication date: 20130320 License type: Exclusive License Record date: 20141216 |
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| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201203 Address after: Room a-09, 10 / F, building 1, yard 7, mei'an Road, Mentougou District, Beijing 102300 Patentee after: Guoan Jiuzhou New Energy Technology Co.,Ltd. Address before: 518040 A, block 13Z, Fortune Plaza, 7060 Shennan Road, Shenzhen, Guangdong, Futian District Patentee before: SHENZHEN XINLI ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130320 |
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| CX01 | Expiry of patent term |