CN202815203U - Self-checking system in electric measuring instrument general calibrating device - Google Patents
Self-checking system in electric measuring instrument general calibrating device Download PDFInfo
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- CN202815203U CN202815203U CN 201220487879 CN201220487879U CN202815203U CN 202815203 U CN202815203 U CN 202815203U CN 201220487879 CN201220487879 CN 201220487879 CN 201220487879 U CN201220487879 U CN 201220487879U CN 202815203 U CN202815203 U CN 202815203U
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Abstract
The utility model discloses a self-checking system in an electric measuring instrument general calibrating device. The self-checking system includes a central processor, a digital signal processor, a first digital-to-analog converter, a second digital-to-analog converter, a filter, a power amplifier, an analog-to-digital converter, and a relay. The central processor is connected with the first digital-to-analog converter and the second digital-to-analog converter via the digital signal processor. The first digital-to-analog converter and the second digital-to-analog converter are connected with the filter. When the central processor controls the relay on a first position, the filter is connected with the analog-to-digital converter; and when the relay is on a second position, the filter is connected with the analog-to-digital converter via the power amplifier. The model of each of the first and second digital-to-analog converter is DAC8734, the model of the digital signal processor is BF533, and the model of the analog-to-digital converter is ADS1278. The self-checking system is mainly realized by software, so the detection accuracy is greatly improved, and the manpower cost is reduced. The self-checking system only needs one relay, so the cost is saved, and the self-checking unreliability is reduced. The self-checking system has an advantage.
Description
Technical field
The utility model relates to a kind of verification system of electric measuring instrument, relates in particular to the self-checking system in the general calibrating installation of a kind of electric measuring instrument.
Background technology
Self-checking function is a ring very important in signal generation apparatus, calibrating installation and the proving installation, lacked self-checking function, some fault occurs instrument will be difficult to timely discovery, even and found, can not quick lock in location of fault and reason, so self-checking function is very important.For example the each start of digital oscilloscope all can be carried out a self check, when doubtful fault occurs in the AC signal source, can carry out quick diagnosis by self-checking function.Because the function ratio of the general calibrating installation of electric measuring instrument is more, three-phase alternating voltage for example, three-phase alternating current, dc high voltage (1000V), D.C. high-current (30A), small-signal DC voltage (mV or μ V level), small-signal ac and dc current (mA or μ A level), RTU detection module etc., therefore port number is also many, if according to traditional self test mode, the relay that needs is a lot, make up also very complicated, this has just increased the unreliability (the mechanical relay action frequency is restricted) of self check greatly, but self-checking function originally just need to be more reliable than instrument other parts function.
The utility model content
The purpose of this utility model is to overcome deficiency of the prior art, by selecting at present up-to-date technology, take full advantage of the existing resource of chip, and the functional requirement of combination product itself, provide the self-checking system in the general calibrating installation of a kind of electric measuring instrument, to substitute traditional comparatively loaded down with trivial details notching relay self-checking system.
For achieving the above object, self-checking system in the general calibrating installation of described electric measuring instrument, be characterized in, described self-checking system comprises that central processing unit, digital signal processor, model are the first digital to analog converter of DAC8734, the second digital to analog converter, wave filter, power amplifier, analog to digital converter and the relay that model is DAC8734, wherein
Described central processing unit is electrically connected with the first and second digital to analog converters respectively through digital signal processor, and described the first and second digital to analog converters all are electrically connected with described wave filter; And,
When described central processing unit pilot relay was in primary importance, described wave filter directly was electrically connected with analog to digital converter; When described central processing unit pilot relay was in the second place, described wave filter was electrically connected with analog to digital converter through power amplifier.
Preferably, the model of described digital signal processor is BF533.
Preferably, the model of described analog to digital converter is ADS1278.
The beneficial effects of the utility model are that the self-checking system in the general calibrating installation of described electric measuring instrument is most of to be realized by software, has greatly improved the degree of accuracy that detects, and has reduced simultaneously human cost; System only needs a relay, the cost-effective while, reduced the unreliability of self check, and have larger advantage.
Description of drawings
Fig. 1 is the circuit diagram of the self-checking system in the general calibrating installation of described electric measuring instrument;
Fig. 2 is the mapping form explanation of the first/the second analog to digital converter DAC8734 internal register;
Fig. 3 is the corresponding explanation of the truth table of the first/the second analog to digital converter DAC8734 internal control register;
Fig. 4 is the graph of a relation of the switching of the first/the second analog to digital converter DAC8734 internal simulation and policing port;
Fig. 5 is the sequential chart that central processing unit passes through the output of SPI interface control digital to analog converter;
Fig. 6 is the filtering circuit of digital to analog converter output port;
Fig. 7 is filtering and the signal conditioning circuit of policing port.
Embodiment
The utility model is described in more detail below in conjunction with the drawings and specific embodiments:
Fig. 1 is the circuit diagram of the self-checking system in the general calibrating installation of described electric measuring instrument, as shown in Figure 1, self-checking system in the general calibrating installation of described electric measuring instrument, comprise central processing unit, digital signal processor 1, the first digital to analog converter 21, the second digital to analog converter 22, wave filter 3, power amplifier 4, analog to digital converter 5 and relay 6, wherein, described central processing unit is electrically connected with the first digital to analog converter 21 and the second digital to analog converter 22 respectively through digital signal processor 1, and described the first digital to analog converter 21 and the second digital to analog converter 22 all are electrically connected with described wave filter 3.And when described central processing unit pilot relay 6 was in primary importance, described wave filter 3 directly was electrically connected with analog to digital converter 5; When described central processing unit pilot relay 6 was in the second place, described wave filter 3 was electrically connected with analog to digital converter 5 through power amplifier 4.
The model of described digital signal processor 1 is BF533, and its high primary frequency 533MHz is the very good DSP chip of a performance.The model of described the first digital to analog converter 21 and the second digital to analog converter 22 is DAC8734, it is the 4 Channel Synchronous output DAC chip of TI company, 16bit resolution, do not calibrate the error less than 4LSB yet, calibration is rear less than 1LSB, long-term output stability 1000 hours is less than 3ppm, so precision is very outstanding.The model of described analog to digital converter 5 is ADS1278, and it is the 8 Channel Synchronous sampling AD chip of TI company, 24bit resolution, up to the SNR(equivalent precision of 111dB near 19bit), the sampling rate of the highest 144kSPS float less than 1.3ppm/ ℃ gain temperature, so precision is very high.
Below will introduce in detail scheme content and the specific implementation principle of this self-checking system.
Described digital signal processor 1 is controlled the output of the first digital to analog converter 21 and the second digital to analog converter 22 by the SPI interface, wherein said the first digital to analog converter 21 be connected digital to analog converter 22 and adopt the form of daisy chains to connect (as shown in Figure 1), so only need a SPI interface can control simultaneously two digital to analog converters 21,22, but should be noted that in the control sequential, namely need 48 CLK rather than 24 (as shown in Figure 5) in a CS signal, when SPI transmits the 25th CLK, first valid data that comes on the SDI interface will enter on the SDI pin of the second digital to analog converter 22 by its SDO pin, the DA signal of 8 passages of output that therefore will be complete, 4 CS pulses need to be arranged, totally 192 CLK signals, after all data of 192 have been sent, by low level pulse signal on the LDAC pin data of all 8 passages will be loaded synchronously, so DAC8734 is a synchronous analog-digital chip.
It is the VMON interface that DAC8734 has a very practical interface, its cut-away view is shown in 4, be that inside has an analog switch, can select respectively AIN, VOUT1, VOUT2, VOUT3, VOUT4 conducting, perhaps all not selecting, is that 0001 control register is realized by SPI control address specifically.Shown in elliptical section was divided among Fig. 2, its truth table then as shown in Figure 3 in the position in the register mapping table for control register.
By SPI control control register, can so that the arbitrary passage output in these 10 passages when needing self check then can select at ordinary times to close.What need in addition explanation here is because the direct current component function only needs very low sampling rate, and direct current output is because PWM control and producing, and the closed loop that therefore can be used for DC voltage and DC current when self-checking function is no at ordinary times detects.As shown in Figure 1, the AIN pin of the first digital to analog converter 21 and the second digital to analog converter 22 connects respectively DC voltage and the DC current of power amplifier 4, at set intervals the MUX of inside is switched back and forth by the SPI interface, can obtain corresponding direct current signal at the VMON end.
VOUT1 ~ VOUT8 is 8 signal ports of the first digital to analog converter 21 and the long-term output of the second digital to analog converter 22, and wherein VOUT4 and VOUT8 are exclusively used in the output of the electric current (mA or μ A level) of the voltage (mV or μ V level) of small-signal and small-signal.Behind second order active low-pass filter 3 filtering staircase effects, can obtain comparatively perfectly sinusoidal signal.Filtering circuit as shown in Figure 6.Signal after the filtering is directly delivered to power amplifier 4 and export gauge external to after power amplification, the signal behind the power amplifier is dwindled again, delivers to block converter after the filtering and detect.Because the existing staircase effect of signal of VMON end, amplitude is larger again in addition, and this is because the voltage range of digital to analog converter output is ± 10V, and the measurement range of analog to digital converter 5 is due to 0 ~ 5V.The late-class circuit of VMON end as shown in Figure 7.
Should be noted that, the signal output of VMON end is 8 road coherent signals of power amplifier prime, and analog to digital converter 5 long-term tests is the power amplifier rear class, switch the first via signal of VMON and power amplifier rear end by relay 6, can realize the simulating signal of having a few of whole system, thereby consist of a complete self-checking system, and the mouth line of pilot relay 6 is to be realized by the GPIO port of the first digital to analog converter 21, the address that this GPIO port is controlled the first digital to analog converter 21 by SPI is that 0000 register is realized, thereby saved the IO mouth line of a digital signal processor 1, reached the design of simplifying the most.
Here the process that starts of bright self-checking system for instance, suppose C phase voltage power amplifier level fault, the user is in the process that reality is used, find that the output of C phase voltage is incorrect, set output 220VAC, about actual output 205V, and export unstablely, this moment, the push button of the liquid crystal panel that the user can have by system entered successively: system's setting-self check-self check starts.Then the central processing unit on master control borad this moment sends the self check order to the SPORT mouth of digital signal processor 1 by its McBSP interface, after digital signal processor 1 receives orders, enters at once self-check program.Here self check is divided into several steps, and is as follows respectively:
Step 1: the address that digital signal processor 1 is controlled the first digital to analog converter 21 by the SPI interface is the DB8 position (as shown in Figure 2) of 0000 register, so that GPIO0 is output as height, thereby so that 6 dozens on described relay is to primary importance, be one side of self check, this moment described wave filter 3 direct connection mode number converters 5.Then 8 passages controlling the first digital to analog converter 21 and the second digital to analog converter 22 by the SPI interface are exported 0V simultaneously, read the value that analog to digital converter 5 gathers by the SPORT mouth, and be temporarily stored among the SDRAM, then exporting successively the standard sine wave of 5V and 10V measures and keeps in, will be at 0V, 5Vpk, the 10Vpk measured value respectively with the I2C storer in the history parameters value that deposits in compare, when exceeding the allowed band of self check defined, then think a certain index exceeding standard, here whether 0V is normal in order to detect DC quantity (direct current biasing), 5Vpk and 10Vpk then are respectively half-full place value and full place value, owing to be that the power amplifier end has fault here, thus this step testing result all are normal.
Step 2: DSP is by the gear relay 6(remarks in SPI interface (claiming soft SPI interface here) the power ratio control amplifier 4 of GPIO simulation: because the relay 6 of this part total original just needs that are systems, therefore do not calculate in the self-checking system), select the gear of minimum electric current and voltage, this moment, 6 dozens on described relay was to the second place, be that described wave filter 3 is by power amplifier 4 connection mode number converters 5, then control 8 road DA by hard SPI interface, make power amplifier rear end output zero signal, read in ADC by the SPORT mouth and gather the value of coming, compare with the historical zero adjustment parameter that deposits in the I2C storer, concrete comparative approach is that calibration parameter value deducts actual measured value, then difference is asked for absolute value again and is temporarily stored among the SDRAM; Same method is exported, measures, is compared full place value, then comparative result is temporarily stored among the SDRAM.The comparative result of zero-bit and full position is all out once analyzed afterwards, when the deviation of the zero value of a certain phase or full place value surpasses the scope that self-check program sets, then this is marked mutually.
Step 3: again use the method for step 2, the gear relay 6 of power amplifier 4 is switched to second little, the 3rd little, the 4th little etc. gear increase successively and carry out self-checking.Then it is fixed to carry out the opinion of fault according to self-detection result, if for example the C phase voltage is all undesired during all gears, then fault should be amplifier or the power tube induced fault of power amplifier leading portion, if be some ranges for example the 220V gear is unusual, then fault should be due to the transformer fault.Fault self-checking finishes since then, because each gear C phase voltage is all undesired, so fault diagnosis result is power tube or power amplifier 4 faults.
Be no less than 10 relays 6 and numerous control mouthful line by designing this self-checking system, having saved, therefore namely strengthened reliability, saved greatly again resource.
Being the utility model preferred embodiment only in sum, is not to limit practical range of the present utility model.Be that all equivalences of doing according to the content of the utility model claim change and modification, all should belong to technology category of the present utility model.
Claims (3)
1. the self-checking system in the general calibrating installation of electric measuring instrument, it is characterized in that: described self-checking system comprises that central processing unit, digital signal processor, model are the first digital to analog converter of DAC8734, the second digital to analog converter, wave filter, power amplifier, analog to digital converter and the relay that model is DAC8734, wherein
Described central processing unit is electrically connected with the first and second digital to analog converters respectively through digital signal processor, and described the first and second digital to analog converters all are electrically connected with described wave filter; And,
When described central processing unit pilot relay was in primary importance, described wave filter directly was electrically connected with analog to digital converter; When described central processing unit pilot relay was in the second place, described wave filter was electrically connected with analog to digital converter through power amplifier.
2. the self-checking system in the general calibrating installation of electric measuring instrument according to claim 1, it is characterized in that: the model of described digital signal processor is BF533.
3. the self-checking system in the general calibrating installation of electric measuring instrument according to claim 1, it is characterized in that: the model of described analog to digital converter is ADS1278.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220487879 CN202815203U (en) | 2012-09-24 | 2012-09-24 | Self-checking system in electric measuring instrument general calibrating device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220487879 CN202815203U (en) | 2012-09-24 | 2012-09-24 | Self-checking system in electric measuring instrument general calibrating device |
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| CN202815203U true CN202815203U (en) | 2013-03-20 |
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| CN 201220487879 Expired - Fee Related CN202815203U (en) | 2012-09-24 | 2012-09-24 | Self-checking system in electric measuring instrument general calibrating device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110505200A (en) * | 2019-07-09 | 2019-11-26 | 惠州市亿能电子有限公司 | A kind of multi-protocols daisy chain interface conversion chip |
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2012
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110505200A (en) * | 2019-07-09 | 2019-11-26 | 惠州市亿能电子有限公司 | A kind of multi-protocols daisy chain interface conversion chip |
| CN110505200B (en) * | 2019-07-09 | 2022-06-24 | 惠州市亿能电子有限公司 | Multi-protocol daisy chain interface conversion chip |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130320 Termination date: 20150924 |
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| EXPY | Termination of patent right or utility model |