CN202772555U - Shoot-through protection circuit of photovoltaic grid-connected inverter - Google Patents
Shoot-through protection circuit of photovoltaic grid-connected inverter Download PDFInfo
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- CN202772555U CN202772555U CN 201120481037 CN201120481037U CN202772555U CN 202772555 U CN202772555 U CN 202772555U CN 201120481037 CN201120481037 CN 201120481037 CN 201120481037 U CN201120481037 U CN 201120481037U CN 202772555 U CN202772555 U CN 202772555U
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Abstract
The utility model provides a shoot-through protection circuit of a photovoltaic grid-connected inverter. The shoot-through protection circuit of the photovoltaic grid-connected inverter is characterized in that the shoot-through protection circuit of the photovoltaic grid-connected inverter includes a control signal protection circuit, a power source monitoring circuit and an 8-bit reverse buffering drive circuit. The control signal protection circuit and the power source monitoring circuit are connected in parallel and output terminal of the control signal protection circuit and the power source monitoring circuit are both connected with the 8-bit reverse buffering drive circuit. According to the utility model, by adding a circuit protecting control signals and combining factors of an auxiliary power source, an inverter bridge is not allow to work when PWM control signals are in an uncertain state in an electrifying moment, so that the inverter bridge is protected. Shoot-through short-circuit failures are avoided, thereby preventing the inverter bridge from burning out. Therefore, the working stability and reliability of the shoot-through protection circuit of the photovoltaic grid-connected inverter are improved effectively.
Description
Technical field
The utility model relates to the solar photovoltaic technology field, is specifically related to a kind of novel photovoltaic combining inverter IGBT full-bridge circuit.
Background technology
Because solar energy has pollution-free, aboundresources, without characteristics such as region limits, therefore as a kind of new forms of energy of reproducible utilization, be widely used.Solar energy power generating is a kind of important application of solar energy, more and more receive in recent years the people of the world's concern, photovoltaic combining inverter is one of core component of photovoltaic generating system, effect is that the direct current energy that photovoltaic module produces is converted to AC energy and is delivered to electrical network, and the quality of its performance has a great impact the reliable and stable operation tool of whole system.
Photovoltaic combining inverter mainly is divided into two-stage, and previous stage is DC-DC BOOST circuit, is used for direct voltage adjustment and maximal power tracing; Rear one-level is single-phase full bridge formula DC-AC translation circuit as shown in Figure 1, and its output is incorporated into the power networks through behind the inductor filter.
At first, for avoiding because upper pipe VT1(VT3) and lower pipe VT2(VT4) the straight-through fault that causes for high level simultaneously because of the driving signal, need in drive software, consider on the one hand to add the dead band, on the other hand also need to be on hardware circuit the drive waveforms of pipe be up and down carried out hardware interlock, when managing up and down drive level simultaneously for significant level, automatically block driving voltage.
In addition; IGBT also might be because of overvoltage, overheated to cause moment to puncture straight-through; perhaps self snowslide inefficacy short circuit, because the short circuit that the electrical connection that external cause causes causes; two transistors on the same brachium pontis all can have large electric current to pass through at this moment; present various safeguard measures all can't thoroughly be avoided the possibility of converter generation bridge arm direct pass; so how, be implemented in time to detect when bridge arm direct pass occurs and lead directly to fault and protect IGBT, burn to avoid IGBT, just seem particularly important.
The bridge arm direct pass protective circuit has two types at present:
As shown in Figure 2, it is for detecting the brachium pontis current protecting circuit.When brachium pontis electric current I 1 and I2 increase to suddenly the certain multiple rated current, just think the bridge arm direct pass fault occurs that block all IGBT and drive this moment, to eliminate fault, avoids IGBT to burn.This kind testing circuit is applicable in the single-phase low capacity converter, for three-phase inverter or high power converters because the brachium pontis rated current is larger, during single-phase bridge arm direct pass, before IGBT damages its electric current I variation not too obvious, can not implement effective protection.
As shown in Figure 3, it is for using the protective circuit with the driving optocoupler (for example HCPL316J) of over-current detection.By the characteristic of IGBT as can be known, when IGBT opened, its C, E both end voltage and its electric current that passes through had linear relationship, IGBT can bear the peak current of 4 times of its rated current in 10 μ s, when occuring to lead directly to, judge the IGBT overcurrent by the saturation voltage drop that detects UCE, drive signal thereby block.Its general circuit is as shown in Figure 3.
Above-mentioned two kinds of protective circuits can be protected the inverter bridge shoot through in the ordinary course of things effectively; but the nondeterministic statement of having ignored moment of powering on (DSP initialization finish before) pwm control signal; if pwm control signal is significant level simultaneously when powering on, inverter bridge just might be burnt in the moment that powers on.
The utility model is exactly the fault of burning of " leading directly to " power transistor that short circuit phenomenon causes for the full bridge inversion circuit of one-level behind the photovoltaic combining inverter and propose a kind of more effective, more reliable protective circuit.
The utility model content
In view of this, be necessary for the problem of mentioning in the background technology, provide a kind of more effective, protect the novel protected circuit of photovoltaic combining inverter more reliably.
The utility model is achieved through the following technical solutions:
A kind of straight-through protective circuit of photovoltaic combining inverter; it comprises a control signal protective circuit, a power supply supervisory circuit and one 8 reverse buffering drive circuits; this control signal protective circuit and this power supply supervisory circuit are in parallel, and its output all is connected with these 8 reverse buffering drive circuits.
As optimization; described 8 reverse buffering drive circuits comprise that one oppositely cushions driving chip 74HC540; one resistance R 3; one capacitor C 3; one triode Q2 and a diode D1; the pwm control signal of the inverter bridge of described photovoltaic combining inverter is via this oppositely buffering driving chip 74HC540 output; oppositely the sheet selected control signal pins G1 processed of buffering driving chip 74HC540 is connected with the IO mouth of the control chip DSP of photovoltaic combining inverter; another sheet selected control signal pins G2 processed and resistance are that the resistance R 3 of 1K and the collector electrode of NPN triode Q2 join; resistance R 3 connection+5V power supplys; the grounded emitter of triode Q2; base stage links to each other with the negative electrode of diode D1, and the anode of diode D1 is connected with the output of described control signal protective circuit and power supply supervisory circuit.
As optimization, described power supply supervisory circuit is received the 3.3V power supply by the magnetic bead L1 of the 600/100KHZ of 3 pin serial connection of a power monitoring chip TPS3809K33,3 pin connect an over the ground filtering of capacitor C 1 simultaneously, the 1 pin ground connection of power monitoring chip TPS3809K33,2 pin are through 6 outputs of a 1K resistance R.
As optimization; described control signal protective circuit is comprised of four NAND gate and a diode D2; two pwm control signal UP of the same brachium pontis of the inverter bridge of photovoltaic combining inverter and UN connect respectively two inputs of the first NAND gate; in addition two control signal VP and VN connect respectively two inputs of the second NAND gate; the input of the 3rd NAND gate is received respectively in the output of this first NAND gate and the second NAND gate again; the output of the 3rd NAND gate is reverse through the 4th NAND gate; the negative electrode of a diode D2 is received in the output of the 4th NAND gate, and the anode of diode D2 is output.
Compared with prior art; the utility model possesses following advantage: increased a circuit to the control signal protection; factor in conjunction with accessory power supply; the protection inverter bridge does not allow work at the moment pwm control signal that powers under uncertain state; therefore inverter bridge can not cause the shoot through fault and burn, and effectively improves job stability and the reliability of circuit.
Description of drawings
Fig. 1 is the photovoltaic combining inverter single-phase full bridge formula DC-AC translation circuit schematic diagram of prior art;
Fig. 2 is the straight-through protective circuit schematic diagram of the bridge wall of prior art;
Fig. 3 is the over-current detection protective circuit schematic diagram of prior art;
Fig. 4 is the utility model circuit diagram;
Fig. 5 is the power supply supervisory circuit schematic diagram among Fig. 4;
Fig. 6 is the control signal protective circuit schematic diagram among Fig. 4.
Embodiment
As shown in Figure 4, the embodiment of the utility model is comprised of 8 reverse buffering drive circuits, power supply supervisory circuit and control signal protective circuit three parts.
1, reverse buffering drive circuit
As shown in Figure 4, this partial circuit comprises that one oppositely cushions driving chip 74HC540, a resistance R 3, a capacitor C 3, a triode Q2 and a diode D1.
The pwm control signal UP of the inverter bridge of photovoltaic combining inverter, UN, VP, if the VN(inverter bridge is three-phase bridge, then also have WP and WN) via this oppositely buffering driving chip 74HC540 output, oppositely buffering drives chip 74HC540 two sheet selected control signal G1 processed and G2, oppositely the sheet selected control signal pins G1 processed of buffering driving chip 74HC540 is connected (not shown) with the IO mouth of the control chip DSP of photovoltaic combining inverter, another sheet selected control signal pins G2 processed (19 pin) and resistance are that the resistance R 3 of 1K and the collector electrode of NPN triode Q2 join, when two chip selection signal G1 and G2 allow to export pwm control signal during simultaneously for low level.During normal operation, the G1(1 pin) directly by giving a low level, moves+5V the E utmost point ground connection of Q2 on the resistance R 3 to, the B utmost point links to each other with the negative electrode of diode D1, the anode of diode D1 is connected with the output of other two parts circuit, and triode Q2 is controlled by other two parts circuit, when the anode of diode D1 is high level, diode D1 conducting, the Q2 conducting, oppositely buffering drives the G2(19 pin of chip 74HC540) be low level, allow output; Otherwise when the anode of diode D1 is low level, diode D1 cut-off, the Q2 shutoff, oppositely buffering drives the G2(19 pin of chip 74HC540) level is by moving high level on the R3, restriction is exported.
2, power supply supervisory circuit
As shown in Figure 5, this partial circuit is received power supply 3.3V by the magnetic bead L1 of the 600/100KHZ of 3 pin serial connection of a power monitoring chip TPS3809K33, and 3 pin connect 104 over the ground filtering of capacitor C 1 simultaneously, 1 pin ground connection, and 2 pin are through 6 outputs of a 1K resistance R.
When supply voltage is lower than 2.93V, the 2 pin output low levels of TPS3809K33, when power supply rises to 2.93V, the reverse buffering of low level restriction that the A point continues a 200MS of output drives chip 74HC540 output, control chip DSP can finish initialization during this 200MS, 2 pin output high level behind the 200MS, the A point draws on R6 and is high level, the G2 pin that allows reverse buffering to drive chip 74HC540 is low level work, thereby the A point does not allow the control purpose exported when having realized that power supply is unstable.
3, bridge is not allow the control signal protective circuit exported at 1 o'clock simultaneously up and down
As shown in Figure 6, this partial circuit is comprised of four NAND gate and a diode D2, two pwm control signal UP and the UN of same brachium pontis meet the first NAND gate A, VP and VN meet the second NAND gate D, the input of the 3rd NAND gate C is received respectively in the output of these two NAND gate again, the output of the 3rd NAND gate C is reverse through the 4th NAND gate B, and the negative electrode of a diode D2 is received in the output of NAND gate B, and the anode of diode D2 is output.
As UP and UN(or VP and VN) when being high level 1 simultaneously, NAND gate A or D are output as 0, and NAND gate C is when having one to be input as 0, output (8 pin) is 1, NAND gate B output (6 pin) is 0, and diode D2 conducting is forced output C level point is dragged down, and does not allow output; When two groups of UP, UN and VP, VN respectively have one during for low level, NAND gate A and D export high level simultaneously, NAND gate C output (8 pin) is 0, NAND gate B output (6 pin) is high level 1, the C point is high-impedance state, can be high level by drawing on the resistance, allowing oppositely, the G2 pin of buffering driving chip 74HC540 is low level work.
Close eventually and state circuit, when pwm control signal UP, UN and VP, VN are not high level simultaneously, the C point is high-impedance state, when power supply 3.3V is normal, A point output high level, therefore, triode Q2 conducting, to oppositely cushion the G2(19 pin that drives chip 74HC540) force to drag down, allow reverse the buffering to drive chip 74HC540 output.Go to realize that pwm control circuit in the time restriction PWM output at uncertain state of the moment that powers on, pwm control signal, does not allow transistor work from this two aspect, with the reliability that improves bridge inverter main circuit work and stable.
Claims (4)
1. the straight-through protective circuit of a photovoltaic combining inverter; it is characterized in that; comprise a control signal protective circuit, a power supply supervisory circuit and one 8 reverse buffering drive circuits; this control signal protective circuit and this power supply supervisory circuit are in parallel, and its output all is connected with these 8 reverse buffering drive circuits.
2. circuit according to claim 1; it is characterized in that; described control signal protective circuit is comprised of four NAND gate and a diode D2; two pwm control signal UP of the same brachium pontis of the inverter bridge of photovoltaic combining inverter and UN connect respectively two inputs of the first NAND gate; in addition two control signal VP and VN connect respectively two inputs of the second NAND gate; the input of the 3rd NAND gate is received respectively in the output of this first NAND gate and the second NAND gate again; the output of the 3rd NAND gate is reverse through the 4th NAND gate; the negative electrode of a diode D2 is received in the output of the 4th NAND gate, and the anode of diode D2 is output.
3. circuit according to claim 1, it is characterized in that, described power supply supervisory circuit is received the 3.3V power supply by the magnetic bead L1 of the 600/100KHZ of 3 pin serial connection of a power monitoring chip TPS3809K33,3 pin connect an over the ground filtering of capacitor C 1 simultaneously, the 1 pin ground connection of power monitoring chip TPS3809K33,2 pin are through 6 outputs of a 1K resistance R.
4. circuit according to claim 1; it is characterized in that; described 8 reverse buffering drive circuits comprise that one oppositely cushions driving chip 74HC540; one resistance R 3; one capacitor C 3; one triode Q2 and a diode D1; the pwm control signal of the inverter bridge of described photovoltaic combining inverter is via this oppositely buffering driving chip 74HC540 output; oppositely the sheet selected control signal pins G1 processed of buffering driving chip 74HC540 is connected with the IO mouth of the control chip DSP of photovoltaic combining inverter; another sheet selected control signal pins G2 processed and resistance are that the resistance R 3 of 1K and the collector electrode of NPN triode Q2 join; resistance R 3 connection+5V power supplys; the grounded emitter of triode Q2; base stage links to each other with the negative electrode of diode D1, and the anode of diode D1 is connected with the output of described control signal protective circuit and power supply supervisory circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120481037 CN202772555U (en) | 2011-11-28 | 2011-11-28 | Shoot-through protection circuit of photovoltaic grid-connected inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120481037 CN202772555U (en) | 2011-11-28 | 2011-11-28 | Shoot-through protection circuit of photovoltaic grid-connected inverter |
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| CN202772555U true CN202772555U (en) | 2013-03-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201120481037 Expired - Lifetime CN202772555U (en) | 2011-11-28 | 2011-11-28 | Shoot-through protection circuit of photovoltaic grid-connected inverter |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103296917A (en) * | 2013-06-09 | 2013-09-11 | 江苏节高电子有限公司 | Full-bridge type inverter driving circuit |
| CN104104370A (en) * | 2014-06-30 | 2014-10-15 | 南京亚派科技实业有限公司 | PWM signal power-up and power-down protection circuit |
| CN104158158B (en) * | 2013-05-15 | 2017-04-05 | 深圳市海洋王照明工程有限公司 | The straight-through protection circuit of full-bridge and half-bridge inversion circuit |
| CN112737299A (en) * | 2020-12-29 | 2021-04-30 | 联合汽车电子有限公司 | Method, device and system for protecting high voltage on inverter of electric automobile |
| CN115206067A (en) * | 2022-07-11 | 2022-10-18 | 上海茵特格锐科技有限公司 | PWM signal alarm circuit for inverter |
-
2011
- 2011-11-28 CN CN 201120481037 patent/CN202772555U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158158B (en) * | 2013-05-15 | 2017-04-05 | 深圳市海洋王照明工程有限公司 | The straight-through protection circuit of full-bridge and half-bridge inversion circuit |
| CN103296917A (en) * | 2013-06-09 | 2013-09-11 | 江苏节高电子有限公司 | Full-bridge type inverter driving circuit |
| CN103296917B (en) * | 2013-06-09 | 2015-06-03 | 江苏节高电子有限公司 | Full-bridge type inverter driving circuit |
| CN104104370A (en) * | 2014-06-30 | 2014-10-15 | 南京亚派科技实业有限公司 | PWM signal power-up and power-down protection circuit |
| CN104104370B (en) * | 2014-06-30 | 2017-12-26 | 南京亚派科技股份有限公司 | A kind of pwm signal power on and off protection circuit |
| CN112737299A (en) * | 2020-12-29 | 2021-04-30 | 联合汽车电子有限公司 | Method, device and system for protecting high voltage on inverter of electric automobile |
| CN112737299B (en) * | 2020-12-29 | 2022-04-05 | 联合汽车电子有限公司 | Method, device and system for protecting high voltage on inverter of electric automobile |
| CN115206067A (en) * | 2022-07-11 | 2022-10-18 | 上海茵特格锐科技有限公司 | PWM signal alarm circuit for inverter |
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20130306 |
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| CX01 | Expiry of patent term |