CN202736448U - Lattice type VFD display screen protective circuit - Google Patents
Lattice type VFD display screen protective circuit Download PDFInfo
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- CN202736448U CN202736448U CN 201220134909 CN201220134909U CN202736448U CN 202736448 U CN202736448 U CN 202736448U CN 201220134909 CN201220134909 CN 201220134909 CN 201220134909 U CN201220134909 U CN 201220134909U CN 202736448 U CN202736448 U CN 202736448U
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Abstract
A lattice type VFD display screen protective circuit comprises a resistor R1, a capacitor C1, a triode Q1, a resistor R4, a capacitor C2, a resistor R5, a resistor R7 and a triode Q2. Periodic clock signals CLKA emitted by a CPU control the base electrode of the triode Q1 through a blocking coupling capacitor of the resistor R1 and the capacitor C1. A 5-volt power supply is connected with the emitter electrode of the triode Q1. The collector electrode of the triode Q1 is connected with the capacitor C2 through the resistor R4. The collector electrode of the triode Q1 is connected with the base electrode of the triode Q2 through the resistor R4 and the resistor R5. The 5-volt power supply is connected with the collector electrode of the triode Q2 through the resistor R7. The collector electrode of the triode Q2 is connected with the switch pin BKGO of a lattice type VFD display screen. The emitter electrode BKG of the triode Q2 is connected with the I/O pin of the CPU. By means of the clock pin CLKA which controls the lattice type VFD display screen and always demonstrates stable periodic pulse signals, the switch pin BKG of the display screen can be controlled by judging the presence or absence of the clock line and also by using the protective circuit and the CPU. The on-off of the display screen is then controlled.
Description
Technical field
The utility model relates to dot matrix VFD display screen, and the dot matrix VFD display screen that drives of internal high-voltage especially is mainly used in the demonstration of family's power amplifier.
Background technology
Home theater amplifier function development in recent years; function is more and more; exercisable function is also more and more; because VFD has fast response time; the advantage that contrast is high; still be widely used at present every field; in order to realize good man-machine interface; at present a lot of home theater amplifiers have all adopted dot matrix VFD to do demonstration; so that realize the prompting of various animation effects and Chinese character; because driving, dot matrix needs a lot of mouth lines; therefore this series products substantially all is the form that internal high-voltage drives chip; the outside is only controlled by the data port of one group of serial; transmit data; inside is finished and is shown the work that refreshes, and therefore the high bright spot of short time often can occur in the pause of the data clock in debug process and the power down process, thereby burns black fluorescent powder; cause the damage of display screen, greatly reduce the serviceable life of display screen.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of dot matrix VFD display screen holding circuit, the serviceable life that can improve dot matrix VFD display screen.
For solving the problems of the technologies described above, the technical solution of the utility model is: a kind of dot matrix VFD display screen holding circuit comprises resistance R 1, capacitor C 1, triode Q1, resistance R 4, capacitor C 2, resistance R 5, resistance R 7 and triode Q2; The periodicity clock signal clk A that CPU sends controls the base stage of triode Q1 every straight coupling capacitance by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU;
The periodicity clock signal clk A control triode Q1 periodically conducting of CPU by sending;
After the conducting of triode Q1 periodicity ,+5V power supply gives capacitor C 2 chargings by triode Q1 and resistance R 4;
When holding circuit received the CLKA signal that CPU sends, the I/O human hair combing waste of CPU went out low level the emitter BKG current potential of triode Q2 is dragged down, and making the switch pin BKGO that is connected with triode Q2 collector is low level, and this moment, VFD shielded normal demonstration work;
When machine was in holding state, the I/0 pin of CPU output high level was drawn high the emitter BKG current potential of triode Q2, and making the switch pin BKGO that is connected with triode Q2 collector is high level, and display screen is closed;
When normal machines shutdown or suddenly power down; the periodicity clock signal clk A that holding circuit receives is low level; at this moment triode Q1, Q2 cut-off; this moment because+the 5V power supply has reason or the high level of large electric capacity accumulate; the switch pin BKGO that is connected with triode Q2 collector so just is high level, has turned off demonstration, avoids because of suddenly power down at once; local Chang Liang appears in the middle of causing display screen, thus protection VFD display screen.
As improvement: be provided with resistance R 3 between the base stage of described+5V power supply and triode Q1, be provided with resistance R 2 between the base stage of triode Q1 and the ground; Be provided with resistance R 6 between the base stage of triode Q2 and the ground.
As improvement, described holding circuit also comprises the switching power supply that is electrically connected with external communication, described switching power supply comprises filtering circuit and mu balanced circuit, described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen; Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal of CPU control pin STBY, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.CPU sends standby signal STBY by resistance R 11 control triode Q3 conductings, and the conducting of triode Q3 causes triode Q4 cut-off, thereby cuts off the anode high voltage+45V of display screen, also turns off filament simultaneously, protects thoroughly display screen.
As improvement, be provided with diode D600, D601 between described external communication electricity and the filtering circuit, the effect of diode is that alternating current is become direct current.
As improvement, described CPU is 32 high-speed CPUs, and model is STM32F101.
The beneficial effect that the utility model compared with prior art brings is:
Utilize the clock pin CLKA of reference mark configuration VFD display screen is stable cyclic pulse signal always; come the switch pin BKGO of control display screen by have or not join protection circuit and the CPU that judges this clock lines; thereby the Push And Release of control display screen plays the effect of protection display screen.
Description of drawings
Fig. 1 is the utility model circuit frame figure.
Fig. 2 is CPU pin schematic diagram.
Fig. 3 is the utility model circuit theory diagrams.
Embodiment
The utility model is described in further detail below in conjunction with Figure of description.
As shown in Figure 1, 2, the present embodiment is take the dot matrix VFD display screen of the MN12864K of Japanese Noritake company as example, this display screen is 128 * 64 dot matrix screen, internal high-voltage drives, the digital signal access, can directly connect high speed MCU, the present embodiment CPU is 32 high-speed CPUs, and model is STM32F101.
As shown in Figure 3, dot matrix VFD display screen holding circuit comprises resistance R 1 ~ R7, capacitor C 1, capacitor C 2, triode Q1, triode Q2.The periodicity clock signal clk A that CPU sends controls the base stage of triode Q1 every straight coupling capacitance by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU; Described resistance R 3 is arranged on+base stage of 5V power supply and triode Q1 between; Resistance R 2 is arranged between the base stage and ground of triode Q1; Resistance R 6 is arranged between the base stage and ground of triode Q2.
Described holding circuit also comprises the switching power supply that is electrically connected with external communication, and described switching power supply comprises filtering circuit and mu balanced circuit.Described filtering circuit is comprised of capacitor C 601, the C602 of parallel connection, and the external communication electricity is powered to mu balanced circuit by diode D600, D601, filtering circuit.Described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen.Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal of CPU control pin STBY, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.
Principle of work of the present utility model is as follows:
The periodicity clock signal clk A control triode Q1 periodically conducting of CPU by sending;
After the conducting of triode Q1 periodicity ,+5V power supply gives capacitor C 2 chargings by triode Q1 and resistance R 4;
When holding circuit received the CLKA signal that CPU sends, the I/O human hair combing waste of CPU went out low level the emitter BKG current potential of triode Q2 is dragged down, and making the switch pin BKGO that is connected with triode Q2 collector is low level, and this moment, VFD shielded normal demonstration work;
When machine was in holding state, the I/0 pin of CPU output high level was drawn high the emitter BKG current potential of triode Q2, and making the switch pin BKGO that is connected with triode Q2 collector is high level, and display screen is closed; CPU sends standby signal STBY by resistance R 11 control triode Q3 conductings simultaneously, and the conducting of triode Q3 causes triode Q4 cut-off, thereby cuts off the anode high voltage+45V of display screen, also turns off filament simultaneously, protects thoroughly display screen.
When normal machines shutdown or suddenly power down; the periodicity clock signal clk A that holding circuit receives is low level; at this moment triode Q1, Q2 cut-off; this moment because+the 5V power supply has reason or the high level of large electric capacity accumulate; the switch pin BKGO that is connected with triode Q2 collector so just is high level, has turned off demonstration, avoids because of suddenly power down at once; local Chang Liang appears in the middle of causing display screen, thus protection VFD display screen.
In the machine simulating developer stage; can be to interrupt sending number to display screen at debugging problem often, so also be easy to cause the local Chang Liang of display screen to cause damaging, in case periodically clock signal clk A stops to send number; just turn off display screen and show, thereby reach the protection effect at once.
Claims (5)
1. a dot matrix VFD display screen holding circuit is characterized in that: comprise resistance R 1, capacitor C 1, triode Q1, resistance R 4, capacitor C 2, resistance R 5, resistance R 7 and triode Q2; The periodicity clock signal clk A that CPU sends controls the base stage of triode Q1 every straight coupling capacitance by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU.
2. a kind of dot matrix VFD display screen holding circuit according to claim 1 is characterized in that: be provided with resistance R 3 between the base stage of described+5V power supply and triode Q1, be provided with resistance R 2 between the base stage of triode Q1 and the ground; Be provided with resistance R 6 between the base stage of triode Q2 and the ground.
3. a kind of dot matrix VFD display screen holding circuit according to claim 1, it is characterized in that: described holding circuit also comprises the switching power supply that is electrically connected with external communication, described switching power supply comprises filtering circuit and mu balanced circuit, described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen; Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal of CPU control pin STBY, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.
4. a kind of dot matrix VFD display screen holding circuit according to claim 3 is characterized in that: be provided with diode D600, D601 between described external communication electricity and the filtering circuit.
5. a kind of dot matrix VFD display screen holding circuit according to claim 1, it is characterized in that: described CPU is 32 high-speed CPUs, and model is STM32F101.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220134909 CN202736448U (en) | 2012-04-01 | 2012-04-01 | Lattice type VFD display screen protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220134909 CN202736448U (en) | 2012-04-01 | 2012-04-01 | Lattice type VFD display screen protective circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202736448U true CN202736448U (en) | 2013-02-13 |
Family
ID=47662124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220134909 Expired - Lifetime CN202736448U (en) | 2012-04-01 | 2012-04-01 | Lattice type VFD display screen protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202736448U (en) |
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2012
- 2012-04-01 CN CN 201220134909 patent/CN202736448U/en not_active Expired - Lifetime
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130213 |
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| CX01 | Expiry of patent term |