CN202720272U - Adaptive frequency measurement circuit - Google Patents

Abstract

The utility model discloses an adaptive frequency measurement circuit, relates to the technical field of turbine control, and the technical problem to be solved in the utility model is the rotating speed measurement in the full range. The circuit comprises a MPU chip, a CPLD chip, and a clock reference signal generating source. Two D triggers and two counters are arranged in the CPLD chip. The D end of the first D trigger is connected to the gate control end of the MPU chip, and the Q end of the first D trigger is connected to the gate status feedback end of the MPU chip and connected to the CE ends of the two counters. The frequency input pin of the CPLD chip is connected to the C end of the first D trigger and the C end of the first counter. The Q end of the second D trigger is connected to the overflow status feedback end of the MPU chip, the CLR end of the second D trigger is connected to the overflow flag clearing end of the MPU chip, and the D end of the second D trigger is connected to the OF end of the second counter. The data output ends of the two counters are connected to the MPU chip separately. The circuit provided in the utility model is applicable to monitor the rotating speed of a turbine.

Description

The self-adaptation frequency measurement circuit

Technical field

The utility model relates to the steam turbine control technology, particularly relates to a kind of technology of self-adaptation frequency measurement circuit.

Background technology

In the Control System of Rotational Speed of Steam Turbine, accuracy and requirement of real-time that turbine speed is gathered are very high.In the existing turbine speed acquisition method, the more a kind of method of using at present Deng the Precision Measuring Frequency method, as shown in Figure 4, it is that gate time of presetting of definite value is t that the method presets first a duration, after t1 sends the gate opening order constantly, begin to preset the timing of t gate time, and the t2 that arrives at first rising edge of subsequently measured signal s1 constantly, beginning is counted the pulse number of measured signal s1 and clock reference signal s0 simultaneously, send the closing gate order at the moment t3 that presets t timing end gate time, and the t4 that arrives at first rising edge of subsequently measured signal s1 constantly, stop simultaneously the counting of measured signal s1 and clock reference signal s0, actual gate time, t ' began constantly to finish to t4 from t2 constantly, if the frequency of measured signal s1 is Fc, the frequency of clock reference signal s0 is Fd, the counted number of pulses of measured signal s1 is Nc, the counted number of pulses of clock reference signal s0 is Nd, and the frequency that then can calculate measured signal s1 is: Fc=(Fd/Nd) * and Nc.

Very good Deng Precision Measuring Frequency method working condition when turbine speed is higher, but the range of speeds of steam turbine is wider, generally will from zero to several thousand rev/mins, can produce two kinds of situations when therefore waiting Precision Measuring Frequency method to measure the slow-speed of revolution in actual applications.

The first situation as shown in Figure 5, at the gate time of presetting of rising edge without tested tach signal s1 in the t, preset in this situation and be carved into t3 gate time when t is from t1 constantly, actual t ' gate time equals 0, counter is not activated the step-by-step counting to clock reference signal s0 at all, thereby causes the frequency measurement failure.

The second situation as shown in Figure 6, in the single cycle of tested tach signal s1, the number of pulses of clock reference signal s0 is greater than the counting region of counter, preset in this situation and be carved into t3 gate time when t is from t1 constantly, be carved into t5 actual gate time when t ' is from t2 constantly, although actual gate opening, counter begins counting, but since the single excessive cycle of actual t ' gate time, the counter overflow in the t4 moment to clock reference signal s0 counting, thus cause the frequency measurement failure.

Suppose that magnetoresistive transducer produces 60 pulse signals when steam turbine whenever turns around, when presetting when being set in 5ms gate time, turbine speed is less than 200 rev/mins (respective frequencies 200Hz) so, and this moment, situation shown in Figure 5 will occur; When using 16 digit counters, when the reference clock frequency was 2500kHz, turbine speed was during less than 38 rev/mins (respective frequencies 38Hz), and the situation of overflowing shown in Figure 6 will occur counter.

Summary of the invention

For the defective that exists in the above-mentioned prior art, technical problem to be solved in the utility model provides a kind of high rotating speed and the slow-speed of revolution situation that can take into account steam turbine, can realize the self-adaptation frequency measurement circuit of gamut tachometric survey.

In order to solve the problems of the technologies described above, a kind of self-adaptation frequency measurement circuit provided by the utility model is characterized in that: comprise the MPU chip, CPLD chip, clock reference signal generating source;

Described MPU chip is provided with gate control end, reset terminal, gate feedback of status end, overflow status feedback end, overflow indicator removing end, and is provided with two groups of data receivers;

Described CPLD chip is provided with a frequency input pin, and is built-in with two d type flip flops and two counters, and described two d type flip flops are respectively the first d type flip flop, the second d type flip flop, and described two counters are respectively the first counter, the second counter;

The D of described the first d type flip flop terminates to the gate control end of MPU chip, and the Q of the first d type flip flop terminates to the gate feedback of status end of MPU chip, and is connected to the CE end of the first counter and the second counter;

The frequency input pin of described CPLD chip is received the C end of the first d type flip flop and the C end of the first counter;

The Q of described the second d type flip flop terminates to the overflow status feedback end of MPU chip, and the CLR of the second d type flip flop terminates to the overflow indicator of MPU chip and removes end, and the D of the second d type flip flop terminates to the OF end of the second counter;

The C termination clock reference signal generating source of described the second counter;

The CLR of described the first d type flip flop, the first counter and the second counter terminates to the reset terminal of MPU chip;

The data output end of the data output end of described the first counter and the second counter is received respectively two groups of data receivers of MPU chip.

Further, described the first counter is 8 digit counters, and described the second counter is 16 digit counters.

The self-adaptation frequency measurement circuit that the utility model provides, utilize the first d type flip flop to catch the rising edge of tested frequency signal, the MPU chip is adjusted gate time according to the feedback signal self-adaptation of the first d type flip flop, can avoid the frequency measurement failure that causes without tested tach signal rising edge in gate time because presetting; By the processing to the second counter overflow signal, avoided the frequency measurement failure that causes because the clock reference signal-count is overflowed; Therefore high rotating speed and the slow-speed of revolution situation of steam turbine can be taken into account, the gamut tachometric survey can be realized.

Description of drawings

Fig. 1 is the structural representation of the self-adaptation frequency measurement circuit of the utility model embodiment;

Fig. 2 is the circuit diagram in the Adjustment of sensitivity loop in the self-adaptation frequency measurement circuit of the utility model embodiment;

Fig. 3 is the circuit diagram in the input shaper loop in the self-adaptation frequency measurement circuit of the utility model embodiment;

Fig. 4 is the existing measuring frequency principle synoptic diagram that waits the Precision Measuring Frequency method;

Fig. 5 has now when waiting frequency measurement of Precision Measuring Frequency method, causes the synoptic diagram of frequency measurement failure within the gate time of presetting without tested tach signal rising edge;

Fig. 6 has now when waiting frequency measurement of Precision Measuring Frequency method, and the single cycle inside counting device of tested tach signal overflows the synoptic diagram that causes the frequency measurement failure.

Embodiment

Below in conjunction with description of drawings embodiment of the present utility model is described in further detail, but present embodiment is not limited to the utility model, every employing analog structure of the present utility model and similar variation thereof all should be listed protection domain of the present utility model in.

As shown in Figure 1, a kind of self-adaptation frequency measurement circuit that the utility model embodiment provides is characterized in that: comprise MPU chip U1(microprocessor), CPLD chip U2(complex programmable logic chip), the clock reference signal generating source;

Described MPU chip U1 is provided with gate control end CMD, reset terminal RST, gate feedback of status end CMDST, overflow status feedback end OvF, overflow indicator removing end OvFRst, and is provided with two groups of data receiver P1, P2;

Described CPLD chip U2 is provided with a frequency input pin Fx, and be built-in with two d type flip flops and two counters, described two d type flip flops are respectively the first d type flip flop U21, the second d type flip flop U22, described two counters are respectively the first counter U23, the second counter U24, described the first counter U23 is 8 digit counters, and described the second counter U24 is 16 digit counters;

The D end (data input pin) of described the first d type flip flop U21 is received the gate control end CMD of MPU chip U1, the Q end (positive output end) of the first d type flip flop U21 is received the gate feedback of status end CMDST of MPU chip U1, and is connected to the CE end (Enable Pin) of the first counter U23 and the second counter U24;

The frequency input pin Fx of described CPLD chip U2 receives the C end (input end of clock) of the first d type flip flop U21 and the C end (input end of clock) of the first counter U23;

The Q end (positive output end) of described the second d type flip flop U22 is received the overflow status feedback end OvF of MPU chip U1, the CLR end (clear terminal) of the second d type flip flop U22 is received the overflow indicator of MPU chip U1 and is removed end OvFRst, and the D end (data input pin) of the second d type flip flop U22 is received the OF end (overflow status end) of the second counter U24;

The C end (input end of clock) of described the second counter U24 connects the clock reference signal generating source;

The CLR end (clear terminal) of described the first d type flip flop U21, the first counter U23 and the second counter U24 is received the reset terminal RST of MPU chip U1;

((Q0～Q15) receives respectively two groups of data receiver P1, P2 of MPU chip U1 to the data output end of described the first counter U23 for Q0～Q7) and the data output end of the second counter U24.

Among the utility model embodiment, described clock reference signal generating source is prior art, be the signal generating circuit for outputting stable frequency clock reference signal, the frequency of the clock reference signal that the clock reference signal generating source of the utility model embodiment is exported is 2.5MHZ.

The utility model embodiment also comprises Adjustment of sensitivity loop, input shaper loop.

As shown in Figure 2, described Adjustment of sensitivity loop comprises comparer U4 and two jumper wire devices, and described two jumper wire devices are respectively the first jumper wire device J21, the second jumper wire device J22;

Described the first jumper wire device J21 has a common port, two selecting sides, and described the second jumper wire device J22 has two common ports, four selecting sides;

Two common ports of the common port of described the first jumper wire device J21 and the second jumper wire device J22 are received respectively the inverting input of comparer U4;

Each connects positive voltage through the different divider resistance of resistance each selecting side of described the first jumper wire device J21, and each meets the negative signal output terminal S2-of external frequency source each selecting side of described the second jumper wire device J22 through the different divider resistance of resistance;

The normal phase input end of described comparer U4 is received the positive signal output terminal S2+ of external frequency source, and the output terminal of comparer U4 is received the input end F2 in input shaper loop through a resistance;

During described Adjustment of sensitivity loop works, after converting the high-low level frequency signal to, the frequency signal to be measured that comparer U4 exports external frequency source outputs to the input shaper loop, choose the threshold voltage that different divider resistances can be regulated comparer U4 by wire jumper, realize the measurement Adjustment of sensitivity to the measured signal of external frequency source output.

Shown in Figure 3, described input shaper loop comprises optical coupling isolator U5 and two phase inverters, and described two phase inverters are respectively the first phase inverter U6, the second phase inverter U7;

The input end of described optical coupling isolator U5 consists of the input end F2 in input shaper loop, the input end of described the first phase inverter U6 is received the output terminal of optical coupling isolator U5 through resistance and electric capacity, the input end of described the second phase inverter U7 is received the output terminal of the first phase inverter U6, and the output terminal of the second phase inverter U7 is received the frequency input pin Fx of CPLD chip U2;

During described input shaper loop works, first by the high-low level frequency signal light-coupled isolation of optical coupling isolator U5 to the output of Adjustment of sensitivity loop, again by a shaping of the first phase inverter U6, again by outputing to the frequency input pin Fx of CPLD chip U2 after the second phase inverter U7 secondary reshaping, to guarantee the quality of measuring-signal.

The utility model embodiment is applicable to monitor turbine speed, speed-frequency with steam turbine during use accesses the Adjustment of sensitivity loop as external frequency source, through the conversion of Adjustment of sensitivity loop, behind the input shaper loop shaping, be input to again the frequency input pin Fx of CPLD chip U2.

The frequency measuring method of the self-adaptation frequency measurement circuit that the utility model embodiment provides is as follows:

MPU chip U1 sets first the gate timer that a duration is definite value (such as 5ms), and the gate chronotron that duration is definite value (such as 40ms), and then from the instruction of gate control end CMD output throttle valve, and startup gate timer begins to open a sluice gate timing;

After the D end (data input pin) of the first d type flip flop U21 is received the throttle valve instruction, if the source frequency signal capture that receives from its C end (input end of clock) is to rising edge, then open a sluice gate feedback signal to the gate feedback of status end CMDST of MPU chip U1 from its Q end (positive output end) output, the CE end (Enable Pin) that triggers simultaneously the first counter U23 and the second counter U24 enables effectively, make the first counter U23 begin the source frequency signal that self C end (input end of clock) receives is carried out step-by-step counting, make the second counter U24 begin the clock reference signal that self C end (input end of clock) receives is carried out step-by-step counting;

After MPU chip U1 begins to open a sluice gate timing, if receiving, the gate feedback of status end CMDST of MPU chip U1 do not open a sluice gate feedback signal in the setting duration of gate timer, then starting the gate chronotron begins one and opens a sluice gate the timing of delaying time, otherwise then close the gate instruction from its gate control end CMD output, and reset and restart the gate timer, the timing of beginning barrier gate;

After MPU chip U1 begins the timing of opening a sluice gate to delay time, if receiving, the gate feedback of status end CMDST of MPU chip U1 do not open a sluice gate feedback signal in the setting duration of gate chronotron, then reset and restart the gate chronotron, the beginning next one is opened a sluice gate the timing of delaying time, otherwise then close the gate instruction from its gate control end CMD output, and reset and restart the gate timer, the timing of beginning barrier gate;

MPU chip U1 adds up each time open a sluice gate to delay time clocking value of timing, the aggregate-value of timing reaches 1 second if each time opened a sluice gate to delay time, and the gate feedback of status end CMDST of MPU chip U1 does not receive yet and opens a sluice gate feedback signal, judges that then the gate time of source frequency signal was greater than 1 second;

After the D end (data input pin) of the first d type flip flop U21 is received and is closed the gate instruction, if the source frequency signal capture that receives from its C end (input end of clock) is to rising edge, then export barrier gate feedback signal to the gate feedback of status end CMDST of MPU chip U1 from its Q end (positive output end), it is invalid that the CE end (Enable Pin) that triggers simultaneously the first counter U23 and the second counter U24 enables, and makes the first counter U23 and the second counter U24 stop counting;

After MPU chip U1 begins the barrier gate timing, if the gate feedback of status end CMDST of MPU chip U1 does not receive the barrier gate feedback signal in the setting duration of gate timer, then start the gate chronotron and begin a barrier gate time-delay timing, otherwise then calculate the frequency of source frequency signal;

After MPU chip U1 begins a barrier gate time-delay timing, if the gate feedback of status end CMDST of MPU chip U1 does not receive the barrier gate feedback signal in the setting duration of gate chronotron, then reset and restart the gate chronotron, begin next barrier gate time-delay timing, otherwise then calculate the frequency of source frequency signal;

MPU chip U1 adds up the clocking value of each time barrier gate time-delay timing, if the aggregate-value of each time barrier gate time-delay timing reaches 1 second, and the gate feedback of status end CMDST of MPU chip U1 does not receive the barrier gate feedback signal yet, judges that then the gate time of source frequency signal was greater than 1 second;

It is 0 the counter that overflows that described MPU chip U1 also presets an initial value, the Q of the second d type flip flop U22 end is exported a not spill under the original state, after the gate instruction is closed in MPU chip U1 output, when the second counter U24 counts up to when overflowing, its OF end (overflow status end) is namely exported the D end (data input pin) of spill over to the second a d type flip flop U22, trigger immediately spill over of Q end (positive output end) output of the second d type flip flop U22 to the overflow status feedback end OvF of MPU chip U1, after MPU chip U1 receives spill over from overflow status feedback end OvF, add 1 with the count value that is about to overflow counter, and remove clear command of end OvFRst output from overflow indicator and make the second d type flip flop U22 zero clearing that resets, one of Q end (positive output end) output that makes the second d type flip flop U22 is spill over not;

The first counter U23 and the second counter U24 pass to MPU chip U1 in real time with the counted number of pulses of source frequency signal and the counted number of pulses of clock reference signal respectively, the count value that MPU chip U1 transmits according to the first counter U23 and the second counter U24 is calculated the frequency of source frequency signal, and specific formula for calculation is:

Fa=[Fb/(y×Nmax＋Nb)]×Na；

In the formula, Fa is the frequency values of source frequency signal, Na is the counted number of pulses of the first counter, Fb is the frequency values of clock reference signal, Nb is the counted number of pulses of the second counter, and y is the count value of overflowing counter, and Nmax is the counting higher limit of the second counter, the second counter is 16 digit counters in the present embodiment, its counting higher limit Nmax=65535;

Described source frequency signal refers to change through the Adjustment of sensitivity loop, be input to the frequency signal that derives from external frequency source (steam turbine) of the frequency input pin Fx of CPLD chip U2 behind the input shaper loop shaping, described clock reference signal is the frequency signal by the output of clock reference signal generating source again.

Among the utility model embodiment, whenever finish one-shot measurement after, reset signal of the reset terminal RST of MPU chip U1 output makes the first d type flip flop U21, the first counter U23 and the second counter U24 zero clearing that resets.

Claims (2)

1. a self-adaptation frequency measurement circuit is characterized in that: comprise the MPU chip, CPLD chip, clock reference signal generating source;

Described MPU chip is provided with gate control end, reset terminal, gate feedback of status end, overflow status feedback end, overflow indicator removing end, and is provided with two groups of data receivers;

Described CPLD chip is provided with a frequency input pin, and is built-in with two d type flip flops and two counters, and described two d type flip flops are respectively the first d type flip flop, the second d type flip flop, and described two counters are respectively the first counter, the second counter;

The D of described the first d type flip flop terminates to the gate control end of MPU chip, and the Q of the first d type flip flop terminates to the gate feedback of status end of MPU chip, and is connected to the CE end of the first counter and the second counter;

The frequency input pin of described CPLD chip is received the C end of the first d type flip flop and the C end of the first counter;

The Q of described the second d type flip flop terminates to the overflow status feedback end of MPU chip, and the CLR of the second d type flip flop terminates to the overflow indicator of MPU chip and removes end, and the D of the second d type flip flop terminates to the OF end of the second counter;

The C termination clock reference signal generating source of described the second counter;

The CLR of described the first d type flip flop, the first counter and the second counter terminates to the reset terminal of MPU chip;

The data output end of the data output end of described the first counter and the second counter is received respectively two groups of data receivers of MPU chip.

2. self-adaptation frequency measurement circuit according to claim 1, it is characterized in that: described the first counter is 8 digit counters, described the second counter is 16 digit counters.

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