CN202696578U

CN202696578U - Proportional timing and sampling circuit and switching power supply using proportional timing and sampling circuit

Info

Publication number: CN202696578U
Application number: CN 201220292669
Authority: CN
Inventors: 高耿辉; 叶英; 王利; 李铎
Original assignee: Fujian Fushun Microelectronics Co ltd; DALIAN LIANSHUN ELECTRONICS CO LTD; Unisonic Technologies Co Ltd
Current assignee: Fujian Fushun Microelectronics Co ltd; DALIAN LIANSHUN ELECTRONICS CO LTD; Unisonic Technologies Co Ltd
Priority date: 2012-06-21
Filing date: 2012-06-21
Publication date: 2013-01-23
Anticipated expiration: 2022-06-21

Abstract

The utility model relates to a proportional timing and sampling circuit and a switching power supply using the proportional timing and sampling circuit. The proportional timing and sampling circuit is formed by electrically connecting a sampling control circuit, a first sampling clock generating unit, a second sampling clock generating unit and a delay unit in sequence; proportional sampling can be performed accurately by setting the ratio of two capacitance values; meanwhile, periodic sampling can be performed following the demagnetization time of a system; the switching power supply comprises a transformer and a control circuit, and is characterized in that the pulse width and the pulse frequency of the transformer can be adjusted precisely by performing periodic proportional sampling on a feedback winding unit of the transformer by the control circuit; the control circuit comprises the proportional timing and sampling circuit; and higher constant-voltage output precision can be realized by the switching power supply.

Description

A kind of ratio timing sampling circuit and use the Switching Power Supply of this circuit

Technical field

The utility model relates to a kind of ratio timing sampling circuit and uses the Switching Power Supply of this sample circuit.

Background technology

Use the Switching Power Supply of traditional controller as shown in Figure 1, this Switching Power Supply comprises that output module is connected in the auxiliary winding two ends of transformer T1, absorbing circuit is connected in the main winding two ends of transformer T1, the drain electrode of switching tube Q1 links to each other with main winding one end, grid links to each other with the output of traditional controller 20, source electrode links to each other with sampling resistor Rcs, controller 20, and the feedback winding element links to each other with controller; This controller comprises that sampling switch links to each other with PWM/PFM modulator 22 with sample circuit 32, feedback winding element; PWM/PFM modulator 22 links to each other with sampling resistor Rcs, logical drive 23, and logical drive 23 links to each other with switching tube Q1.

Controller 20 is by voltage signal 33 samplings of 21 pairs of feedbacks of inner sample circuit winding input, the size of the sampled signal 34 reflection output voltage V o that obtain, signal 36 on 22 pairs of these sampled signals of PWM/PFM modulator 34 and the sampling resistor relatively, the output modulation signal is to logical drive 23, logical drive 23 is adjusted pulse duration and the frequency of switching tube Q1, and then pulse duration and the frequency of adjustment transformer main winding, regulated output voltage Vo is to reach constant voltage output.

Clock signal 31 controls of the inside sample circuit 21 controlled device inside of traditional controller 20, when the clock signal 31 of controller inside is inconsistent with signal 33 phase places of feedback winding, sampling error will appear, shown in Fig. 2 (a), PWM/PFM modulator 22 is processed the sampled signal 34 that error is arranged, and obtains pulse duration and a frequency that the modulation signal control transformer of error is arranged.And then cause Switching Power Supply constant voltage output Vo precision not high.

The inside sample circuit of traditional controller 20 also can adopt the method for timing sampling, when feedback winding signal 33 changes, also sampling error can occur, shown in Fig. 2 (b), causes Switching Power Supply constant voltage output Vo precision not high.

In order to address the above problem, need to provide a kind of novel ratio timing sampling circuit to reach the high-precision constant voltage output of Switching Power Supply.

Summary of the invention

The utility model has proposed ratio timing sampling circuit for the problems referred to above, and this circuit can be applicable to Switching Power Supply, makes the output constant voltage can reach degree of precision.

The technical solution of the utility model is: a kind of ratio timing sampling circuit is characterized in that: be electrically connected successively by sampling control circuit, the first sampling clock generating unit, the second sampling clock generating unit and delay unit and form.

Further, described sampling control circuit comprises the first bias current sources, the first capacitor, the second capacitor and comparator, described the first bias current sources links to each other with the top crown of the 3rd switch with the first capacitor through the first switch, the top crown of described the first capacitor is connected to the ground through the 3rd switch and second switch, positive input terminal through the 5th switch and described comparator links to each other, negative input end through the 6th switch and described comparator links to each other, the positive input terminal of described comparator is connected to the ground through the 4th switch, the negative input end of described comparator links to each other with the top crown of the second capacitor, be connected to ground through the minion pass, be connected to ground through the 8th switch, the bottom crown of described the first capacitor, the bottom crown of the second capacitor is connected to the ground, the output of described comparator through first with the door, the first delayer and second and door produce a sampling control signal and control the 8th switch.

Further, described the first sampling clock generating unit comprise the first inverter, the second delayer, the second inverter and the 3rd with door, described the first inverter is controlled the 3rd switch and the 5th switch through the second delayer, described the second delayer is through the second inverter controlling the 4th switch and the 6th switch, and described the first inverter and the second delayer close with the gate control minion through the 3rd.

Further, described the second sampling clock generating unit comprise the 3rd delayer, the 4th with the door and the 3rd inverter, described the 3rd delayer through the 4th with the gate control second switch, the 4th with Men Jingdi three inverter controlling the first switch.

Further, described delay unit comprises the second bias current sources, delay capacitor, Schmidt trigger and the 4th inverter, input control the 9th switch and the tenth switch of described delay unit, internal power supply is connected to the top crown of delay capacitor through the 9th switch, the top crown of delay capacitor is connected to ground through the tenth switch and the second bias current sources, be connected to the output of described delay unit through Schmidt trigger and the 4th inverter, the bottom crown of the second delay capacitor is connected to ground.

Further, described ratio timing sampling circuit is integrated in the integrated package.

Another purpose of the present utility model is to provide a kind of Switching Power Supply of using aforementioned proportion timing sampling circuit, and this Switching Power Supply can reach the constant voltage output of degree of precision.

Another technical scheme of the present utility model is: a kind of application rights requires the Switching Power Supply of 1 described ratio timing sampling circuit, comprise transformer and control circuit, it is characterized in that: described control circuit links to each other with the feedback winding element of transformer, regulate pulse duration and the frequency of described transformer to produce a switching signal, described control circuit comprises ratio timing sampling circuit and PWM/PFM modulator.

Further, described ratio timing sampling circuit and PWM/PFM modulator are integrated in the integrated package.

The utility model has the advantage of: the clock of this ratio timing sampling circuit determines by the demagnetization time signal of feedback winding, the sampling error of having avoided the phase difference of internal clocking and feedback winding demagnetization signal to cause; This ratio timing sampling circuit is exported sampling clock in proportion, has eliminated the sampling error that timing sampling causes, so that use the constant voltage output that Switching Power Supply of the present utility model reaches degree of precision.

Description of drawings

Fig. 1 is traditional switch power principle schematic block diagram.

Fig. 2 is traditional switch power supply sampling schematic diagram.

Fig. 3 is the connection diagram of the utility model ratio timing sampling circuit.

Fig. 4 is based on the Switching Power Supply schematic block diagram of ratio timing sampling circuit.

Fig. 5 is based on the Switching Power Supply sampling schematic diagram of ratio timing sampling circuit.

The primary clustering symbol description:

103: sampling control circuit

104: the first sampling clock generating unit

105: the second sampling clock generating unit

106: delay unit

20,1020: controller

22,1022:PWM/PFM modulator (pulse duration/pulse frequency modulator)

23,1023: logical drive

Q1: switching transistor

T1: transformer

D1: diode

C1, C2, Cdelay, Co: capacitor

Rfbh, Rfbl, Rcs: resistance

Vin: input voltage

Vo: output voltage

N1, N2, N3:NMOS transistor

The P1:PMOS transistor

K1, K2, K3, K4, K5, K6, K7, K8, K9, K10: switch

Vdd: supply power voltage

Tdemag: system's demagnetization time signal

Tsp: controlling of sampling clock

Ton: the ON time of switching tube Q1

Toff: the turn-off time of switching tube Q1.

Embodiment

Below in conjunction with drawings and Examples the utility model is described further.

The utility model discloses a kind of ratio timing sampling circuit, it is characterized in that: by sampling control circuit, the first sampling clock generating unit, the second sampling clock generating unit and delay unit are electrically connected composition successively, specifically referring to Fig. 3, Fig. 3 is the circuit connection diagram of the ratio timing sampling circuit of the present embodiment, the input of the ratio timing sampling circuit described in the figure links to each other with the tdemag signal, output links to each other with the output of door 122 with second, the first bias current sources 101 links to each other with the first capacitor C 1 top crown 143 with the 3rd K switch 3 through the first K switch 1, the top crown 143 of the first capacitor C 1 is connected to the ground through the 3rd K switch 3 and second switch K2, positive input terminal 141 through the 5th K switch 5 and comparator 102 links to each other, link to each other with the negative input end 142 of comparator 102 through the 6th K switch 6, the positive input terminal 141 of comparator 102 is connected to the ground through the 4th K switch 4, the negative input end 142 of comparator 102 links to each other with the top crown of the second capacitor C2, the negative input end 142 of comparator 102 closes K7 through minion and is connected to ground, be connected to ground through the 8th switch K8, the bottom crown of the first capacitor C 1, the bottom crown of the second capacitor C 2 is connected to the ground, the output of comparator 102 through first with the door 121, the first delayer 131 and second and door 122 produce sampling control signal tsp, tsp controls the 8th switch K8.

The first sampling clock produces circuit 104 and is comprised of with door 123 electric connections the first inverter 111, the second inverter 112, delayer 132, the 3rd, produce control signal t1 and control the 3rd K switch 3 and the 5th K switch 5, produce control signal t1n and control the 4th K switch 4 and the 6th K switch 6, produce control signal 145 control minions and close K7.

The second sampling clock produces circuit 105 and is comprised of with door 124 electric connections the 3rd inverter 113, the 3rd delayer 133, the 4th, produces control signal t2 control second switch K2, produces control signal t2n and controls the first K switch 1.

Delay unit 106 is by the second bias current sources 152, the 9th K switch 9, the tenth K switch 10, delay capacitor Cdelay, Schmidt trigger 152 and the 4th inverter 114 form, input control the 9th K switch 9 and the tenth K switch 10 of delay unit 106, internal power supply Vdd is connected to the top crown of delay capacitor Cdelay through the 9th K switch 9, the top crown of delay capacitor Cdelay is connected to ground through the tenth K switch 10 and Schmidt trigger 152, be connected to the output of delay unit 106 through Schmidt trigger 152 and the 4th inverter 114, the bottom crown of delay capacitor Cdelay is connected to ground.

In order to allow those skilled in the art better understand the utility model, below in conjunction with circuit operation principle of the present utility model is further described:

See also Fig. 3, because the existence of delay unit, in each tdemag cycle, delay unit 132 produces the t1 clock signals, and t1n is t1 negate signal, and the 4th produces t2 clock signals with door 124, and t2n is t2 negate signal, and the 3rd produces 145 clock signals with door 123.

See also Fig. 5, when tdemag becomes high level, t2 is high level, and t1 also is high level, and the junction node of second switch K2 and the 3rd K3, the first K switch 1 is 144,144 because second switch K2 closure is earth potential, t2 is low level subsequently, and second switch K2 opens, the first K switch 1 closure, 144 by 101 chargings of the first bias current sources, and voltage linear rises.Since tdemag in the time t1 be high level always, so the 3rd K switch 3, the 5th K switch 5 closures, the top crown node of capacitor C 1 is 143, then 144 equate with 143 voltages, 101 pairs of C1 chargings of the first bias current sources, 143 voltage linears rise, and the second comparator 102 positive input terminal nodes are 141, then 141 equate with 144 node voltages with 143, and voltage is linear the rising also.

Until 141 equate with 142 node voltages, 102 upsets of the second comparator, tsp signal of the second inverter 122 outputs, K8 is closed, and 142 are pulled to ground.

141,143,144 node voltages continue to rise until t1 becomes low level, this moment, 143 node voltages were designated as V1, the 4th K switch 4, the 6th K switch 6 closures, the 3rd K switch 3, the 5th K switch 5 are opened, 141 nodes are pulled to ground, 144 and 143 nodes disconnect, and 143 electric charges on the first capacitor C 1 are redistributed by the first capacitor C 1 and the second capacitor C 2, and 142 node voltages equate with 143 node voltages.This moment, 142 node voltages were designated as V2, had:

142 nodes keep voltage V2 constant, until next tdemag high level arrives, t2 is high level, and t1 also is high level; Because second switch K2, the 3rd K switch 3, the 5th K switch 5 closures, 144,143,141 node voltages are pulled to and are ground, t2 is low level subsequently, second switch K2 opens, the first K switch 1 closure, then 144,143,141 node voltages equate, 1 charging of 101 pairs of the first capacitor C of the first bias current sources, and 141 voltage linears rise.

Until 141 equate with 142 node voltages, when also namely equaling V2,102 upsets of the second comparator, tsp signal of the second inverter 122 outputs, K8 is closed, and 142 are pulled to ground.

Repeated work like this.

As long as the ratio of C1 and C2 is set, just can obtains accurate ratio timing and be:

Figure 2012202926699100002DEST_PATH_IMAGE002

The Tsp sampling time is only relevant with the ratio of tdemag time, C1 and C2, irrelevant with internal clocking, as long as and C1 and C2 match and just can realize quite high-precision ratio, the tsp sampling time changed with the tdemag time, accomplished the demagnetization time timing sampling by system.

Be applied to by way of example in the power supply changeover device although be noted that the utility model here, the utility model itself has in addition wider range of application of example.

Fig. 4 is based on the Switching Power Supply of ratio timing sampling circuit, comprise that output module is connected in the auxiliary winding two ends of transformer T1, absorbing circuit is connected in the main winding two ends of transformer T1, the drain electrode of switching tube Q1 links to each other with main winding one end, grid links to each other with the output of using controller 1020 of the present utility model, and source electrode links to each other with sampling resistor Rcs, controller 1020.The feedback winding element links to each other with controller 1020.This controller comprises comparator 1021, ratio timing sampling circuit 100, sampling switch, PWM/PFM modulator 1022 and logical drive 1023.

Comparator 1021 detects feedback winding element signal 1030, export 1034 time signals, 1034 high level time is demagnetization time tdemag, ratio timing sampling circuit 100 is sampled to 1030 according to tdemag time signal adjustment output tsp sampling clock control sampling switch, obtaining sampled signal is 1031, the size of this signal reflection output voltage V o; Signal 1033 on 1022 pairs 1031 of PWM/PFM modulators and the sampling resistor is done computing, the output modulation signal is to logical drive 1023, logical drive 1023 is adjusted pulse duration and the frequency of switching tube Q1, and then width and the frequency of the main winding inductive current of adjustment transformer T1, regulated output voltage Vo.Because the tsp clock signal is in proportion output regularly, 1031 signals that obtain can accurately reflect the size of Vo, so can access accurate output voltage V o.

The above only is preferred embodiment of the present utility model, and all equalizations of doing according to the utility model claim change and modify, and all should belong to covering scope of the present utility model.

Claims

1. ratio timing sampling circuit is characterized in that: be electrically connected successively by sampling control circuit, the first sampling clock generating unit, the second sampling clock generating unit and delay unit and form.

2. a kind of ratio timing sampling circuit according to claim 1, it is characterized in that: described sampling control circuit comprises the first bias current sources, the first capacitor, the second capacitor and comparator, described the first bias current sources links to each other with the top crown of the 3rd switch with the first capacitor through the first switch, the top crown of described the first capacitor is connected to the ground through the 3rd switch and second switch, positive input terminal through the 5th switch and described comparator links to each other, negative input end through the 6th switch and described comparator links to each other, the positive input terminal of described comparator is connected to the ground through the 4th switch, the negative input end of described comparator links to each other with the top crown of the second capacitor, be connected to ground through the minion pass, be connected to ground through the 8th switch, the bottom crown of described the first capacitor, the bottom crown of the second capacitor is connected to the ground, the output of described comparator through first with the door, the first delayer and second and door produce a sampling control signal and control the 8th switch.

3. a kind of ratio timing sampling circuit according to claim 1, it is characterized in that: described the first sampling clock generating unit comprise the first inverter, the second delayer, the second inverter and the 3rd with door, described the first inverter is controlled the 3rd switch and the 5th switch through the second delayer, described the second delayer is through the second inverter controlling the 4th switch and the 6th switch, and described the first inverter and the second delayer close with the gate control minion through the 3rd.

4. a kind of ratio timing sampling circuit according to claim 1, it is characterized in that: described the second sampling clock generating unit comprise the 3rd delayer, the 4th with the door and the 3rd inverter, described the 3rd delayer through the 4th with the gate control second switch, the 4th with Men Jingdi three inverter controlling the first switch.

5. a kind of ratio timing sampling circuit according to claim 1, it is characterized in that: described delay unit comprises the second bias current sources, delay capacitor, Schmidt trigger and the 4th inverter, input control the 9th switch and the tenth switch of described delay unit, internal power supply is connected to the top crown of delay capacitor through the 9th switch, the top crown of delay capacitor is connected to ground through the tenth switch and the second bias current sources, be connected to the output of described delay unit through Schmidt trigger and the 4th inverter, the bottom crown of the second delay capacitor is connected to ground.

6. a kind of ratio timing sampling circuit according to claim 1, it is characterized in that: described ratio timing sampling circuit is integrated in the integrated package.

7. an application rights requires the Switching Power Supply of 1 described ratio timing sampling circuit, comprise transformer and control circuit, it is characterized in that: described control circuit links to each other with the feedback winding element of transformer, regulate pulse duration and the frequency of described transformer to produce a switching signal, described control circuit comprises ratio timing sampling circuit and PWM/PFM modulator.

8. the Switching Power Supply of application percentage timing sampling circuit according to claim 7, it is characterized in that: described ratio timing sampling circuit and PWM/PFM modulator are integrated in the integrated package.