CN202652181U

CN202652181U - I2C intelligent output circuit

Info

Publication number: CN202652181U
Application number: CN 201220233416
Authority: CN
Inventors: 陈�峰
Original assignee: CHANGZHOU XINQI MICROELECTRONICS TECHNOLOGY Co Ltd
Current assignee: CHANGZHOU XINQI MICROELECTRONICS TECHNOLOGY Co Ltd
Priority date: 2012-05-23
Filing date: 2012-05-23
Publication date: 2013-01-02
Anticipated expiration: 2022-05-23

Abstract

The utility model discloses an I2C intelligent output circuit comprising a starting circuit, a delay circuit, a slope control circuit, a voltage generator circuit, a current generator circuit and a direct-current power supply, wherein the delay circuit is electrically connected with the direct-current power supply; the starting circuit, the voltage generator circuit and the current generator circuit are electrically connected with the delay circuit respectively; and the slope control circuit is electrically connected with the current generator circuit. By means of the above mode, the I2C intelligent output circuit has the advantages of being able to output stably, reducing the power consumption, prolonging the service life, and reducing the production cost.

Description

I 2C intelligence output circuit

Technical field

The utility model relates to electronic circuit field, particularly relates to a kind of I ²C intelligence output circuit.

Background technology

I ²The C bus is the many principal and subordinates' of serial bus protocol, is widely used in than the communication of low speed and basic configuration and the control of complication system.Based on the requirement of EMI and sequential, I ²The C standard is stipulated the signal slope of output-stage circuit: in the bus capacitance loading range of 10pF to 400pF, the slope of output signal should 20+0.1Cb ~ 250ns(wherein Cb be load capacitance).This is a stricter regulation, in traditional application process, generally adopts the outside upper mode that skews rate control of drop-down slope control+sheet in the sheet.

I ²The C bus since cost low and use simple and in electronic equipment extensive equipment.Because I ²The C bus adopts Transistor-Transistor Logic level, and driving force and poor anti jamming capability, transmission range are very limited, therefore is mainly used in the usefulness of electronic equipment internal communication, and is not suitable for the communication between the electronic equipment.Yet increasing transducer has adopted I in recent years ²C bus and electronic equipment carry out communication between devices.In order to prolong I ²The C communication distance, some semiconductor companies have designed special I ²C drives chip and solves this problem.

The utility model content

The technical problem that the utility model mainly solves provides a kind of I ²C intelligence output circuit can be stablized output, reduces power consumption, increase the service life, reduces cost of manufacture.

For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of I is provided ²C intelligence output circuit, comprise: start-up circuit, delay circuit, slope control circuit, voltage generation circuit, current generating circuit and DC power supply, described delay circuit and DC power supply are electrically connected, described start-up circuit, voltage generation circuit, current generating circuit are respectively at being electrically connected with delay circuit, and described slope control circuit and current generating circuit are electrically connected.

In preferred embodiment of the utility model, described slope control circuit also is connected with common.

In preferred embodiment of the utility model, described slope control circuit comprises drop-down slope control device and rate of rise control device.

In preferred embodiment of the utility model, described start-up circuit comprises two PMOS pipes and an electric capacity at least.

In preferred embodiment of the utility model, described delay circuit comprises NMOS pipe and PMOS pipe.

The beneficial effects of the utility model are: the utility model I ²C intelligence output circuit can be stablized output, reduces power consumption, increase the service life, reduces cost of manufacture.

Description of drawings

Fig. 1 is the utility model I ²The structural representation of C intelligence output circuit one preferred embodiment;

The mark of each parts is as follows in the accompanying drawing: 1, start-up circuit, 2, delay circuit, 3, slope control circuit, 4, voltage generation circuit, 5, current generating circuit, 6, DC power supply, 7, common.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present utility model is described in detail, thereby so that advantage of the present utility model and feature can be easier to be it will be appreciated by those skilled in the art that protection range of the present utility model is made more explicit defining.

See also Fig. 1, a kind of I ²C intelligence output circuit, comprise: start-up circuit 1, delay circuit 2, slope control circuit 3, voltage generation circuit 4, current generating circuit 5 and DC power supply 6, described delay circuit 2 is electrically connected with DC power supply 6, described start-up circuit 1, voltage generation circuit 4, current generating circuit 5 are respectively at being electrically connected with delay circuit 2, and described slope control circuit 3 is electrically connected with current generating circuit 5.

In addition, described slope control circuit 3 also is connected with common 7.

In addition, described slope control circuit 3 comprises drop-down slope control device and rate of rise control device, and slope control circuit 3 is controlled I by integrated drop-down slope control device and rate of rise control device ²The output voltage gradient of C output device has reduced system cost and PCB complexity, has reduced power consumption.

In addition, described start-up circuit 1 comprises two PMOS pipes and an electric capacity at least.

In addition, described delay circuit 2 comprises NMOS pipe and PMOS pipe, delay circuit 2 by transmission as delay cell, carry out slope control by conducting quantity and the degree of control efferent duct, utilize floating trap technology to realize and bus on effective isolation of data.

Be different from prior art, the utility model I2C intelligence output circuit can be stablized output, reduces power consumption, increase the service life, reduces cost of manufacture.

The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model specification and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.

Claims

1. I ²C intelligence output circuit, it is characterized in that, comprise: start-up circuit, delay circuit, slope control circuit, voltage generation circuit, current generating circuit and DC power supply, described delay circuit and DC power supply are electrically connected, described start-up circuit, voltage generation circuit, current generating circuit are respectively at being electrically connected with delay circuit, and described slope control circuit and current generating circuit are electrically connected.

2. I according to claim 1 ²C intelligence output circuit is characterized in that described slope control circuit also is connected with common.

3. I according to claim 1 ²C intelligence output circuit is characterized in that described slope control circuit comprises drop-down slope control device and rate of rise control device.

4. I according to claim 1 ²C intelligence output circuit is characterized in that described start-up circuit comprises two PMOS pipes and an electric capacity at least.

5. I according to claim 1 ²C intelligence output circuit is characterized in that, described delay circuit comprises NMOS pipe and PMOS pipe.