CN202651091U - 三维线路芯片正装有基岛无源器件封装结构 - Google Patents

三维线路芯片正装有基岛无源器件封装结构 Download PDF

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CN202651091U
CN202651091U CN2012202717142U CN201220271714U CN202651091U CN 202651091 U CN202651091 U CN 202651091U CN 2012202717142 U CN2012202717142 U CN 2012202717142U CN 201220271714 U CN201220271714 U CN 201220271714U CN 202651091 U CN202651091 U CN 202651091U
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chip
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packaging structure
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王新潮
梁志忠
李维平
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及一种三维线路芯片正装有基岛无源器件封装结构，所述结构包括基岛（1）和引脚（2），所述基岛和引脚均由多层金属线路层构成，所述基岛正面设置有芯片（4），所述芯片正面与引脚正面之间用金属线（5）相连接，所述基岛和引脚周围区域以及芯片和金属线外均包封有塑封料（6），所述引脚下部的塑封料表面上开设有小孔（7），所述小孔与引脚背面相连通，所述小孔内设置有金属球（9），所述金属球与引脚背面相接触，所述引脚与引脚之间跨接无源器件（10）。本实用新型的有益效果是：降低了制造成本，提高了封装体的安全性和可靠性，减少了环境污染，能够真正做到高密度线路的设计和制造。

Description

三维线路芯片正装有基岛无源器件封装结构
技术领域
本实用新型涉及一种三维线路芯片正装有基岛无源器件封装结构。属于半导体封装技术领域。
背景技术
传统的高密度基板封装结构的制造工艺流程如下所示：
步骤一、参见图7，取一玻璃纤维材料制成的基板，
步骤二、参见图8，在玻璃纤维基板上所需的位置上开孔，
步骤三、参见图9，在玻璃纤维基板的背面披覆一层铜箔，
步骤四、参见图10，在玻璃纤维基板打孔的位置填入导电物质，
步骤五、参见图11，在玻璃纤维基板的正面披覆一层铜箔，
步骤六、参见图12，在玻璃纤维基板表面披覆光阻膜，
步骤七、参见图13，将光阻膜在需要的位置进行曝光显影开窗，
步骤八、参见图14，将完成开窗的部分进行蚀刻，
步骤九、参见图15，将基板表面的光阻膜剥除，
步骤十、参见图16，在铜箔线路层的表面进行防焊漆（俗称绿漆）的披覆，
步骤十一、参见图17，在防焊漆需要进行后工序的装片以及打线键合的区域进行开窗，
步骤十二、参见图18，在步骤十一进行开窗的区域进行电镀，相对形成基岛和引脚，
步骤十三、完成后续的装片、打线、包封、切割等相关工序。
上述传统高密度基板封装结构存在以下不足和缺陷：
1、多了一层的玻璃纤维材料，同样的也多了一层玻璃纤维的成本；
2、因为必须要用到玻璃纤维，所以就多了一层玻璃纤维厚度约100~150μm的厚度空间；
3、玻璃纤维本身就是一种发泡物质，所以容易因为放置的时间与环境吸入水分以及湿气，直接影响到可靠性的安全能力或是可靠性等级；
4、玻璃纤维表面被覆了一层约50~100μm的铜箔金属层厚度，而金属层线路与线路的蚀刻距离也因为蚀刻因子的特性只能做到50~100μm的蚀刻间隙（蝕刻因子: 最好製做的能力是蚀刻间隙约等同于被蚀刻物体的厚度，参见图19），所以无法真正的做到高密度线路的设计与制造；
5、因为必须要使用到铜箔金属层，而铜箔金属层是采用高压粘贴的方式，所以铜箔的厚度很难低于50μm的厚度，否则就很难操作如不平整或是铜箔破损或是铜箔延展移位等等；
6、也因为整个基板材料是采用玻璃纤维材料，所以明显的增加了玻璃纤维层的厚度100~150μm，无法真正的做到超薄的封装；
7、传统玻璃纤维加贴铜箔的工艺技术因为材质特性差异很大（膨胀系数），在恶劣环境的工序中容易造成应力变形，直接的影响到元件装载的精度以及元件与基板粘着性与可靠性。
发明内容
本实用新型的目的在于克服上述不足，提供一种三维线路芯片正装有基岛无源器件封装结构，其工艺简单，不需使用玻璃纤维层，减少了制作成本，提高了封装体的安全性和可靠性，减少了玻璃纤维材料带来的环境污染，而且金属基板线路层采用的是电镀方法，能够真正做到高密度线路的设计和制造。
本实用新型的目的是这样实现的：一种三维线路芯片正装有基岛无源器件封装结构，它包括基岛和引脚，所述基岛和引脚均由多层金属线路层构成，所述基岛正面通过导电或不导电粘结物质设置有芯片，所述芯片正面与引脚正面之间用金属线相连接，所述基岛外围的区域、基岛和引脚之间的区域、引脚与引脚之间的区域、基岛和引脚上部的区域、基岛和引脚下部的区域以及芯片和金属线外均包封有塑封料，所述引脚背面开设有小孔，所述小孔与引脚背面相连通，所述小孔内设置有金属球，所述金属球与引脚背面相接触, 所述引脚与引脚之间跨接有无源器件。
具体地，所述无源器件跨接于引脚正面与引脚正面之间。
具体地，所述无源器件还可以跨接于引脚中间的金属线路层与引脚中间的金属线路层之间。
具体地，所述无源器件还可以跨接于引脚背面与引脚背面之间。
在所述引脚背面与金属球之间还设置有金属保护层。
与现有技术相比，本实用新型具有以下有益效果：
1、本实用新型不需要使用玻璃纤维层，所以可以减少玻璃纤维层所带来的成本；
2、本实用新型没有使用玻璃纤维层的发泡物质，所以可靠性的等级可以再提高，相对对封装体的安全性就会提高；
3、本实用新型不需要使用玻璃纤维层物质，所以就可以减少玻璃纤维材料所带来的环境污染；
4、本实用新型的三维金属基板线路层所采用的是电镀方法，而电镀层每一层的总厚度约在10~15μm，而线路与线路之间的间隙可以轻松的达到25μm以下的间隙，所以可以真正地做到高密度內引腳線路平铺的技术能力；
5、本实用新型的三维金属基板因采用的是金属层电镀法，所以比玻璃纤维高压铜箔金属层的工艺来得简单，且不会有金属层因为高压产生金属层不平整、金属层破损以及金属层延展移位的不良或困惑；
6、本实用新型的三维金属基板线路层是在金属基材的表面进行金属电镀，所以材质特性基本相同，所以镀层线路与金属基材的内应力基本相同，可以轻松的进行恶劣环境的后工程（如高温共晶装片、高温锡材焊料装片以及高温被动元件的表面贴装工作）而不容易产生应力变形。
附图说明
图1为本实用新型三维线路芯片正装有基岛无源器件封装结构实施例1的结构示意图。
图2为图1的立体图。
图3为本实用新型三维线路芯片正装有基岛无源器件封装结构实施例2的结构示意图。
图4为图3的立体图。
图5为本实用新型三维线路芯片正装有基岛无源器件封装结构实施例3的结构示意图。
图6为图5的立体图。
图7~图18为传统的高密度基板封装结构的制造工艺流程图。
图19为玻璃纤维表面铜箔金属层的蚀刻状况示意图。
其中： 
基岛1
引脚2
导电或不导电粘结物质3
芯片4
金属线5
塑封料6
小孔7
金属保护层8
金属球9
 无源器件10。
具体实施方式
实施例1、无源器件安装于引脚正面
参见图1和图2，本实用新型三维线路芯片正装有基岛无源器件封装结构，它包括基岛1和引脚2，所述基岛1和引脚2均由多层金属线路层构成，所述基岛1正面通过导电或不导电粘结物质3设置有芯片4，所述芯片4正面与引脚2正面之间用金属线5相连接，所述基岛1外围的区域、基岛1和引脚2之间的区域、引脚2与引脚2之间的区域、基岛1和引脚2上部的区域、基岛1和引脚2下部的区域以及芯片4和金属线5外均包封有塑封料6，所述引脚2背面开设有小孔7，所述小孔7与引脚2背面相连通，所述小孔7内设置有金属球9，所述金属球9与引脚2背面之间设置有金属保护层8，所述金属球9采用锡或锡合金材料，所述引脚2与引脚2之间通过导电粘结物质跨接无源器件10，所述无源器件10跨接于引脚2正面与引脚2正面之间。
实施例2、无源器件安装于引脚的金属线路层之间
参见图3和图4，实施例2与实施例1的区别在于所述无源器件10跨接于引脚2中间的金属线路层和引脚2中间的金属线路层之间。
实施例3、无源器件安装于引脚的背面
参见图5和图6，实施例3与实施例1的区别在于所述无源器件10跨接于引脚2的背面与引脚2的背面之间。

Claims (5)

1.一种三维线路芯片正装有基岛无源器件封装结构，其特征在于它包括基岛（1）和引脚（2），所述基岛（1）和引脚（2）均由多层金属线路层构成，所述基岛（1）正面通过导电或不导电粘结物质（3）设置有芯片（4），所述芯片（4）正面与引脚（2）正面之间用金属线（5）相连接，所述基岛（1）外围的区域、基岛（1）和引脚（2）之间的区域、引脚（2）与引脚（2）之间的区域、基岛（1）和引脚（2）上部的区域、基岛（1）和引脚（2）下部的区域以及芯片（4）和金属线（5）外均包封有塑封料（6），所述引脚（2）背面开设有小孔（7），所述小孔（7）与引脚（2）背面相连通，所述小孔（7）内设置有金属球（9），所述金属球（9）与引脚（2）背面相接触，所述引脚（2）与引脚（2）之间跨接无源器件（10）。
2.根据权利要求1所述的一种三维线路芯片正装有基岛无源器件封装结构，其特征在于在所述引脚（2）背面与金属球（9）之间还设置有金属保护层（8）。
3.根据权利要求1或2所述的一种三维线路芯片正装有基岛无源器件封装结构，其特征在于所述无源器件（10）跨接于所述引脚（2）的正面与引脚（2）的正面之间。
4.根据权利要求1或2所述的一种三维线路芯片正装有基岛无源器件封装结构，其特征在于所述无源器件（10）跨接于所述引脚（2）中间的金属线路层与引脚（2）中间的金属线路层之间。
5.根据权利要求1或2所述的一种三维线路芯片正装有基岛无源器件封装结构，其特征在于所述无源器件（10）跨接于所述引脚（2）的背面与引脚（2）的背面之间。
CN2012202717142U 2012-06-09 2012-06-09 三维线路芯片正装有基岛无源器件封装结构 Expired - Lifetime CN202651091U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015018173A1 (en) * 2013-08-06 2015-02-12 Jiangsu Changjiang Electronics Technology Co., Ltd First-packaged and later-etched normal chip three dimension system-in-package metal circuit board structure and processing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015018173A1 (en) * 2013-08-06 2015-02-12 Jiangsu Changjiang Electronics Technology Co., Ltd First-packaged and later-etched normal chip three dimension system-in-package metal circuit board structure and processing method thereof

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