CN202650533U

CN202650533U - An audio reproducing system based on a CPU or a FPGA/CPLD

Info

Publication number: CN202650533U
Application number: CN 201220264227
Authority: CN
Inventors: 林建政
Original assignee: NANJING SOUNDFEEL CO Ltd
Current assignee: NANJING SOUNDFEEL CO Ltd
Priority date: 2012-06-06
Filing date: 2012-06-06
Publication date: 2013-01-02
Anticipated expiration: 2022-06-06

Abstract

The utility model provides an audio reproducing system based on a CPU or a FPGA/CPLD. The audio reproducing system comprises a CPU and a FPGA/CPLD which are supplied with power by an independent power supply, respectively. Data interaction between the CPU and the FPGA/CPLD are performed via high-speed asynchronous bus of the CPU. The CPU comprises a USB, a SATA, a network card, a SD memory card, and a decompression processing unit while the FPGA/CPLD comprises an audio synthesis unit. The audio reproducing system based on a CPU or a FPGA/CPLD satisfies all essential conditions of the high-quality digital audio reproducing system and guarantees high audio reproducing quality.

Description

Audio playback systems based on CPU and FPGA/CPLD

Technical field

The utility model relates to the audio signal processing technique field, particularly a kind of audio playback systems based on CPU and FPGA/CPLD.

Background technology

At present, along with high code check digital music is more and more universal, realized the purchase function of high code check digital music abroad, in the urgent need to a kind of digital playback device that can realize to high code check music file high-fidelity.Simultaneously along with some defectives of CD music (CD preservation problem for example itself, there is the higher problem of cost etc. in good medium), also can substitute CD and when guaranteeing to reach the CD replaying effect and overcome the device of the defective that CD resets own in the urgent need to a kind of.

CPLD (Complex Programmable Logic Device, CPLD), it is the device that develops out from PAL and GAL device, scale is large comparatively speaking, complex structure, belonging to the large scale integrated circuit scope, is a kind of user according to needs separately and the digital integrated circuit of constitutive logic function voluntarily.Its basic design method is by the Integrated Development software platform, with methods such as schematic diagram, hardware description languages, generates corresponding file destination, by download cable (" in system " programming) code is sent in the objective chip, realizes the digital display circuit of design.Field programmable gate array (Field-Programmable Gate Array, FPGA), it is the product that further develops on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.At present, at home the processing of high code check sound signal is mainly contained following three kinds of methods: 1. based on the mode of pure operating system CPU, mainboard or cpu chip are with the i2s audio output interface; 2. music is carved into CD or DVD audio form, resets at traditional C D or DVD; 3. based on single-chip microcomputer, or the support of the high code check file of simple WAV of FPGA/CPLD.More than three kinds of methods, reach the effect of real high-fidelity, open defect is all arranged, and imperfect.

As everyone knows, high code check music file mainly is the forms such as WAV, FLAC, APE, from 32khz-384khz, do not wait from 16bit-32bit, in the situation of 32bit, 384khz, per second is up to the data speed of 24Mbps, and the nearly real-time decompress(ion) ability of the needs such as FLAC, APE, and processing power is had higher requirement.

As high-quality data audio decoding system, the audio interface from data to last i2s, middle without any redundancy and error correction design, sound not only requires data correctness, more requires the accuracy of presentation of data time, real-time.So the quality of i2s affects the performance that rear end DAC and simulation are amplified greatly.Such as, the FLAC music file at first needs nearly real-time decompress(ion), will deliver to synthesis chip behind the decompress(ion) and carry out the synthetic of i2s, and finally export the i2s agreement that DAC can receive.Yet judge the quality of i2s, the most basic is exactly the bit error rate and clock accuracy, is exactly the position that at a time should occur, and mistake do not occur or occur at last; Next is phase noise, and poor phase noise directly embodies in i2s, not only may may cause erroneous judgement to the DAC receive data, the more important thing is analog amplify circuit is formed larger interference.Also have a bit, it also is HIFI-END audio system the important point, be exactly time-delay and phase place, in a Play System, it is very important that major clock shares, synthetic major clock with DAC such as i2s need to be identical, and music playback system need to be supported the music file (such as 44.1k, 48k etc.) of different sampling rates, and this just has higher requirement to the phase delay of major clock precision and i2s and major clock.Give an example, the music of 32bit, 384khz, the i2s bit clock is 22.576MHZ, if the time-delay of an audio frequency synthesis chip be can not determine, such as tens nanoseconds, at i2s and major clock in totally four lines, it is large different and cause situation about misplacing to make each other time-delay, and high-fidelity is not just known where to begin yet like this.At last, common CPU(such as ARM) precision of integrated phase locked looped function and the demand that does not also far reach high-fidelity of phase noise.

Based on this, method 1 in the prior art is not because be specially for hi-fi reproduction designs substantially, and phaselocked loop, clock, phase noise far do not reach the requirement of high-fidelity, generally at-70-90db, based on the audio frequency synthesis mode of interrupt mode, be difficult to the i2s output that reaches high-quality, stable simultaneously; Music file is carved into CD, DVD in the method 2, and the imprinting process just causes damage to music, and particularly the individual can't have in the situation of RW system of very high quality, worse off.Adopt pure single-chip microcomputer or FPGA/CPLD in the method 3, limited in one's ability because of interface and complex process, substantially can only support the music file of comparison single type, interface is also very limited simultaneously, simultaneously the also defective as CPU of single-chip microcomputer.

The utility model content

Above problem based on prior art exists the utility model proposes a kind of audio playback systems based on CPU and FPGA/CPLD, has satisfied all essential conditions of high-quality digital music playback system, has guaranteed the high-quality of audio playback.The technical scheme that the utility model adopts specifically is achieved in that

The utility model provides a kind of audio playback systems based on CPU and FPGA/CPLD, and it comprises CPU and the FPGA/CPLD that is powered respectively by independent current source, and the high-speed asynchronous bus by described CPU between described CPU and the FPGA/CPLD is finished data interaction.

Preferably, described CPU comprises USB, SATA, network interface card, SD card and decompress(ion) processing unit, comprises the audio frequency synthesis unit among the described FPGA/CPLD.

Preferably, described decompression processing unit is that FLAC, decompress(ion) are that PCM unit, APE decompress(ion) are the PCM unit.

Preferably, also comprise digital to analog converter, itself and FPGA/CPLD share a cover major clock.

Preferably, the clock of described FPGA/CPLD has adopted low doubleclocking of making an uproar mutually.

Preferably, described FPGA provides FIFO to carry out buffer memory.

Audio playback systems based on CPU and FPGA/CPLD of the present utility model has satisfied all essential conditions of high-quality digital music playback system, has guaranteed the high-quality of audio playback.

Description of drawings

Fig. 1 is the structural representation based on the audio playback systems of CPU and FPGA/CPLD of the utility model embodiment.

Embodiment

For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing embodiment of the present utility model is described in detail, it will be more clear making above-mentioned and other purpose of the present utility model, Characteristics and advantages.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw in proportion accompanying drawing, focus on illustrating purport of the present utility model.

The title abbreviation that relates in the utility model specific embodiment is described below:

CPU: central processing unit, the abbreviation of English Central Processing Unit;

USB: USB (universal serial bus), the abbreviation of English Universal Serial BUS;

SATA: Serial Advanced Technology Attachment, the abbreviation of English Serial Advanced Technology Attachment;

SD card: safe digital card, the abbreviation of English Secure Digital Memory Card;

FIFO: First Input First Output, the abbreviation of English First Input First Output;

DMA: direct memory access, the abbreviation of English Direct Memory Access.

Be elaborated below in conjunction with the specific embodiment of accompanying drawing to the audio playback systems based on CPU and FPGA/CPLD of the present utility model.

Fig. 1 is the structural representation based on the audio playback systems of CPU and FPGA/CPLD of the utility model embodiment, the audio playback systems of CPU of the present utility model and FPGA/CPLD, it comprises CPU 10 and the FPGA/CPLD 20 that is powered respectively by independent

current source

30 and 40, high-speed asynchronous bus 11 by CPU 10 between CPU 10 and the FPGA/CPLD 20 is finished data interaction, CPU 10 comprises USB 12, SATA 13, network interface card 14, SD card 15 and decompress(ion) processing unit 16, comprises the audio frequency synthesis unit among the described FPGA/CPLD 20.Power supply 30 provides power supply for CPU 10, and power supply 40 provides power supply for FPGA/CPLD 20, and high-speed asynchronous bus 11 connects CPU 10 and FPGA/CPLD 20 and finishes therebetween data interaction, and decompress(ion) and the processing of audio frequency finished in decompression processing unit 16.

In the audio playback systems based on CPU and FPGA/CPLD of the utility model embodiment, for example, decompression processing unit 16 can be PCM with the FLAC decompress(ion), can be PCM with the APE decompress(ion).

In the audio playback systems based on CPU and FPGA/CPLD of the utility model embodiment, preferably, also comprise digital to analog converter, itself and FPGA/CPLD 20 share a cover major clock.

In the present embodiment, the clock of FPGA/CPLD 20 has adopted low doubleclocking of making an uproar mutually, and its frequency is respectively 22.5792MHZ and 24.576MHZ, is the direct frequency multiplication major clock of the music file of 44.1khz and 48khz frequency multiplication; Preferably, FPGA provides FIFO to carry out buffer memory.

In the audio playback systems based on CPU and FPGA/CPLD of the utility model embodiment, CPU is responsible for the man-machine interface that provides good, the bad border of pattern development of providing convenience, provide abundant peripheral hardware USB, SATA, network interface card to be used for interconnection network, SD card etc., because the powerful processing power of CPU, it also is responsible for the decompression processing of audio file, and the good interface that it is born and complex instruction set possess the audio format file of any complexity of decompress(ion) fully.FPGA/CPLD 20 is responsible for the synthetic of audio frequency, and in the situation of power supply, it can guarantee to hang down and make an uproar mutually separately, can guarantee synthetic precision and stability.In the utility model specific embodiment, the data interaction of CPU 10 and FPGA is to finish by the high-speed asynchronous bus 11 of CPU 10, CPU 10 FPGA/CPLD 20 all have the high-speed asynchronous bus interface that coupling connects, adopt in the utility model that the system to CPU has carried out real-time optimization in self the scheme, reached the response time of us level, higher real-time and the processing power of per second hundreds of MB are provided simultaneously; FPGA/CPLD 20 and CPU 10 power separately, and isolation, and digital to analog converter DAC and FPGA/CPLD 20 shared cover major clocks, and preferably phase noise and clock consistance are provided like this; The clock of FPGA/CPLD20 has adopted low doubleclocking 22.5792MHZ and the 24.576MHZ that makes an uproar mutually, be the direct frequency multiplication major clock of the music file of 44.1khz and 48khz frequency multiplication, need not the phase locked looped function of FPGA, further optimized the precision of phase noise and clock; FPGA provides FIFO to carry out buffer memory, and adopt the kernel interruption tupe of ultralow time-delay and the data transmission that dma mode carries out high speed, low consumption, low delay, thereby accomplish high stability, high-speed, high real-time (us level), guaranteed that data are without the requirement of cutout without error code.

FPGA/CPLD has nanosecond other time-delay ability of (ns) level, in the middle of the FPGA or CPLD that fully optimize, time-delay can be low to moderate below the 5ns, satisfies the demand that any audio frequency is processed fully, FPGA/CPLD has highly stable, fixing processing power simultaneously, shake is low to moderate psec (ps) level, and it is synthetic to be fit to very much big data quantity and high quality audio agreement, in addition, cooperation is to FPGA/CPLD electric power system independently, can reach low fully and make an uproar mutually low jitter, the audio synthesis system of low delay.

Audio playback systems based on CPU and FPGA/CPLD of the present utility model is used for playback or the broadcast of DAB mostly, has satisfied all essential conditions of high-quality digital music playback system, has guaranteed the high-quality of audio playback.

In above description, a lot of details have been set forth so that fully understand the utility model.But above description only is preferred embodiment of the present utility model, and the utility model can be implemented much to be different from alternate manner described here, so the utility model is not subjected to the restriction of top disclosed implementation.Any skilled personnel are not breaking away from the technical solutions of the utility model scope situation simultaneously, all can utilize method and the technology contents of above-mentioned announcement that technical solutions of the utility model are made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Every content that does not break away from technical solutions of the utility model according to any simple modification, equivalent variations and the modification that technical spirit of the present utility model is done above embodiment, all still belongs in the scope of technical solutions of the utility model protection.

Claims

1. the audio playback systems based on CPU and FPGA/CPLD is characterized in that, comprises the CPU and the FPGA/CPLD that are powered respectively by independent current source, and the high-speed asynchronous bus by described CPU between described CPU and the FPGA/CPLD is finished data interaction.

2. the audio playback systems based on CPU and FPGA/CPLD as claimed in claim 1 is characterized in that, described CPU comprises USB, SATA, network interface card, SD card and decompress(ion) processing unit, comprises the audio frequency synthesis unit among the described FPGA/CPLD.

3. the audio playback systems based on CPU and FPGA/CPLD as claimed in claim 1 is characterized in that, described decompression processing unit is that FLAC, decompress(ion) are that PCM unit, APE decompress(ion) are the PCM unit.

4. the audio playback systems based on CPU and FPGA/CPLD as claimed in claim 1 is characterized in that, also comprises digital to analog converter, and itself and FPGA/CPLD share a cover major clock.

5. the audio playback systems based on CPU and FPGA/CPLD as claimed in claim 1 is characterized in that, the clock of described FPGA/CPLD has adopted low doubleclocking of making an uproar mutually.

6. the audio playback systems based on CPU and FPGA/CPLD as claimed in claim 1 is characterized in that, described FPGA provides FIFO to carry out buffer memory.