CN202549308U - Double-bit-line sub-threshold storage unit circuit - Google Patents

Abstract

The utility model provides a double-bit-line sub-threshold storage unit circuit. The circuit adopts double-end read-write operation and comprises a first phase inverter and a second phase inverter, wherein the two phase inverters are connected to form a cross coupling; the circuit adopts a double-bit-line structure with read-write bit lines separated; two storage nodes of the cross coupling are respectively connected to two write bit lines by an NMOS (N-mental-oxide-semiconductor) transistor; and meanwhile, the two storage nodes of the cross coupling are connected to two read bit lines by an NMOS transistor and a PMOS (P-mental-oxide-semiconductor) transistor. The circuit has the following advantages and obvious effects that the circuit adopts the PMOS substrate regulation technology, namely, all the substrate ends of the PMOS are connected to the gate ends, thus being capable of ensuring the system to realize simultaneous reduction of dynamic operation energy consumption and leakage power in static operation on the premise of not increasing the extra management power and not reducing the performances, improving the static noise margin of the storage unit and optimizing the system performances.

Description

A kind of double dight wire sub-threshold storing unit circuit

Technical field

The utility model relates in the subthreshold value design, the low-power consumption storage unit under the subthreshold value perform region, and especially a kind of double dight wire sub-threshold storing unit circuit belongs to the IC design technical field.

Background technology

SRAM (SRAM) is the important component part of Modern Digital System, has often occupied the most area of System on Chip/SoC, also the power consumption bottleneck of system design often.Along with market to the improving constantly of various portable set demands, the reduction power consumption technology of memory cell array is had higher requirement.The subthreshold value design is the hot topic of current super low-power consumption design.Get into the subthreshold value zone of circuit through reducing supply voltage VDD: supply voltage VDD is less than threshold voltage vt h, makes system works at the linear zone of circuit, so significantly reduce system dynamically, quiescent dissipation.The design of sub-threshold memory cell array has highlighted the low-power consumption superiority of subthreshold value design especially.

SRAM is the important component part of Design of Digital Circuit, and its crash rate will directly influence the yield of system.Along with further dwindling of technology characteristics size, the long L of grid, grid width W, oxidated layer thickness T _OXAnd process fluctuation such as dopant profiles more can not be ignored the influence that device brings.Wherein mixing at random, (it can have a strong impact on the transistorized threshold voltage of little physical dimension (Vth), particularly sram cell, causes the rapid rising of crash rate for Random Dopant Fluctuation, having the greatest impact RDF) in fluctuation.In typical superthreshold six transistor memory unit unit design, the deviser can through the balance pull-down transistor, pull up transistor and access transistor between the drive ratio relation, when satisfying the yield demand, reach the density requirements of memory cell.But transistor drive current and threshold voltage exponent function relation in subthreshold value zone, device technology deviation also become to the influence of storage unit yield and have more challenge, only depend on simple trim size can not satisfy design demand.Memory cell structure is designed to coordinate each crash rate for subthreshold value memory circuit balance read-write operation, satisfies the key that the design yield requires.Along with the raising of semiconductor devices integrated level, constantly dwindling of characteristic dimension must cause the increase of static leakage current.The operating characteristic that it should be noted that storage array has simultaneously determined its part unit will be in idle state (Standby Operation) for a long time.The composition number of transistors of considering storage array is numerous, corresponding serviceable life and the reliability that increases sharply and then reduce product of the static energy consumption of storage array.Therefore; How to pass through dynamic energy consumption and the static leakage current that circuit design reduces storage unit in the storage array; Guarantee design performance simultaneously, that is on the basis that guarantees certain working current, reduce cell leakage current, become one of research direction of storage array design.

Summary of the invention

The problem that the utility model will solve is: because sub-threshold memory cell has adopted lower supply voltage to obtain super low energy consumption; Its influence that receives process, process deviation is more serious; Need to solve the noise margin problem of smaller of storage unit, on the basis that guarantees certain working current, reduce cell leakage current.

For solving the problems of the technologies described above, the utility model is taked following technical scheme:

A kind of double dight wire sub-threshold storing unit circuit is characterized in that, comprises four PMOS pipe P1～P4 and six NMOS pipe N1～N6, constitutes the sub-threshold storing unit circuit of both-end read-write, has a pair of write bit line and a pair of sense bit line, wherein:

The substrate of four PMOS pipe P1～P4 is connected with separately grid end respectively, and six NMOS manage the equal ground connection GND of substrate of N1～N6; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end that PMOS manages P1 respectively, constitute first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end that PMOS manages P2 respectively, constitute second phase inverter; First phase inverter and second phase inverter connect into cross-couplings: the grid end of NMOS pipe N1 grid end, PMOS pipe P1 and the drain terminal of NMOS pipe N2 and the drain terminal of PMOS pipe P2 link together; The drain terminal of the drain terminal of the grid end of the grid end of NMOS pipe N2, PMOS pipe P2 and NMOS pipe N1 and PMOS pipe P1 links together, and the source end of PMOS pipe P1, P2 all is connected with supply voltage VDD; The drain terminal of the drain terminal of the grid end of the source end of NMOS pipe N3, NMOS pipe N5 and PMOS pipe P1 and NMOS pipe N1 links together, and the grid end of NMOS pipe N3 connects write word line WWL, and the drain terminal of NMOS pipe N3 connects write bit line WBL; The drain terminal of NMOS pipe N5 connects the drain terminal of PMOS pipe P3; The grid end of PMOS pipe P3 connects readout word line RWL, and the source end of PMOS pipe P3 connects sense bit line RBL, and the drain terminal of the grid end of the source end of NMOS pipe N4, NMOS pipe N6 and the drain terminal of PMOS pipe P2 and NMOS pipe N2 links together; The grid end of NMOS pipe N4 connects write word line WWL; The drain terminal of NMOS pipe N4 connects another root write bit line WBLB, and the drain terminal of NMOS pipe N6 connects the drain terminal of PMOS pipe P4, and the grid end of PMOS pipe P4 connects readout word line RWL; The source end of PMOS pipe P3 connects another root sense bit line RBLB, the equal ground connection GND of source end of NMOS pipe N1, N2, N5, N6.

Compared with prior art, the utlity model has following advantage and remarkable result:

(1) storage unit of the utility model design adopts the double dight wire structure; Be that write bit line separates with sense bit line; So just significantly reduced to be connected on the transistorized quantity on write bit line and the sense bit line; Thereby significantly reduced the electric capacity on write bit line and the sense bit line, and then improved the speed of discharging and recharging, reduced dynamic energy consumption;

(2) sub-threshold memory cell of the super low energy consumption of the utility model design, high robust is under the situation that does not influence time for reading; Owing to adopted the coupling pipe (P3, P4) of the PMOS pipe of body terminal voltage dynamic adjustments as read operation; Make the bit line amplitude of oscillation be controlled in the 0.5VDD, thereby reduced the dynamic energy consumption of bit line; And, when static state operation, adopt the bit line leakage current of unit of the present invention less, thereby reduced the leakage power consumption;

(3) storage unit of the utility model design owing to adopted PMOS body end dynamic electric voltage regulation technology, has reduced the static leakage current of unit, thereby has reduced the leakage power consumption of storage array;

(4) in the sub-threshold memory cell of the utility model design; NMOS pipe N5, N6 combine PMOS pipe P3, P4 to form and read buffer circuit; This buffer circuit makes memory node and bitline separation in the read operation process; The current potential of preliminary filling can not cause the rising of memory node current potential on the bit line; Therefore the most critical of subthreshold value SRAM design problem---the read noise tolerance limit is expanded, the diverse read schemes that just adopts in the utility model has improved the anti-noise ability that reads storage unit in the process, has strengthened the robustness of SRAM; And, further improved the static noise margin of unit again because the PMOS pipe is adopted body terminal voltage regulation technology;

(5) the utility model is when adopting read-write bitline separation technology to reduce bit line capacitance; The method that adopt to strengthen write word line WWL strengthens writes driving force, strengthens simultaneously and writes the logic driving force more weak to selected unit not reducing other storage unit stability of not read and write;

(6) the utility model creatively adopts the mode of logical organization of change storage unit to make this design can all adopt the transistor of minimum dimension, improves design robustness satisfying under the area-constrained condition.Read buffer circuit and make that the readability of storage unit is able to guarantee; Writability is guaranteed by the external control signal WWL that strengthens.It is area-constrained that this makes that the present invention can all adopt the transistor of minimum dimension to satisfy memory circuit.

In a word; The utility model can not increase the additional management power consumption and not reduce under the prerequisite of performance in the assurance system, reduces when realizing dynamic energy consumption and static leakage power consumption, improves cell robustness; Each item index of balanced memory cell makes the system performance optimization.The sub-threshold storing unit circuit that PMOS substrate (being the body end) is regulated; Its PMOS reads to mate pipe and PMOS substrate regulation technology can not increase the additional management power consumption and not reduce under the prerequisite of performance; Reduce when realizing dynamic energy consumption and static leakage power consumption, have characteristics such as high robust concurrently.

Description of drawings

Fig. 1 is the utility model circuit structure diagram;

Fig. 2 is the utility model double dight wire johning knot composition;

The oscillogram comparison of reading " 0 " operation bit line that Fig. 3 is the utility model when on every bit line, connect 512 number of memory cells with reference to 10 pipe units (10T);

The oscillogram of reading " 0 " operation bit line that Fig. 4 is the utility model when on every bit line, connecting 1024 number of memory cells with reference to 10T relatively;

The oscillogram of Fig. 5 bit line leakage current that is the utility model when on every bit line, connecting 512 number of memory cells with reference to 10T relatively;

Fig. 6 (a) is with reference to the unit static leakage current distribution plan of 10T under technology mismatch situation, and Fig. 6 (b) is the unit static leakage current distribution plan of the utility model under technology mismatch situation;

Fig. 7 (a) is the static noise margin figure that reads of the present invention, and Fig. 7 (b) is the static noise margin figure that writes of the present invention, and Fig. 7 (c) is the maintenance static noise margin figure of the utility model;

Fig. 8 is the utility model and comparison sheet with reference to three kinds of noise margin values of 10T;

Fig. 9 (a) is with reference to the read noise tolerance limit distribution plan of 10T under technology mismatch situation, and Fig. 9 (b) is the read noise tolerance limit distribution plan of the utility model under technology mismatch situation;

Figure 10 (a) writes the noise margin distribution plan with reference to 10T under technology mismatch situation, Figure 10 (b) is that the utility model is write the noise margin distribution plan under technology mismatch situation;

Embodiment

Referring to Fig. 1; The utility model storage unit circuit is made up of ten transistors (10T): four PMOS pipe P1, P2, P3, P4 and six NMOS pipe N1～N6; Constitute the sub-threshold storing unit circuit of both-end read-write, have the double dight wire structure, a pair of write bit line and a pair of sense bit line are promptly arranged.

Wherein, the body end (substrate) of four PMOS pipes is connected with its grid end respectively, the body end ground connection GND of six NMOS pipes; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end that PMOS manages P1 respectively, form first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end that PMOS manages P2 respectively, form second phase inverter; First phase inverter and second phase inverter connect into cross-couplings; The drain terminal of the grid end of NMOS pipe N1 grid end, PMOS pipe P1 and body end thereof, NMOS pipe N2, the drain terminal of PMOS pipe P2, the source end of NMOS pipe N4 and the grid end of NMOS pipe N6 are connected; The grid end of the source end of the grid end of the grid end of the drain terminal of the drain terminal of NMOS pipe N1, PMOS pipe P1, NMOS pipe N2, PMOS pipe P2 and body end thereof, NMOS pipe N3 and NMOS pipe N5 is connected; The source end of PMOS pipe P1, P2 is connected with supply voltage VDD, and the source end of NMOS pipe N1, N2, N5, N6 connects together, and ground connection GND;

The grid end of the grid end of NMOS pipe N3 and NMOS pipe N4 links together, and is connected on the write word line WWL; The drain terminal of NMOS pipe N3 is connected on the write bit line WBL; The drain terminal of NMOS pipe N4 is connected on another root write bit line WBLB; The grid end of the grid end of the grid end of the drain terminal of the drain terminal of the source end of NMOS pipe N3 and NMOS pipe N1, PMOS pipe P1, NMOS pipe N2, PMOS pipe P2 and body end thereof, NMOS pipe N5 links together; The grid end of the grid end of the grid end of the drain terminal of the drain terminal of the source end of NMOS pipe N4 and NMOS pipe N2, PMOS pipe P2, NMOS pipe N1, PMOS pipe P1 and body end thereof, NMOS pipe N6 links together;

The drain terminal of the drain terminal of NMOS pipe N5 and PMOS pipe P3 links together; The source end of the source end of NMOS pipe N5 and NMOS pipe N1, N2, N6 links together; And being connected to ground GND, the drain terminal of the source end of the grid end of NMOS pipe N5 and NMOS pipe N3, the drain terminal of NMOS pipe N1, PMOS pipe P1, the grid end of NMOS pipe N2, grid end and the body end thereof of PMOS pipe P2 link together; The drain terminal of the drain terminal of PMOS pipe P3 and NMOS pipe N5 links together; Grid end and the body end thereof of the grid end of PMOS pipe P3 and its body end, PMOS pipe P4 link together, and are connected on the readout word line RWL; The source end of PMOS pipe P3 is connected on the sense bit line RBL;

The drain terminal of the drain terminal of NMOS pipe N6 and PMOS pipe P4 connects together; The source end of the source end of NMOS pipe N6 and NMOS pipe N1, N2, N5 connects together; And being connected to ground GND, the drain terminal of the source end of the grid end of NMOS pipe N6 and NMOS pipe N4, the drain terminal of NMOS pipe N2, PMOS pipe P2, the grid end of NMOS pipe N1, grid end and the body end thereof of PMOS pipe P1 link together; The drain terminal of the drain terminal of PMOS pipe P4 and NMOS pipe N6 links together; Grid end and the body end thereof of the grid end of PMOS pipe P4 and body end thereof and PMOS pipe P3 link together, and are connected on the readout word line RWL; The source end of PMOS pipe P4 is connected on the sense bit line RBLB;

The grid end of NMOS pipe N3, N4 is connected with write word line WWL, and grid end and the body end thereof of the grid end of PMOS pipe P3 and body end thereof, PMOS pipe P4 are connected with readout word line RWL; The drain terminal of NMOS pipe N3 is connected on the write bit line WBL; The drain terminal of NMOS pipe N4 is connected on another root write bit line WBLB; The source end of PMOS pipe P3 is connected on the sense bit line RBL; The source end of PMOS pipe P4 is connected on another root sense bit line RBLB.

As a transistor that uses separately, its source end and drain terminal can exchange.In conventional design especially digital circuit, because PMOS pipe often is used in pull-up circuit, NMOS often is used in pull-down circuit, thus their source end can fix to be connected on supply voltage VDD motionless with ground GND.But in design of the present invention, because characteristic that storage unit had: when write operation, the signal on write bit line and write bit line non-is written into storage unit; When read operation, the inner signal of storage unit is read on sense bit line and sense bit line non-.As NMOS pipe N3, N4 and the PMOS pipe P3 of coupling pipe, the signal at P4 two ends are dynamic changes.And according to the definition of source transistor end, drain terminal: the output terminal of charge carrier is the source end; The receiving terminal of charge carrier is a drain terminal; Though the concrete annexation of storage unit does not change, the port definition at transistor N3, N4 and PMOS pipe P3, P4 two ends can change the size variation of last current potential along with the storage unit internal information and with respect to paratope line.

Referring to Fig. 2; In the actual operating process of the utility model, during write operation, be data-signal to be strobed on a write bit line WBL and another root write bit line WBLB by write control circuit; Open NMOS pipe N3, N4 through write word line WWL signal controlling again; Signal on write bit line WBL and the WBLB is sent to internal node, changes the inner information of storage unit, accomplish the operating process that both-end is write.During read operation; Unlatching through readout word line RWL signal controlling PMOS pipe P3, P4; Read NMOS pipe N5, N6 in the buffer circuit then according to storage unit internal node RB, the different different working states that appear of RT canned data, so, buffer circuit read by what PMOS pipe P3, NMOS pipe N5 and PMOS pipe P4, NMOS pipe N6 formed; Can the internal information of storage unit be sent on two complementary sense bit line RBL and the RBLB; By the gating of column selection signal controlling CMUX, make the paratope line signal get into sense amplifier identification and amplify again, accomplish the operating process that both-end is read.

The principle of work of the sub-threshold storing unit circuit of the utility model super low energy consumption, high robust is following:

1, read operation

Because in the subthreshold value circuit of ELV work; Circuit receives the influence of noise and technological fluctuation very obvious; And; In the design of storage array, three static noise margins: read static noise margin, write static noise margin, keep reading the static noise margin minimum in the static noise margin.How to expand and read the bottleneck that static noise margin becomes the sub-threshold memory cell design.If can read Problem of Failure to the interference of unit node information with regard to solving by masking operation process neutrality line current potential, and then expansion read noise tolerance limit.In sub-threshold memory cell of the present invention, P3, P4 combine N5, N6 to form buffer circuit, and it can guarantee in the read operation process that the information of memory cell storage is not destroyed, and then expands the static noise margin of reading of sub-threshold memory cell.The tie point of NMOS pipe N1 grid end and PMOS pipe P1 grid end is RT, and the tie point of NMOS pipe N2 grid end and PMOS pipe P2 grid end is RB, supposes under the starting condition RB=" 1 ", RT=" 0 " (" 1 " expression high level, " 0 " expression low level).In the read operation process, RWL is set to " 0 ", and WWL is " 0 ".At this moment, write coupling pipe N3, N4 turn-offs, and read coupling pipe P3, P4 is in opening.Consider RB=" 1 ", RT=" 0 ", transistor N5 conducting, N6 ends; Like this when read operation; The electric charge that sense bit line RBL goes up preliminary filling can discharge through P3 and N5, and the electric charge on another root sense bit line RBLB can not bleed off, thereby reads Q point canned data.In view of memory node and bitline separation in this operating process, the current potential of preliminary filling can not cause the rising of memory node current potential on the bit line, the most critical of subthreshold value SRAM design problem---the read noise tolerance limit is expanded.Be that the diverse read schemes that adopts among the present invention has improved the anti-noise ability that reads storage unit in the process, strengthened the robustness of SRAM.Fig. 7 (a) has showed the read noise tolerance limit emulation synoptic diagram of the utility model unit.

2, write operation

In the subthreshold value circuit design, subthreshold value zone overdrive voltage reduces, load capacitance is big and under the condition of technique change, keep enough write capabilities is another challenge of sub-threshold memory cell design.Conventional method is in the write operation process, further to reduce sub-threshold memory cell VDD to write driving force with enhancing.But this also reduces the maintenance operational stability of storage unit in other not selected row of sharing same VDD simultaneously.In order to strengthen the write capability of subthreshold value unit, the utility model adopts read-write bitline separation technology, the remarkable like this load capacitance that reduces write bit line, and simultaneously, the utility model adopts and strengthens write word line WWL signal voltage, strengthens and writes driving force.When write operation; Write word line signal WWL is high level " 1 ", and readout word line RWL also is a high level " 1 ", so PMOS manages P3, the P4 pipe ends; NMOS pipe N3, N4 conducting, the signal on the non-WBLB of write bit line WBL and write bit line just passes to the unit internal node through N3, N4 pipe like this.Fig. 7 (b) writes noise margin emulation synoptic diagram for the utility model unit.

3, keep operation

Keeping operating period, write word line WWL is set to " 0 ", and readout word line RWL is " 1 ".Write coupling pipe N3, N4 shutoff, information on the write bit line and cell stores information isolation; Equally, read coupling pipe P3, P4 shutoff, information on the sense bit line and cell stores information isolation.Information is kept by cross-linked two phase inverters.Fig. 7 (c) is the maintenance noise margin emulation synoptic diagram of the utility model unit.

Reading static noise margin is the crucial noise margin of conventional storage unit.In the subthreshold value zone, because rapid deterioration, the memory node of storage unit is more vulnerable to the influence of bit line potential fluctuation.For addressing this problem, the sub-threshold memory cell of the utility model adopts transistor P3-N5, and P4-N6 forms and reads buffer circuit.This buffer circuit can be with the information isolation on memory node and the bit line in concrete read operation process, so the extension storage unit read static noise margin.Keep static noise margin to become the crucial noise margin of the design's storage unit like this.Fig. 8 has showed that people such as unit and the C.Ik Joon of the utility model is published in the comparison of a three kinds of noise margin values with reference to the 10T design among the IEEE; Wherein Read SNM representes the read noise tolerance limit; Write SNM representes to write noise margin; Hold SNM representes to keep noise margin, obviously the utlity model has more excellent noise margin.

For further relatively unit of the present invention and performance with reference to the anti-technology mismatch of 10T; The utility model has carried out 1000 times Monte Carlo simulation; Fig. 9 (a) is the distribution plan of read noise tolerance limit under technology mismatch situation with reference to 10T; Fig. 9 (b) is the distribution plan of read noise tolerance limit under technology mismatch situation of the utility model 10T; The mean value (mean) of read noise tolerance limit that can find out the utility model 10T big than with reference to 10T, and discrete standard poor (std) little than with reference to 10T explain that the anti-technology mismatch of read noise tolerance limit of the utility model is better.

Figure 10 (a) is for writing the distribution plan of noise margin under technology mismatch situation with reference to 10T; Figure 10 (b) writes the distribution plan of noise margin under technology mismatch situation for the utility model 10T's; The mean value of writing noise margin (mean) that can find out the utility model big than with reference to 10T; And discrete standard poor (std) little than with reference to 10T explains that the anti-technology mismatch of writing noise margin of the utility model 10T is better equally.

4, the storage unit of super low energy consumption

Verified in relevant document, reduce the reduction dynamic energy consumption that supply voltage can be quadratic term.If but further reduce supply voltage VDD can cause leaking energy consumption once to optimum supply voltage increase; This is because postpone the increase of the index along with the reduction of supply voltage; Thereby increased total leakage energy consumption, the optimum supply voltage of document description is in sub-threshold region simultaneously.In present System on Chip/SoC design, storage array occupies sizable area.Simultaneously, each storage unit of the functional requirement of storage array need keep data for a long time.So further reduce the bit line leakage current, reduce dynamic power consumption, and the quiescent dissipation of restriction SRAM storage array a key and very important problem have been become.Introduced the superthreshold state limit leakage current scheme of typical case's six pipe storage arrays down in the relevant document.But they all do not consider dynamic energy consumption and static leakage current simultaneously.The utility model provides a kind of subthreshold value sram cell of super low energy consumption, it can realize the minimizing of dynamic operation (read/write operation) and static state operation leakage current simultaneously under the prerequisite that does not influence performance.

$I_{\mathrm{sub}}={\mathrm{<figure-callout\; id="0"\; label="I\; sub"\; filenames="HDA0000136346320000031.png,HDA0000136346320000041.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{sub}}\&CenterDot;e^{\frac{(V_{\mathrm{GS}}-V_{\mathrm{th}}+\mathrm{\&eta;}{V}_{\mathrm{DS}}-\mathrm{\&gamma;}{V}_{\mathrm{SB}})}{n{V}_T}}(1-e^{\frac{-\left(V_{\mathrm{DS}}\right)}{V_T}})---\left(1\right)$

I wherein _SubBe subthreshold current, n is a subthreshold value amplitude of oscillation parameter, and η leaks to cause potential barrier reduction effect (DIBL) coefficient, and γ is a body-effect coefficient, V _GSBe gate source voltage, V _DSBe drain-source voltage, V _TBe thermal voltage kT/q, its value at room temperature approximates 26mV greatly, and k is that bohr is grown graceful constant, and T is an environment temperature, and q is the electric charge constant.I _Sub0Be V _GS=V _Th, the specific currents that obtains under the W/L=1 condition, W is transistorized channel width, L is transistorized channel length, V _ThBe threshold voltage.V _Th0Be the threshold voltage of substrate bias when being " 0 ", V _SBBe the source body bias.

Shown in formula (1), the principle that reduces leakage current is: subthreshold value zone drain-source current is along with V _GSBe exponential variation with poor (the device overdrive voltage) of transistorized threshold voltage.As PMOS, when the current potential of source end S descends, V _SGCan reduce,, cause the electric current of PMOS to descend rapidly so the overdrive voltage of PMOS reduces.The utility model is used in this current characteristics of PMOS in the subthreshold value unit design.

The utility model adopts the PMOS pipe as reading the coupling pipe, supposes under the worst case of read operation in the array storage unit, to have only the RT=" 1 " of a unit b0, RB=" 0 ", the RT=of other unit " 0 ", RB=" 1 ".When unit b0 was carried out read operation, the P3 of b0 unit, N5 read buffer circuit and open, and sense bit line RBL current potential descends; And in the remaining unit that another root sense bit line RBLB is connected, because the coupling pipe is read in PMOS pipe P4 conduct, along with the decline of RBLB, the overdrive voltage of PMOS significantly descends, and causes the current index level of PMOS to descend, so the leakage current of sense bit line RBLB is very little.Simultaneously, the less characteristic of current ratio NMOS when remedying the PMOS ON state, the utility model adopts PMOS underlayer voltage dynamic adjustment technique; The substrate that is about to the PMOS pipe is connected to its grid end; When the conducting of PMOS pipe, its threshold voltage can descend, and then has improved the working current of PMOS pipe.

In order to verify the leakage current characteristic of the utility model unit, carry out read operation during the different unit of series connection on the utility model pairs of bit line, and be arranged to worst case, it is opposite with other unit canned datas promptly to be read in the unit canned data in the row.Like this, the leakage current on the sense bit line is maximum.

Fig. 3 is the read operation bit-line voltage simulation waveform figure when connecting 512 unit on the sense bit line.Can find out and compare that the sense bit line RBLB of the utility model unit reaches required pressure reduction earlier than the bit line BLB with reference to 10T with reference to 10T.And the leakage current of the sense bit line RBL of the utility model unit is than with reference to little many of the bit line BL leakage current of 10T.The theoretical explanation of having been discussed below this has just confirmed through emulation, promptly along with the decline of bit line current potential, the leakage current of the utility model unit reduces rapidly.Exactly because the utility model bit line leakage current is very little, can normally read so can connect 1024 unit on the sense bit line of the storage array of employing the utility model unit, and with reference to the 10T cisco unity malfunction, as shown in Figure 4.In addition, the bit line decline current potential during from read operation can be found out, adopts the bit-line voltage of the utility model unit to drop in the 0.5VDD, so it is lower to read dynamic energy consumption.

Fig. 5 is the simulating, verifying that bit line leakage current carried out when further checking is static; As can be seen from the figure; When on bit line, connecting 512 unit, the bit-line voltage of the utility model unit only drops to 0.28V, and has dropped to 0.18V with reference to the bit-line voltage of 10T; So the static bit line leakage current of the utility model unit is much smaller.

That is the sub-threshold memory cell that the utility model proposes is not increasing the additional management power consumption and is not reducing under the prerequisite of performance, reduction when having realized bit line dynamic energy consumption and the static state operation neutrality line leakage power in the dynamic operation.

Because the most of unit in the storage array are in holding state, so the static leakage current of unit also is the important indicator of a unit design.The utility model is verified this; Fig. 6 (a) has shown the distribution situation of static leakage current under consideration process deviation and device mismatch condition with reference to 10T, and Fig. 6 (b) has shown that the utility model 10T is in the distribution situation of considering under process deviation and the device mismatch condition.The result is 121.328pA with reference to the average of the leakage current of 10T (mean), and standard deviation (std) is 60.5316pA; The average (mean) of the leakage current of the utility model 10T unit is 98.2054pA, and standard deviation (std) is 50.1827pA, explains that the leakage current of the utility model under technology mismatch situation is less.

Compare with the 10T storage unit of reference, the utility model 10T demonstrates following characteristics: (1) static time unit leakage current has increased 23.5%; (2) standard deviation of unit leakage current has reduced 20.6%.This explanation is the sub-threshold memory cell design equally, and the utility model design has better technology robustness.

Claims (1)

1. a double dight wire sub-threshold storing unit circuit is characterized in that, comprises four PMOS pipe P1～P4 and six NMOS pipe N1～N6, constitutes the sub-threshold storing unit circuit of both-end read-write, has a pair of write bit line and a pair of sense bit line, wherein:

The substrate of four PMOS pipe P1～P4 is connected with separately grid end respectively, and six NMOS manage the equal ground connection GND of substrate of N1～N6; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end that PMOS manages P1 respectively, constitute first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end that PMOS manages P2 respectively, constitute second phase inverter; First phase inverter and second phase inverter connect into cross-couplings: the grid end of NMOS pipe N1 grid end, PMOS pipe P1 and the drain terminal of NMOS pipe N2 and the drain terminal of PMOS pipe P2 link together; The drain terminal of the drain terminal of the grid end of the grid end of NMOS pipe N2, PMOS pipe P2 and NMOS pipe N1 and PMOS pipe P1 links together, and the source end of PMOS pipe P1, P2 all is connected with supply voltage VDD; The drain terminal of the drain terminal of the grid end of the source end of NMOS pipe N3, NMOS pipe N5 and PMOS pipe P1 and NMOS pipe N1 links together, and the grid end of NMOS pipe N3 connects write word line WWL, and the drain terminal of NMOS pipe N3 connects write bit line WBL; The drain terminal of NMOS pipe N5 connects the drain terminal of PMOS pipe P3; The grid end of PMOS pipe P3 connects readout word line RWL, and the source end of PMOS pipe P3 connects sense bit line RBL, and the drain terminal of the grid end of the source end of NMOS pipe N4, NMOS pipe N6 and the drain terminal of PMOS pipe P2 and NMOS pipe N2 links together; The grid end of NMOS pipe N4 connects write word line WWL; The drain terminal of NMOS pipe N4 connects another root write bit line WBLB, and the drain terminal of NMOS pipe N6 connects the drain terminal of PMOS pipe P4, and the grid end of PMOS pipe P4 connects readout word line RWL; The source end of PMOS pipe P3 connects another root sense bit line RBLB, the equal ground connection GND of source end of NMOS pipe N1, N2, N5, N6.

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