CN202534359U - Integrated circuit system - Google Patents
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- CN202534359U CN202534359U CN2012200654863U CN201220065486U CN202534359U CN 202534359 U CN202534359 U CN 202534359U CN 2012200654863 U CN2012200654863 U CN 2012200654863U CN 201220065486 U CN201220065486 U CN 201220065486U CN 202534359 U CN202534359 U CN 202534359U
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- 238000005457 optimization Methods 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 18
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Abstract
The utility model provides an integrated circuit system. The integrated circuit system comprises an application logic integrated circuit, at least one internal memory integrated circuit and a serial channel control unit, wherein the application logic integrated circuit comprises an application processing unit and an internal memory control unit; the internal memory control unit comprises a bus; each internal memory integrated circuit comprises a first channel interface, an internal memory array and a second channel interface; the internal memory array is used for storing data; the serial channel control unit is coupled with the second channel interface and is used for output the data; the bus is applicable to the application processing unit and the internal memory integrated circuit; and the application logic integrated circuit, the at least one internal memory integrated circuit and the serial channel control unit are integrated in reserved encapsulation. The internal memory control unit can be customized to be suitable for different application processing units and internal memory integrated circuits, so the integrated circuit system has optimal efficacy, efficiency and cost.
Description
Technical field
The utility model relates to a kind of IC system, refer to especially a kind of through customized memory control unit, with the IC system of the usefulness, efficient and the cost that promote memory control unit.
Background technology
Generally speaking; Memory integrated circuits usually can be based on particular industry standard (jedec (Joint Electronic Device Engineering Council, JEDEC)) and be designed to be independent of the standard memory integrated circuit of applied logic integrated circuit for example.That is based on the particular industry standard, memory integrated circuits is the standard memory integrated circuit that is designed to be applicable to various different application logical integrated circuits, rather than be designed to be applicable to the application-specific logical integrated circuit.
In the applied logic integrated circuit, the applied logic integrated circuit needs Memory Controller Hub with the communication between control criterion memory integrated circuits and the applied logic integrated circuit.Because Memory Controller Hub must be linked up with various standard memory integrated circuit; So the Memory Controller Hub in applied logic integrated circuit tendency is designed usefulness, efficient and the cost with inferior goodization, with in response to various standard memory integrated circuit.
Yet, now industry tend to provide the good really chip of memory integrated circuits (known good die) with convenient and applied logic integrated circuit be integrated in the particular system level encapsulate (System in Package, SIP).Because the applied logic integrated circuit only needs and the good really chip of memory integrated circuits (not need in response to various standard memory integrated circuit); So if the Memory Controller Hub in the applied logic integrated circuit still is designed to have usefulness, efficient and the cost of inferior goodization; With in response to various standard memory integrated circuit, then the applied logic integrated circuit will can not brought into play maximum efficiency.
The utility model content
One embodiment of the utility model provides a kind of IC system.This IC system comprises applied logic integrated circuit, at least one memory integrated circuits and serial channel control module.This applied logic integrated circuit comprises application processing unit and memory control unit.This memory control unit is to be coupled to this application processing unit, and this memory control unit has bus.Each memory integrated circuits in this at least one memory integrated circuits comprises first channel interface, memory array and second channel interface.This first channel interface is to be coupled to this memory control unit; This memory array is in order to storage data.This serial channel control module is to be coupled to this second channel interface, in order to export this data; Wherein this bus is customized being applicable to this application processing unit and this memory integrated circuits, and this applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation.
An also embodiment of the utility model provides a kind of IC system.This IC system comprises applied logic integrated circuit, at least one memory integrated circuits and serial channel control module.Each memory integrated circuits in this at least one memory integrated circuits comprises first channel interface, memory array and second channel interface.This memory array is in order to storage data.This serial channel control module is to be coupled to this second channel interface, in order to export this data.This applied logic integrated circuit comprises application processing unit and memory control unit.This memory control unit is to be coupled to this application processing unit and this first channel interface, and wherein this memory control unit has bus, and this memory control unit is in order to support variable voltage, variable frequency or variable bus bit wide; Wherein this applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation
An also embodiment of the utility model provides a kind of IC system.This IC system comprises applied logic integrated circuit, at least one memory integrated circuits and serial channel control module.This applied logic integrated circuit comprises application processing unit and memory control unit.Each memory integrated circuits in this at least one memory integrated circuits comprises first channel interface, memory array and second channel interface.This memory array is in order to storage data.This serial channel control module is to be coupled to this second channel interface, in order to export this data.This memory control unit is to be coupled to this application processing unit and this first channel interface, and wherein this memory control unit has bus, and this memory control unit is in order to support variable voltage, variable frequency or variable bus bit wide; Wherein this bus is customized being applicable to this application processing unit and this memory integrated circuits, and this applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation.
The utility model provides a kind of IC system.This IC system is to utilize customized memory control unit, to be applicable to application processing unit and memory integrated circuits.In addition, the applied logic integrated circuit in the utility model, at least one memory integrated circuits and serial channel control module are to be integrated in the predetermined encapsulation.Therefore; The utility model not only can dwindle the area of this IC system; And because this memory control unit of the utility model can be by customized with in response to different application processing unit and memory integrated circuits, so have optimized usefulness, efficient and cost.
Description of drawings
Fig. 1 is the synoptic diagram that a kind of IC system is provided for an embodiment of the utility model.
Fig. 2 is for explaining that bus is customized to be applicable to the synoptic diagram of application processing unit and two memory integrated circuits.
Fig. 3 becomes a synoptic diagram with memory integrated circuits of larger capacity for explaining that two memory integrated circuits are integrated through the salient point array.
Fig. 4 is for the synoptic diagram of encapsulation one on top of another is described.
Fig. 5 is the synoptic diagram for encapsulation in the explanation encapsulation.
Fig. 6 is the synoptic diagram for the encapsulation of illustrative system level.
Fig. 7 is for IC system being described according to the picture signal that produces from two cameras, being produced the synoptic diagram of looking dark of object.
Fig. 8 is the synoptic diagram for explanation camera and visual angle.
Fig. 9 is the synoptic diagram that a kind of IC system is provided for an also embodiment of the utility model.
Wherein, description of reference numerals is following:
100,900 IC systems
102 applied logic integrated circuit
103,104,105 memory integrated circuits
106 serial channel control modules
107 salient point arrays
108 next stage circuit
110 predetermined encapsulation
402,404,502,504 encapsulation
406,506,508,606,608 standard interfaces
408 ball grid array
Encapsulation in 500 encapsulation
600 system in package
801 imageing sensors
802 lens
803 positions
804 centers
912 buffers
1022 application processing unit
1024 memory control units
1026 applied logic integrated circuit interfaces
1,042 first channel interfaces
1044 memory arrays
1046 second channel interfaces
10242 buses
C1, C2 camera
CD, W distance
D looks deeply
The O object
The PD pixel distance
θ 1, θ 2 visual angles
Embodiment
Please with reference to Fig. 1, Fig. 1 is the synoptic diagram that a kind of IC system 100 is provided for an embodiment of the utility model.As shown in Figure 1, IC system 100 comprises applied logic integrated circuit 102, memory integrated circuits 104 and serial channel control module 106.But the utility model is not limited to only comprise memory integrated circuits 104, that is the utility model can comprise more than one memory integrated circuits.Applied logic integrated circuit 102 comprises application processing unit 1022, memory control unit 1024 and applied logic integrated circuit interface 1026.Applied logic integrated circuit interface 1026 is to be coupled to application processing unit 1022 and memory control unit 1024, produces from the picture signal of two camera C 1 with C2 in order to receive.Application processing unit 1022 is to be the 3D rendering acquisition unit, in order to according to producing from the picture signal of two camera C 1 with C2, produces the D that looks dark of object O.But in an also embodiment of the utility model, application processing unit 1022 is to be 2D capturing images unit, and applied logic integrated circuit interface 1026 receives the picture signal that produces from a camera C 1.Memory control unit 1024 is to be coupled to application processing unit 1022; Memory control unit 1024 is to can be parallel memory control unit; Has bus 10242; Wherein bus 10242 is customized being applicable to application processing unit 1022 and memory integrated circuits 104, and bus 10242 can be supported at least 32.That is memory control unit 1024 is not the standard memory control module that meets jedec (JEDEC), so memory control unit 1024 can be optimized design, with in response to memory integrated circuits 104.In addition; Memory control unit 1024 is through direct silicon wafer perforation (Through Silicon Via; TSV) technological manufacturing, wherein directly the silicon wafer puncturing technique is that wafer is carried out vertical stack, on wafer, holes with the mode of etching or laser; Again conductive material such as copper, polysilicon, tungsten etc. are inserted the technology that boring forms the passage of conduction, make lead connect contraction in length to the thickness that equals the storehouse wafer.In addition, please with reference to Fig. 2, Fig. 2 is for explaining that bus 10242 is customized to be applicable to the synoptic diagram of application processing unit 1022 and two memory integrated circuits 103,105.As shown in Figure 2, bus 10242 can be by customized to support two memory integrated circuits 103,105 simultaneously, and wherein the bus bit wide of two memory integrated circuits 103,105 (Bus width) is to can be 16,32,64,128,256 or 512.So, through can flexibly being expanded the bus bit wide of the memory array in the IC system 100 by customized bus 10242.Please with reference to Fig. 3, Fig. 3 becomes a synoptic diagram with memory integrated circuits of big bus bit wide for explaining that two memory integrated circuits 103,105 are integrated through salient point array (Bump array) 107.As shown in Figure 3, two memory integrated circuits 103,105 also can be integrated through salient point array 107 and become a memory integrated circuits.Then, two memory integrated circuits 103,105 can be linked up through the bus in salient point array 107 and the memory control unit 1,024 10242.But the utility model is not limited to integrate two memory integrated circuits 103,105 through salient point array 107, that is the utility model also can be through fuse or rewiring technological (redistribution technique) to integrate two memory integrated circuits 103,105 or more memory integrated circuits.
As shown in Figure 1, memory integrated circuits 104 is to be true good chip.Memory integrated circuits 104 comprises first channel interface 1042, memory array 1044 and second channel interface 1046.First channel interface 1042 is to be coupled to memory control unit 1024, and in order to support the communication between memory control unit 1024 and the memory integrated circuits 104, wherein first channel interface 1042 is to can be the parallel channel interface.In addition, in an also embodiment of the utility model, memory control unit 1024 is to be the serial memory control unit, and first channel interface 1042 is for supporting the serial channel interface of memory control unit 1024.Memory array 1044 is to be coupled to first channel interface 1042, in order to store the D that looks dark that produces from the picture signal of two camera C 1 and C2 and object O.Second channel interface 1046 is to be coupled to memory array 1044, and wherein the D that looks dark of object O is sent to serial channel control module 106 through second channel interface 1046, and second channel interface 1046 is to can be the serial channel interface.
As shown in Figure 1, serial channel control module 106 is to be coupled to second channel interface 1046, looks dark D to next stage circuit 108 in order to provide quick binding pipeline object output O's.For example (System in Package, SIP) integrated circuit or chip directly encapsulate (Chip on Board, COB) circuit to system in package.In addition; Serial channel control module 106 is for cooperating next stage circuit 108; And can be universal serial bus 3.0 control modules, serial advanced technology attachment (Serial Advanced Technology Attachment; SATA) control module or high-speed peripheral device interconnecting interface (Peripheral Component Interconnect Express, PCIE) control module.
As shown in Figure 1; Applied logic integrated circuit 102, memory integrated circuits 104 are to be integrated within the predetermined encapsulation 110 with serial channel control module 106; Predetermined encapsulation 110 is to can be encapsulation (Package in Package in the encapsulation; PIP), encapsulation one on top of another (Package on package, POP) or system in package (System in Package, SIP).
Please with reference to Fig. 4, Fig. 4 is for the synoptic diagram of encapsulation one on top of another is described.Encapsulation one on top of another is to be the encapsulation in order to integration logical integrated circuit and memory integrated circuits.In encapsulation one on top of another, two or more encapsulation can be passed through standard interface and the mutual storehouse of ball grid array.Therefore, encapsulation one on top of another is applicable to the product of the higher component density of demand, for example mobile phone, personal digital assistant (Personal digital assistant, PDA) or digital camera etc.As shown in Figure 4, the encapsulation 402 of memory integrated circuits 104 is through standard interface 406 and ball grid array 408 mutual storehouse and communications with 102 encapsulation 404 of applied logic integrated circuit.
Please with reference to Fig. 5, Fig. 5 is the synoptic diagram for encapsulation 500 in the explanation encapsulation.Encapsulation 500 is to be the encapsulation in order to integration logical integrated circuit and memory integrated circuits in the encapsulation.In the encapsulation 500, two or more encapsulation can be through standard interface and separately mutual storehouse of encapsulation and communication in encapsulation.Therefore, encapsulation 500 is the same with encapsulation one on top of another also applicable to the product of the higher component density of demand in the encapsulation.As shown in Figure 5, the encapsulation of memory integrated circuits 104 502 and 102 encapsulation 504 of applied logic integrated circuit are through standard interface 506 and 508 and separately mutual storehouse of encapsulation and communication.
Please with reference to Fig. 6, Fig. 6 is the synoptic diagram for illustrative system level encapsulation 600.System in package 600 is to be the encapsulation in order to integration logical integrated circuit and memory integrated circuits.In system in package 600, two or more encapsulation can be passed through mutual storehouse of standard interface and communication.Therefore, encapsulation 600 is the same with encapsulation one on top of another also applicable to the product of the higher component density of demand in the encapsulation.As shown in Figure 6, memory integrated circuits 104 is through standard interface 606 and 608 mutual storehouse and communications with applied logic integrated circuit 102.
Please with reference to Fig. 7, Fig. 7 is for explaining that IC system 100 according to producing from the picture signal of two camera C 1 with C2, produces the synoptic diagram of looking dark D of object O.As shown in Figure 7, produce picture signal from two camera C 1 and C2 and comprise view angle theta 2 and the distance W between camera C 1 and the camera C 2 between view angle theta 1, camera C 2 and the object O between camera C 1 and the object O.Therefore; Please with reference to Fig. 1; IC system 100 can receive view angle theta 1, view angle theta 2 and distance W through applied logic integrated circuit interface 1026, and stores view angle theta 1, view angle theta 2 and distance W in memory array 1044 through the memory control unit 1024 and first channel interface 1042.Then, application processing unit 1022 can calculate the dark D of looking of object O according to view angle theta 1, view angle theta 2, distance W and triangle distance measurement method.
Please with reference to Fig. 8, Fig. 8 is the synoptic diagram that produces view angle theta 1 for explanation camera C 1 and camera C 1.As shown in Figure 8, camera C 1 comprises imageing sensor 801 and lens 802.Reflection is after the rays pass through lens 802 of object O, and 803 form images in the position, and wherein the pixel distance between the center 804 of position 803 and imageing sensor 801 is to be PD, and the distance between imageing sensor 801 and the lens 802 is to be CD.Therefore, the application processing unit 1022 in the IC system 100 can calculate view angle theta 1 according to pixel distance PD and distance C D through the look-up table of triangulation.In like manner, camera C 2 is all identical with camera C 1 generation view angle theta 1 with camera C 1 with the principle that camera C 2 produces view angle theta 2, repeats no more at this.
In addition, in order to look dark the accuracy in computation of D, the pixel distance PD of Fig. 8 can be through specific interpolation algorithm (interpolation algorithm) actuarial to sub-pixel grade.
In addition, for the object in the motion the dark figure of looking of summary only need be provided (depth map).Looking when dark of object in calculating motion; Some logical operations of application processing unit 1022 in the IC system 100 can only be confined in the mobility scale (regions of change) of object; The non-zero pixels (non-zero pixel) of the different pictures in two adjacent pictures of time series picture that wherein can be through identification sampling is to produce the mobility scale of object.
Please with reference to Fig. 9, Fig. 9 is the synoptic diagram that a kind of IC system 900 is provided for an also embodiment of the utility model.The difference of IC system 900 and IC system 100 is that IC system 900 also comprises buffer 912, in order to store 1024 variable voltages that can support of memory control unit, variable frequency or variable bus bit wide.Therefore, memory control unit 1024 can be consulted variable voltage, variable frequency or variable bus bit wide that buffer 912 is supported with suitable adjustment according to the usefulness and the characteristic of memory integrated circuits 104.For example; When memory array 1044 is to be low-power second generation double data rate SDRAM (Low power Double-Data-Rate Two Synchronous Dynamic Random Access Memory; LPDDR2) time, the variable voltage that memory control unit 1024 is supported is between 0V-0.6V; When memory control unit 1024 is during in order to data signal and position signalling, the variable voltage that memory control unit 1024 is supported is between 0.3V-0.9V.In addition, the variable frequency that memory control unit 1024 is supported is the power consumption in order to optimization memory control unit 1024, and wherein the power consumption P of memory control unit 1024 is determined by formula (1):
P＝C*(VH-VL)
2*f*n (1)
In formula (1), C be for the stray capacitance of memory control unit 1024, VH be that the upper bound, the VL of the variable voltage supported for memory control unit 1024 is that lower bound, the f of the variable voltage supported for memory control unit 1024 is that variable frequency and the n that is supported for memory control unit 1024 is the pin count for bus 10242.Therefore, IC system 900 can be according to the usefulness and the characteristic of formula (1) and memory integrated circuits 104, and the power consumption of optimization memory control unit 1024 is to satisfy the speed requirement of memory integrated circuits 104.
In sum, the IC system that the utility model provided is to utilize customized memory control unit, to be applicable to application processing unit and memory integrated circuits.In addition, the applied logic integrated circuit in the utility model, at least one memory integrated circuits and serial channel control module are to be integrated in the predetermined encapsulation.Therefore, the utility model not only can dwindle the area of IC system, and because the memory control unit of the utility model can be by customized with in response to different application processing unit and memory integrated circuits, so have optimized usefulness, efficient and cost.
The preferred embodiment that the above is merely the utility model is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within the spirit and principle of the utility model, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection domain of the utility model.
Claims (19)
1. IC system comprises:
The applied logic integrated circuit comprises:
Application processing unit; And
Memory control unit is coupled to this application processing unit, and this memory control unit has bus;
At least one memory integrated circuits, each memory integrated circuits comprises:
First channel interface is coupled to this memory control unit;
Memory array is in order to storage data; And
The second channel interface; And
The serial channel control module is coupled to this second channel interface, in order to export this data;
This IC system is characterised in that also and comprises:
This bus is customized being applicable to this application processing unit and this memory integrated circuits, and this applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation.
2. IC system comprises:
At least one memory integrated circuits, each memory integrated circuits comprises:
First channel interface;
Memory array is in order to storage data; And
The second channel interface;
The serial channel control module is coupled to this second channel interface, in order to export this data; And
This IC system is characterised in that also and comprises:
The applied logic integrated circuit comprises:
Application processing unit; And
Memory control unit is coupled to this application processing unit and this first channel interface, and wherein this memory control unit has bus, and this memory control unit is in order to support variable voltage, variable frequency or variable bus bit wide;
Wherein this applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation.
3. IC system comprises:
At least one memory integrated circuits, each memory integrated circuits comprises:
First channel interface;
Memory array is in order to storage data; And
The second channel interface;
The serial channel control module is coupled to this second channel interface, in order to export this data; And
This IC system is characterised in that also and comprises:
The applied logic integrated circuit comprises:
Application processing unit; And
Memory control unit is coupled to this application processing unit and this first channel interface, and wherein this memory control unit has bus, and this memory control unit is in order to support variable voltage, variable frequency or variable bus bit wide;
Wherein this bus is customized being applicable to this application processing unit and this memory integrated circuits, and
This applied logic integrated circuit, this at least one memory integrated circuits and this serial channel control module are to be integrated in predetermined encapsulation.
4. like claim 1,2 or 3 described IC systems, it is characterized in that this memory integrated circuits is to be true good chip.
5. like claim 1,2 or 3 described IC systems, it is characterized in that this predetermined encapsulation is for encapsulating interior encapsulation, encapsulation one on top of another or system in package.
6. like claim 2 or 3 described IC systems, it is characterized in that when this memory array is during for low-power second generation double data rate SDRAM, this variable voltage is between 0V-0.6V.
7. like claim 2 or 3 described IC systems, it is characterized in that when this memory control unit data signal and position signalling, this variable voltage is between 0.3V-0.9V.
8. like claim 2 or 3 described IC systems, it is characterized in that this variable frequency is the power consumption in order to this memory control unit of optimization.
9. like claim 2 or 3 described IC systems, it is characterized in that, also comprise:
Buffer is in order to store this variable voltage, this variable frequency or this variable bus bit wide that this memory control unit can be supported.
10. like claim 1,2 or 3 described IC systems; It is characterized in that; A plurality of these memory integrated circuits are to integrate through the salient point array to become a memory integrated circuits, and the bus bit wide of the memory integrated circuits of wherein integrating is greater than the bus bit wide of single memory integrated circuits.
11. like claim 1,2 or 3 described IC systems, it is characterized in that,
This application processing unit produces looking deeply of object in order to according to the picture signal that produces from least one camera;
This memory array produces from the picture signal of this at least one camera and looking deeply of this object in order to store; And
This serial channel control module is dark in order to export looking of this object.
12. IC system as claimed in claim 11 is characterized in that, this applied logic integrated circuit also comprises:
The applied logic integrated circuit interface is coupled to this application processing unit and this memory control unit, in order to receive the picture signal of this generation from least one camera.
13. IC system as claimed in claim 11 is characterized in that, this serial channel control module is that looking of this object of output is deep to another system in package integrated circuit or the direct encapsulated circuit of chip.
14., it is characterized in that this memory control unit is to be parallel memory control unit, and this first channel interface is for supporting the parallel channel interface of this parallel memory control unit like claim 1,2 or 3 described IC systems.
15., it is characterized in that this memory control unit is to be the serial memory control unit like claim 1,2 or 3 described IC systems, and this first channel interface is for supporting the serial channel interface of this serial memory control unit.
16., it is characterized in that this application processing unit is to be 2D capturing images unit or 3D rendering acquisition unit like claim 1,2 or 3 described IC systems.
17., it is characterized in that this second channel interface is to be the serial channel interface like claim 1,2 or 3 described IC systems.
18., it is characterized in that this serial channel control module is to be universal serial bus 3.0 control modules, serial advanced technology attachment control module or high-speed peripheral device interconnecting interface control unit like claim 1,2 or 3 described IC systems.
19., it is characterized in that this memory control unit is through the manufacturing of direct silicon wafer puncturing technique like claim 1,2 or 3 described IC systems.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161464128P | 2011-02-26 | 2011-02-26 | |
| US61/464,128 | 2011-02-26 | ||
| US201161516352P | 2011-04-01 | 2011-04-01 | |
| US61/516,352 | 2011-04-01 |
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| CN202534359U true CN202534359U (en) | 2012-11-14 |
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| CN2012200654863U Expired - Fee Related CN202534359U (en) | 2011-02-26 | 2012-02-27 | Integrated circuit system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022135558A1 (en) * | 2020-12-24 | 2022-06-30 | 华为技术有限公司 | Memory module and memory bus signal processing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022135558A1 (en) * | 2020-12-24 | 2022-06-30 | 华为技术有限公司 | Memory module and memory bus signal processing method |
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Effective date of registration: 20160329 Address after: Taipei City, Taiwan, China Patentee after: EYS 3D CO., LTD. Address before: Hsinchu City, Taiwan, China Patentee before: Etron Technology, Inc. |
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