CN202494982U - Memory power-saving system - Google Patents

Abstract

The utility model provides a memory power-saving system, which includes several memory modules, programmable devices, a reset signal decoding circuit, a processing module and a power-off decoding circuit, wherein the programmable device is used to input the total reset signal; The reset signal decoding circuit is electrically connected to the memory modules respectively and decomposes the total reset signal into sub-reset signals corresponding to each memory module, and the sub-reset signals include power-saving mode reset signals and non-power-saving mode Reset signal; the processing module is electrically connected to the reset signal decoding circuit, and the processing module moves the data on all memory modules to the memory module corresponding to the non-power-saving mode reset signal according to the reset signal; the power is turned off The decoding circuit is electrically connected to the power supply, the programmable device, and the memory module, and the power-off decoding circuit disconnects the circuit of the memory module corresponding to the power-saving mode reset signal according to the total reset signal and the off-peak period, thereby effectively Reduce power consumption caused by memory modules.

Description

memory power saving system

【Technical field】

The utility model relates to a memory power saving system, in particular to a memory power saving system which effectively reduces power consumption.

【Background technique】

In order to save power during off-peak hours of the system, some processors can reduce the frequency during off-peak hours to reduce power consumption, and the system can still operate normally at this time. Some processors also incorporate an "automatic memory throttling" feature. However, during off-peak hours, memory usage becomes low. Even if the system has the functions of "processor frequency reduction" and "automatic memory adjustment", all memory modules in the server will continue to be powered, resulting in unnecessary waste of power.

Processor power consumption ranges from about 45 to 200W; in a server with eight 1Gb dual in-line memory modules (DIMMs), the DIMMs have a power budget of 80W. Therefore, for a large server with up to 64 DIMMs, the result is likely to be "the power consumption of the memory module is higher than that of the processor", so in server applications, if the memory can be effectively reduced during off-peak hours The resulting power consumption will save considerable electricity and electricity bills for enterprises using servers. the

【Content of utility model】

The main purpose of the utility model is to provide a memory power saving system which effectively reduces power consumption.

The utility model provides a memory power-saving system, which includes several memory modules, programmable devices, a reset signal decoding circuit, a processing module and a power-off decoding circuit, wherein the programmable device is used to input the total reset signal; The reset signal decoding circuit is respectively electrically connected to the memory modules and decomposes the total reset signal into sub-reset signals corresponding to each memory module, wherein the sub-reset signals include power-saving mode reset signals and non-power-saving reset signals. Mode reset signal; the processing module is electrically connected to the reset signal decoding circuit, and the processing module moves the data on all memory modules to the memory module corresponding to the non-power-saving mode reset signal according to the sub-reset signal; the power supply The power-off decoding circuit is electrically connected to the power supply, the programmable device and the memory module, and the power-off decoding circuit disconnects the circuit of the memory module corresponding to the power-saving mode reset signal according to the total reset signal and the off-peak period. the

In particular, the programmable device is FPGA. the

Compared with the prior art, the utility model utilizes the power off decoding circuit to cut off the circuit of the memory module corresponding to the reset signal of the power saving mode during the off-peak period, effectively reducing the power consumption caused by the memory module and saving Substantial electricity with electricity bills. the

In order to have a further understanding of the purpose, structural features and functions of the utility model, the detailed description is as follows in conjunction with the accompanying drawings:

【Description of drawings】

FIG. 1 is a schematic block diagram of the memory power saving system of the present invention.

【Detailed ways】

Please refer to Fig. 1, the utility model provides a memory power saving system, which includes several memory modules 10, programmable devices 20, reset signal decoding circuit 30, processing module 40 and power off decoding circuit 50, wherein , the programmable device 20 is used to input the total reset signal, and there are two input methods of the total reset signal, one method is that the server manager manually inputs the total reset signal according to the size of the memory usage, and the other method is the memory The management program automatically inputs the general reset signal according to the size of the memory usage; in this embodiment, the programmable device is FPGA. The reset signal decoding circuit 30 is electrically connected to the memory modules 10 respectively and decomposes the total reset signal into sub-reset signals corresponding to each memory module 10, wherein the sub-reset signals include power-saving mode reset signals and Non-power-saving mode reset signal; the processing module 40 is electrically connected to the reset signal decoding circuit, and the processing module 40 moves all the data on the memory module 10 to the non-power-saving mode reset signal according to the sub-reset signal The corresponding memory module 10; the power off decoding circuit 50 is electrically connected to the power supply 60, the programmable device 20 and the memory module 10, and the power off decoding circuit 50 disconnects the power saving mode reset according to the total reset signal and off-peak time Set the circuit of the memory module 10 corresponding to the signal.

In the method of resetting the memory described in block 5 of the flow chart, the power required by the memory module is re-supplied first. After the power is supplied, after a period of time, the reset signal decoding circuit 30 will re-send the sub-reset signal For the re-powered memory module, after the reset is completed, the memory management program will rearrange the memory configuration and notify the system to modify the memory usage. the

The utility model utilizes the power-off decoding circuit 50 to disconnect the circuit of the memory module 10 corresponding to the reset signal of the power-saving mode during the off-peak period, effectively reducing the power consumption caused by the memory module 10, and saving considerable power and energy. electricity bills. the

The above is only a specific implementation of the utility model, but the scope of protection of the utility model is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the utility model. It should be covered within the scope of protection of utility models. Therefore, the protection scope of the utility model shall be determined by the protection scope of the claims. the

Claims (2)

1. internal memory electricity-saving system is characterized in that comprising:

Some memory modules;

Programming device, it is in order to import total replacement signal;

The reset signal decoding scheme electrically connects said memory modules respectively and the signal decomposition of will always resetting becomes pairing minute reset signal of each memory modules, wherein, divides reset signal to comprise battery saving mode reset signal and non-battery saving mode reset signal;

Processing module, it electrically connects reset signal decoding scheme, and said processing module according to minute reset signal with the data-moving on all memory modules to the pairing memory modules of non-battery saving mode reset signal;

The power-off decoding scheme, it electrically connects power supply, programming device and memory modules, and said power-off decoding scheme breaks off the loop of the pairing memory modules of battery saving mode reset signal according to total replacement signal and from the peak period.

2. internal memory electricity-saving system according to claim 1 is characterized in that: said programming device is FPGA.

Images