CN202394962U - Semiconductor packaging structure with stacked chips - Google Patents

Semiconductor packaging structure with stacked chips Download PDF

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Publication number
CN202394962U
CN202394962U CN201120533681.XU CN201120533681U CN202394962U CN 202394962 U CN202394962 U CN 202394962U CN 201120533681 U CN201120533681 U CN 201120533681U CN 202394962 U CN202394962 U CN 202394962U
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CN
China
Prior art keywords
chip
wall
semiconductor package
substrate
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN201120533681.XU
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Chinese (zh)
Inventor
黄东鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Filing date
Publication date
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Priority to CN201120533681.XU priority Critical patent/CN202394962U/en
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Publication of CN202394962U publication Critical patent/CN202394962U/en
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model provides a semiconductor packaging structure with stacked chips. The semiconductor packaging structure comprises: a substrate, a first chip, multiple second chips and at least one spacer layer. The first chip is arranged on the substrate; the multiple chips are stacked on the first chips; and the at least one spacer layer is arranged between at least two neighboring second chips, and the spacer layer can increase the heat dissipation of two chips and solve the heat dissipation problem of the conventional chip stacked structure.

Description

Semiconductor package with stacked chips
Technical field
The utility model relates to a kind of semiconductor package, particularly relates to a kind of semiconductor package with stacked chips.
Background technology
In semiconductor production process, integrated circuit encapsulation (IC package) is one of important step of processing procedure, in order to protection IC chip with provide outside and electrically connect, to prevent the destruction of carrying and getting external force in the process of putting or environmental factor.In addition, integrated circuit package also needs to be combined into a system with passive components such as resistance, electric capacity, the function that competence exertion is set, and Electronic Packaging (Electronic Packaging) promptly is protection and the organizational structure that is used to set up integrated circuit package.Generally speaking, the beginning is carried out Electronic Packaging after the IC chip processing procedure, comprise that cohering of IC chip is fixing, circuit is online, sealing structure, with the engaging of circuit board, system in combination, all processing procedures between the product completion.
In electronic installation now, a plurality of chips often need be set in the single electronic installation to carry out simultaneously multiple function, to satisfy the demand of modern for electronic installation.Yet if a plurality of chip system is formed at different encapsulating structures respectively, the institute that can increase encapsulating structure takes up space.Therefore, stacked semiconductor chips is generally used to increase the semiconductor mechanism of packaging density.
For instance, please with reference to shown in Figure 1, it discloses a kind of encapsulating structure of existing stacked chips, and it comprises substrate 101, process chip 102 and a plurality of memory chip 103.Process chip 102 is to be arranged on the substrate 101, and (under-fill) material 104 is filled in the tool bottom between substrate 101 and the process chip 102, and memory chip 103 is to be stacked on the process chip 102 through adhesion layer.
Yet in the encapsulating structure of above-mentioned existing stacked chips, the heat between a plurality of memory chips 103 is difficult for scattering and disappearing to outside, causes the radiating efficiency of this stacked chips structure not good, and influences the usefulness performance of assembly easily.
So, be necessary to provide a kind of semiconductor package, to solve the existing in prior technology problem.
The utility model content
The utility model provides a kind of semiconductor package, to solve the existing existing heat dissipation problem of stacked chips structure.
The main purpose of the utility model is to provide a kind of semiconductor package, and said semiconductor package comprises:
One substrate;
One first chip is arranged on the said substrate;
A plurality of second chips pile up and are arranged on said first chip; And
At least one wall is arranged between two adjacent said second chips at least.
In an embodiment of the utility model, said first chip is processor chips.
In an embodiment of the utility model; Said substrate comprises a plurality of metal couplings and a plurality of tin ball; Said metal coupling is a upper surface that is formed at said substrate; Be used to be electrically connected at one of said first chip layer that reroutes, said tin ball is a lower surface that is arranged at said substrate, is used for as the signal I/O assembly of said substrate to the outside.
In an embodiment of the utility model, has a bottom packed layer between said first chip and the said substrate.
In an embodiment of the utility model, said second chip is a plurality of memory chips.
In an embodiment of the utility model, said wall is to be arranged between per two adjacent said second chips.
In an embodiment of the utility model, said wall is to be arranged at said centre position of piling up a stacked structure of second chip respectively.
In an embodiment of the utility model, said wall is to be arranged at the top of a said stacked structure that piles up second chip and two interlayer position of below respectively.
In an embodiment of the utility model, said wall is the semiconductor material layer, and said wall is provided with a plurality of wall perforation, and the inboard of said wall perforation respectively is formed with an insulation madial wall.
In an embodiment of the utility model, said wall is an insulation material layer, and said wall is provided with a plurality of wall perforation.
Stacked chip structure compared to existing thermal problems that exist, the utility model structure of a semiconductor package at least one spacer layer may be provided on at least two adjacent second chip or between between the first chip and the second chip, in order to improve thermal conductivity between the stacked chips efficiency, and increase the overall package structure and the thermal efficiency of heat dissipation area, thus ensuring the components within the structure of a semiconductor package performance.
For letting the foregoing of the utility model can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 shows the profile according to a kind of encapsulating structure of existing stacked chips;
Fig. 2 shows the profile according to the semiconductor package of first embodiment of the utility model;
Fig. 3 shows the exploded view according to the semiconductor package of first embodiment of the utility model;
Fig. 4 shows the profile according to the semiconductor package of second embodiment of the utility model; And
Fig. 5 shows the profile according to the semiconductor package of the 3rd embodiment of the utility model.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to illustration the utility model in order to the specific embodiment of implementing.The direction term that the utility model is mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to restriction the utility model.
In the drawings, the unit of structural similarity is to represent with same numeral.
Please with reference to Fig. 2 and Fig. 3, Fig. 2 shows the profile according to the semiconductor package of an embodiment of the utility model, and Fig. 3 shows the exploded view according to the semiconductor package of an embodiment of the utility model.The semiconductor package 100 of the utility model comprises first chip 110, a plurality of second chip 120, substrate 130, wall 140, adhesion layer 150 and packing colloid 160.First chip 110 is to be arranged on the substrate 130; Second chip 120 is to be stacked on first chip 110; Wall 140 is to be arranged between second chip 120; Adhesion layer 150 is to be formed between second chip 120 and the wall 140, is used to engage second chip 120 and wall 140, and packing colloid 160 is to be used for first chip 110 and second chip 120.
As shown in Figure 2, first chip 110 of present embodiment for example is processor (Processer) chip.First chip 110 can be formed with the insulating barrier and the metallic circuit layer of several layers of alternated, with common formation reroute layer (redistribution layer, RDL) 111 lower surface in first chip 110 (being active surface), and regard to substrate 130.In addition; First chip 110 can be provided with first perforation 112; First perforation 112 runs through first chip 110, and in the hole, electroplates or be filled with conducting metal (like copper, silver, gold or aluminium etc.), to be used to electrically connect layer 111 and second chip 120 that reroute of first chip 110.
As shown in Figure 2, this substrate 130 of present embodiment can be BGA (Ball Grid Array, multilayer printed board BGA), and can be provided with a plurality of metal couplings (Bump) 131 and a plurality of tin ball (Solder Ball) 132.The material of metal coupling 131 and tin ball 132 for example is: tin, aluminium, nickel, silver, copper, indium, lead or its alloy.Metal coupling 131 can sharp wire mark be formed at the upper surface of substrate 130, is used to be electrically connected at the layer 111 that reroutes of first chip 110.Tin ball 132 for example soldered ball ball attachment machines capable of using (not illustrating) are arranged at the lower surface of substrate 130, are used for the signal I/O assembly as 130 pairs of outsides of said substrate.
As shown in Figure 2, when first chip 110 being set, at first, can form the upper surface of metal coupling 131 in substrate 130 in 130 last times of substrate.Then, the upper surface at substrate 130 is coated with bottom filling (under-fill) layer 133.Then, this bottom packed layer 133 is heated, make bottom packed layer 133 be molten condition.Then, the layer 111 that reroutes that engages first chip 110 is in the metal coupling 131 of substrate 130.At this moment, the bottom packed layer 133 of fusion can be filled in the space between first chip 110 and the substrate 130.Then, the bottom packed layer 133 after the curing can firm first chip 110 with substrate 130 between engage.
Perhaps, in another embodiment, at first, can form the upper surface of metal coupling 131 in the layer 111 that reroutes.Then, layer 111 the metal coupling 131 that reroute that engages first chip 110 is in substrate 130.Then, be coated with bottom filling (under-fill) layer 133 at the upper surface of substrate 130 and the space of rerouting between the layer 111.Then, this bottom packed layer 133 is heated, make bottom packed layer 133 after the curing can firm first chip 110 with substrate 130 between engage.
As shown in Figure 2, second chip 120 of present embodiment can be memory chip (memory chip), for example quickflashing (Flash) memory chip or DRAM (Dynamic Random Access Memory, DRAM) chip.These second chips 120 are to be arranged on first chip 110 with piling up each other; And be provided with second the perforation 121; Second perforation 121 runs through second chip 120, and in the hole, electroplates or be filled with conducting metal (like copper, silver, gold or aluminium etc.), therefore can be used for mutual electric connection.The active surface of these second chips 120 can be all down or all up, or partly reach down partly up.
As shown in Figure 2, the wall of present embodiment (thermal spacer) the 140th is arranged between per two adjacent second chips 120, is used to improve the radiating efficiency between second chip 120.Wall 140 can be engaged between second chip 120 through adhesion layer 150, and the material of wall 140 is preferably semi-conducting material or the insulating material with good thermal conductivity.Wall 140 is provided with wall perforation 141, is used to be electrically connected between second chip 120.When the material of wall 140 is when having the semi-conducting material of good thermal conductivity, for example silicon or similar material, the inboard of wall perforation 141 can be formed with insulation madial wall 142, to prevent electrical short circuit.When the material of wall 140 is when having the insulating material of good thermal conductivity, aluminium nitride for example, then the making of wall perforation 141 can be omitted this insulation madial wall 142.
As shown in Figure 2, the adhesion layer 150 of present embodiment can be coated between second chip 120 and the wall 140, becomes a stacked structure to engage a plurality of second chips 120 and wall 140.The same horizontal level of adhesion layer 150 is provided with projection 151, and projection 151 for example is tin projection or golden projection, and it is used to be electrically connected between second chip 120 and the wall 140.Preferably; The diameter of the projection 151 of adhesion layer 150 is the weld pad diameters greater than second perforation 121 of second chip 120; And greater than the weld pad diameter of the wall of wall 140 perforation 141; Be positioned at the weld pad at second perforation, 121 two ends of second chip 120 with 151 pairs of projections that make things convenient for adhesion layer 150, and to the bore a hole weld pad at 141 two ends of the wall that is positioned at wall 140.
As shown in Figure 2, the packing colloid 160 of present embodiment can be used for coating protection first chip 110 and second chip 120.The insulating substrate of said packing colloid 160 can be epoxy resin (epoxy), PMMA, Merlon (Polycarbonate) or silica gel, and it avoids receiving the influence of ambient temperature, humidity or atmosphere in order to the inner assembly of protection packaging structure.
Therefore, the semiconductor package 100 of present embodiment can be provided with wall 140 between second chip 120 that piles up.Because the thermal conductivity of wall 140 can be superior to second chip 120, thereby can increase whole area of dissipation and radiating efficiency, to guarantee the assembly property in the encapsulating structure 100.
Please with reference to Fig. 4, it shows the profile according to the semiconductor package of second embodiment of the utility model.The semiconductor package 200 of second embodiment comprises first chip 210, a plurality of second chip 221,222,223 and 224, substrate 230, wall 240 and adhesion layer 250.First chip 210 is to be arranged on the substrate 230, and second chip 221,222,223 and 224 is to be stacked on first chip 210.Wall 240 is to be arranged between second chip 222 and 223, is used to improve second chip 221,222 and second chip 223, the radiating effect between 224.Adhesion layer 250 be used to be engaged in second chip 221, between 222, be engaged in wall 240 and second chip 222, between 223, and be engaged between second chip 223 and 224.Compared to first embodiment; The wall 240 of the semiconductor package 200 of second embodiment can only be arranged at the centre position (222-223) of the stacked structure of second chip after piling up; To save the material cost of wall 240; And gain dissipation concentrates on the inner most heat of second chip, the radiating efficiency of raising overall package structure 200.
Please with reference to Fig. 5, it shows the profile according to the semiconductor package of the 3rd embodiment of the utility model.The semiconductor package 300 of the 3rd embodiment comprises first chip 310, a plurality of second chip 321,322,323 and 324, substrate 330, wall 340 and adhesion layer 350.First chip 310 is to be arranged on the substrate 330, and second chip 321,322,323 and 324 is to be stacked on first chip 310.Wall 340 is to be arranged between second chip 321 and 322 and between second chip 323 and 324, is used to improve second chip 321, between 322 and the radiating effect between second chip 323 and 324.Adhesion layer 350 is to be used to be engaged between second chip 321,322 and the wall 340, to be engaged between second chip 322 and 323, and be engaged in wall 340 and second chip 323, between 324.Compared to first embodiment; The top of the stacked body of second chip after the wall 340 of the semiconductor package 300 of the 3rd embodiment can be arranged at and pile up and two interlayer position (between second chip 321 and 322 and between second chip 323 and 324) of below; Towards the dissipation of both sides up and down of stacked chips, thereby can improve the radiating efficiency of overall package structure 300 with the gain heat.
From the above; The semiconductor package of the utility model can be provided with at least one wall between at least two adjacent second chips; To guarantee that the heat between the stacked chips can be discharged to the outside effectively; And can increase the area of dissipation and the radiating efficiency of overall package structure, thereby can guarantee the assembly property in the semiconductor package.
In sum; Though the utility model discloses as above with preferred embodiment; But above-mentioned preferred embodiment is not that those of ordinary skill in the art is in spirit that does not break away from the utility model and scope in order to restriction the utility model; All can do various changes and retouching, so the protection range of the utility model is as the criterion with the scope that claim defines.

Claims (10)

1. semiconductor package, it is characterized in that: said semiconductor package comprises:
One substrate;
One first chip is arranged on the said substrate;
A plurality of second chips pile up and are arranged on said first chip; And
At least one wall is arranged between two adjacent said second chips at least.
2. semiconductor package according to claim 1 is characterized in that: said first chip is processor chips.
3. semiconductor package according to claim 1; It is characterized in that: said substrate comprises a plurality of metal couplings and a plurality of tin ball; Said metal coupling is a upper surface that is formed at said substrate; Be used to be electrically connected at one of said first chip layer that reroutes, said tin ball is a lower surface that is arranged at said substrate, is used for as the signal I/O assembly of said substrate to the outside.
4. semiconductor package according to claim 1 is characterized in that: have a bottom packed layer between said first chip and the said substrate.
5. semiconductor package according to claim 1 is characterized in that: said second chip is a plurality of memory chips.
6. semiconductor package according to claim 1 is characterized in that: said wall is to be arranged between per two adjacent said first chips and second chip.
7. semiconductor package according to claim 1 is characterized in that: said wall is to be arranged at said centre position of piling up a stacked structure of second chip respectively.
8. semiconductor package according to claim 1 is characterized in that: said wall is to be arranged at the top of a said stacked structure that piles up second chip and two interlayer position of below respectively.
9. semiconductor package according to claim 1 is characterized in that: said wall is the semiconductor material layer, and said wall is provided with a plurality of wall perforation, and the inboard of said wall perforation respectively is formed with an insulation madial wall.
10. semiconductor package according to claim 1 is characterized in that: said wall is an insulation material layer, and said wall is provided with a plurality of wall perforation.
CN201120533681.XU 2011-12-19 2011-12-19 Semiconductor packaging structure with stacked chips Expired - Lifetime CN202394962U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201120533681.XU CN202394962U (en) 2011-12-19 2011-12-19 Semiconductor packaging structure with stacked chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201120533681.XU CN202394962U (en) 2011-12-19 2011-12-19 Semiconductor packaging structure with stacked chips

Publications (1)

Publication Number Publication Date
CN202394962U true CN202394962U (en) 2012-08-22

Family

ID=46669867

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201120533681.XU Expired - Lifetime CN202394962U (en) 2011-12-19 2011-12-19 Semiconductor packaging structure with stacked chips

Country Status (1)

Country Link
CN (1) CN202394962U (en)

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C14 Grant of patent or utility model
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CX01 Expiry of patent term

Granted publication date: 20120822

CX01 Expiry of patent term