CN202394926U - 多基岛埋入多圈引脚封装结构 - Google Patents

多基岛埋入多圈引脚封装结构 Download PDF

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CN202394926U
CN202394926U CN2011204799299U CN201120479929U CN202394926U CN 202394926 U CN202394926 U CN 202394926U CN 2011204799299 U CN2011204799299 U CN 2011204799299U CN 201120479929 U CN201120479929 U CN 201120479929U CN 202394926 U CN202394926 U CN 202394926U
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chip
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interior
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王新潮
梁志忠
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

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Abstract

本实用新型涉及一种多基岛埋入多圈引脚封装结构,它包括外引脚(1),所述外引脚(1)设置有多圈,所述外引脚(1)正面通过多层电镀方式形成内引脚(3),所述内引脚(3)与内引脚(3)之间通过多层电镀方式形成内基岛(2),所述内基岛(2)有多个,所述内基岛(2)正面设置有芯片(4),所述芯片(4)正面与内引脚(3)正面之间用金属线(5)连接,所述外引脚(1)的背面设置有第二金属层(9)。本实用新型的有益效果是:它省去了背面的耐高温胶膜,降低了封装成本,可选择的产品种类广,金属线键合的质量与产品可靠度的稳定性好,塑封体与金属脚的束缚能力大,实现了内引脚的高密度能力。

Description

多基岛埋入多圈引脚封装结构
技术领域
本实用新型涉及一种多基岛埋入多圈引脚封装结构,属于半导体封装技术领域。
背景技术
传统的引线框结构主要有两种:
第一种:采用金属基板进行化学蚀刻及电镀后,在金属基板的背面贴上一层耐高温的胶膜形成可以进行封装过程的引线框载体(如图2所示);
第二种:采用首先在金属基板的背面进行化学半蚀刻,再将前述已经过化学半蚀刻的区域进行塑封料的包封,之后将金属基板的正面进行内引脚的化学蚀刻,完成后再进行引线框内引脚表面的电镀,即完成引线框的制作(如图4所示)。
而上述两种引线框在封装过程中存在了以下不足点:
第一种:
1、此种的引线框架因背面必须要贴上一层昂贵可抗高温的胶膜,所以直接增加了高昂的成本;
2、也因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜,所以在封装过程中的装片工艺只能使用导电或是不导电的粘結物質,而完全不能采用共晶工艺以及软焊料的工艺进行装片,所以可选择的产品种类就有较大的局限性;
3、又因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜,而在封装过程中的金属线键合工艺中,因为此可抗高温的胶膜是软性材质,所以造成了金属线键合参数的不稳定,严重的影响了金属线键合的质量及产品可靠度的稳定性;
4、再因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜,而在封装过程中的塑封工艺过程,因为塑封时的注胶压力很容易造成引线框架与胶膜之间渗入塑封料,而将原本应属金属脚是导电的型态因为渗入了塑封料反而变成了绝缘脚(如图3所示)。
第二种:
1、因为分别进行了二次的蚀刻作业,所以多增加了工序作业的成本;
2、引线框的组成是金属物质加环氧树脂物质(塑封料)所以在高温下容易因为不同物质的膨胀与收缩应力的不相同,产生引线框翘曲问题;
3、也因为引线框的翘曲直接影响到封装工序中的装置芯片的精准度与引线框传送过程的顺畅从而影响生产良率;
4、也因为引线框的翘曲直接影响到封装工序中的金属线键合的对位精度与引线框传送过程的顺畅从而影响生产良率;
5、因为引线框正面的内引脚是采用蚀刻的技术,所以蚀刻内引脚的脚宽必须大于100μm,而内引脚与内引脚的间隙也必须大于100μm,所以较难做到内引脚的高密度能力。
发明内容
本实用新型的目的在于克服上述不足,提供一种多基岛埋入多圈引脚封装结构,它省去了背面的耐高温胶膜,降低了封装成本,可选择的产品种类广,金属线键合的质量与产品可靠度的稳定性好,塑封体与金属脚的束缚能力大,实现了内引脚的高密度能力。 
本实用新型的目的是这样实现的:一种多基岛埋入多圈引脚封装结构,其特点是:它包括外引脚,所述外引脚设置有多圈,所述外引脚正面通过多层电镀方式形成内引脚,所述内引脚与内引脚之间通过多层电镀方式形成内基岛,所述内基岛有多个,所述内基岛正面设置有芯片,所述芯片正面与内引脚正面之间以及芯片正面与芯片正面之间用金属线连接,所述内基岛和内引脚上部以及芯片和金属线外包封有塑封料,所述外引脚外围的区域以及外引脚与外引脚之间的区域嵌置有填缝剂,且外引脚的背面露出填缝剂外,在露出填缝剂外的外引脚的背面设置有第二金属层。
所述第一金属层可以采用镍、铜、镍、钯、金五层金属层或镍、铜、银三层金属层,或者其他类似结构。以镍、铜、镍、钯、金五层金属层为例,其中第一层镍层主要起到抗蚀刻阻挡层的作用,而中间的铜层、镍层和钯层主要起结合增高的作用,最外层的金层主要起到与金属线键合的作用。
所述第二金属层的成分根据不同的芯片的功能可以采用金镍金、金镍铜镍金、镍钯金、金镍钯金、镍金、银或锡等。
与现有技术相比,本实用新型的有益效果是:
1、此种引线框的背面不需贴上一层昂贵的可抗高温的胶膜,所以直接降低了高昂的成本;
2、也因为此种引线框的背面不需要贴上一层可抗高温的胶膜,所以在封装过程中的工艺除了能使用导电或是不导电的粘結物質外,还能采用共晶工艺以及软焊料的工艺进行装片,所以可选择的种类较广;
3、又因为此种的引线框的背面不需要贴上一层可抗高温的胶膜,确保了金属线键合参数的稳定性,保证了金属线键合的质量和产品的可靠度的稳定性;
4、再因为此种的引线框的背面不需要贴上一层可抗高温的胶膜,因而在封装的工艺过程中完全不会造成引线框与胶膜之间渗入塑封料;
5、由于正面采用了细线电镀的方法,所以正面的引脚宽度最小可以达到25μm,以及内引脚与内引脚之间的距离最小达到25μm,充分地体现出引线框内引脚的高密度能力;
6、由于应用了正面内引脚的电镀方式与背面蚀刻技术,所以能够将引线框正面的引脚尽可能的延伸到基岛的旁边,促使芯片与引脚距离大幅的缩短,如此金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);
7、也因为金属线的缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算更为突出),由于金属线的长度变短了,所以在金属线所存在的寄生电阻、寄生电容与寄生电感对信号的干扰也大幅度的降低;
8、因运用了内引脚的电镀延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小;
9、因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降,由于材料用量的减少,也大幅度地减少了废弃物等环保问题困扰。
附图说明
图1为本实用新型一种多基岛埋入多圈引脚封装结构示意图。
图2为以往四面无引脚引线框背面贴上耐高温胶膜的示意图。
图3为以往背面贴上耐高温胶膜的四面无引脚引线框封装时溢料的示意图。
图4为以往预包封双面蚀刻引线框的结构示意图。
其中:
外引脚1
内基岛2
内引脚3
芯片4
金属线5
塑封料6
填缝剂7
导电或不导电粘结物质8
第二金属层9。
具体实施方式
参见图1, 本实用新型一种多基岛埋入多圈引脚封装结构,它包括外引脚1,所述外引脚1设置有多圈,所述外引脚1正面通过多层电镀方式形成内引脚3,所述内引脚3与内引脚3之间通过多层电镀方式形成内基岛2,所述内基岛2有多个,所述内基岛2和内引脚3统称为第一金属层,所述内基岛2正面通过导电或不导电粘结物质8设置有芯片4,所述芯片4正面与内引脚3正面之间以及芯片4正面与芯片4正面之间用金属线5连接,所述内基岛2和内引脚3上部以及芯片4和金属线5外包封有塑封料6,所述外引脚1外围的区域以及外引脚1与外引脚1之间的区域嵌置有填缝剂7,且外引脚1的背面露出填缝剂7外,在露出填缝剂7外的外引脚1的背面设置有第二金属层9。
所述内引脚3与内引脚3之间也可不通过多层电镀方式形成内基岛2,若内引脚3与内引脚3之间不形成内基岛2,此时芯片4直接通过导电或不导电粘结物质8设置于内引脚3与内引脚3之间的填缝剂7正面。

Claims (1)

1.一种多基岛埋入多圈引脚封装结构,其特征在于:它包括外引脚(1),所述外引脚(1)设置有多圈,所述外引脚(1)正面通过多层电镀方式形成内引脚(3),所述内引脚(3)与内引脚(3)之间通过多层电镀方式形成内基岛(2),所述内基岛(2)有多个,所述内基岛(2)正面设置有芯片(4),所述芯片(4)正面与内引脚(3)正面之间以及芯片(4)正面与芯片(4)正面之间用金属线(5)连接,所述内基岛(2)和内引脚(3)上部以及芯片(4)和金属线(5)外包封有塑封料(6),所述外引脚(1)外围的区域以及外引脚(1)与外引脚(1)之间的区域嵌置有填缝剂(7),且外引脚(1)的背面露出填缝剂(7)外,在露出填缝剂(7)外的外引脚(1)的背面设置有第二金属层(9)。
CN2011204799299U 2011-11-28 2011-11-28 多基岛埋入多圈引脚封装结构 Expired - Lifetime CN202394926U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103759880A (zh) * 2014-01-27 2014-04-30 中国电子科技集团公司第四十九研究所 一种无引线封装结构及采用无引线封装结构的soi绝压敏感器件
CN103940536A (zh) * 2014-04-25 2014-07-23 中国电子科技集团公司第四十九研究所 一种采用陶瓷金属管壳轴向烧结的压力敏感器件

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103759880A (zh) * 2014-01-27 2014-04-30 中国电子科技集团公司第四十九研究所 一种无引线封装结构及采用无引线封装结构的soi绝压敏感器件
CN103759880B (zh) * 2014-01-27 2016-03-02 中国电子科技集团公司第四十九研究所 一种采用无引线封装结构的soi绝压敏感器件
CN103940536A (zh) * 2014-04-25 2014-07-23 中国电子科技集团公司第四十九研究所 一种采用陶瓷金属管壳轴向烧结的压力敏感器件
CN103940536B (zh) * 2014-04-25 2016-03-02 中国电子科技集团公司第四十九研究所 一种采用陶瓷金属管壳轴向烧结的压力敏感器件

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