CN202385166U - Field programmable gate array (FPGA) technology-based visual target self-adaptive detection controller - Google Patents
Field programmable gate array (FPGA) technology-based visual target self-adaptive detection controller Download PDFInfo
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Abstract
The utility model discloses a field programmable gate array (FPGA) technology-based visual target self-adaptive detection controller, which comprises a charge coupled device (CCD) camera, a video input module, a clock module, a sensor module, a position driving and controlling module and an FPGA video detection controller. The FPGA technology-based visual target self-adaptive detection controller is based on the design of the FPGA chip; the hardware design adopts modular design, so that the hardware is easily updated, and different image detection programs can be downloaded; the FPGA technology-based visual target self-adaptive detection controller can adapt to different working conditions, and has the characteristics of high data processing speed, high integration level, small system size, reliable field work and the like.
Description
Technical field
The utility model belongs to sensation target self-adapting detecting control device, and in particular to a kind of sensation target self-adapting detecting control device based on FPGA technology.
Background technology
With the development of automatic control technology, NI Vision Builder for Automated Inspection has application to the fields such as detection, measurement, positioning and identification and has obtained wide application, the maximum feature detected using image procossing and machine vision technique is to carry out noncontacting measurement, compared with traditional detection method, vision detection technology has the advantages that repeatable strong, noncontact, speed be fast and high precision, therefore machine vision is a kind of method that production process detection field provides degree of accuracy and inexpensive compatibility.
The typical NI Vision Builder for Automated Inspection overwhelming majority is still based on the design of pure software at present, and its NI Vision Builder for Automated Inspection basic structure mainly includes the compositions such as lighting source, image pick-up card, PC processing computers, and corresponding image processing program.Because the detection object of most NI Vision Builder for Automated Inspection is all moving object, the time of system processing and processing speed have compared with strict requirements, and the processing of the image based on PC and analysis software use the software architecture under window platforms, larger is relied on to computing power, the volume for also resulting in NI Vision Builder for Automated Inspection is big, be inconvenient to move.Such as " the high speed melon and fruit quality identification system based on machine vision "（CN1462875）Including image capturing system, optical imaging system and fibre optical sensor, using external signal triggering control IMAQ, double CCD three-dimensional stereoscopic visuals and color image processing, but its image processing program is that, based on Window exploitations, the volume of acquisition system is larger；" traffic flow detection system matched based on the visual vehicle optical feature recognition " system is also based on Window exploitations, and its hardware configuration is made up of luminaire, video input unit, image pick-up card, master control PC, display and triggering device etc..
Utility model content
The purpose of this utility model is that there is provided a kind of real-time is good, data processing speed is fast, small volume, the reliable operation vision self-adapting based on FPGA technology detects controller in view of the shortcomings of the prior art.
The technical solution of the utility model is realized in the following manner：A kind of sensation target self-adapting detecting controller based on FPGA technology, including CCD camera, video input module, clock module, sensor assembly, position driving with control module with, FPGA video detection controllers；
The analog video output signal end of CCD camera and the analog video input signal end of video input module are connected；The video output terminals of video input module are connected with the video pre-processing units input of FPGA video detection controllers, the synchronous control signal end of video input module is connected with the Synchronization Control end of FPGA video detection controllers, and the configuration controlling bus end of video input module is connected with the configuration controlling bus end of FPGA video detection controllers；The control signal end of the target location output unit of FPGA video detection controllers is connected with position driving with the control signal end of control module, the target position signal output bus of the target location output unit of FPGA video detection controllers is connected with position driving with the target position signal input bus of control module, and position driving is connected with the drive signal end of control module and the drive signal end of actuating motor；The target location detection input signal end of FPGA video detection controllers and the target location detection output signal end connection of sensor assembly；The input end of clock of FPGA video detection controllers and the output terminal of clock of clock module are connected；
The data/address bus and address bus of FPGA video detection controllers are connected with FLASH modules, SDRAM module, the data/address bus of SDRAM1 modules and address bus respectively；The SDRAM control output ends of FPGA video detection controllers and the control signal of SDRAM module are connected, and the SDRAM1 control output ends of FPGA video detection controllers are connected with the control signal of SDRAM1 modules；The Flash control output ends of FPGA video detection controllers are connected with the control signal of Flash modules.
The FPGA video detections controller is made up of the logic control element write with Verilog hardware description languages, video pre-processing units, video object detection unit, target location output unit.
The logic control element is made up of clock frequency division module, control module.
The video pre-processing units are made up of Video Controller module, fifo module, filtration module, memory module, SDRAM control modules.
The video object detection unit is made up of Flash control modules, dual port RAM module, light detection module, image detection module, particle group optimizing module.
Described target location output unit is made up of output control module, FIFO-A modules.
The utility model is to be based on field programmable gate array FPGA（Field Programmable Gate Array）The design of chip, uses modular design, it is easy to the upgrading of hardware in hardware design, different image detecting programs can also be downloaded simultaneously, to adapt to different conditions of work, with data processing speed is fast, integrated level is high, the small volume of system, the features such as work on the spot is reliable.
Brief description of the drawings
Fig. 1 is theory diagram of the present utility model.
Fig. 2 is the theory diagram of logic control element in FPGA video detection controllers.
Fig. 3 is the theory diagram of image pre-processing unit in FPGA video detection controllers.
Fig. 4 is the theory diagram of video object detection unit in FPGA video detection controllers.
Fig. 5 is the theory diagram of target location output unit in FPGA video detection controllers.
Embodiment
As shown in figure 1, a kind of sensation target self-adapting detecting controller based on FPGA technology, the device includes CCD camera, video input module, clock module, sensor assembly, position driving and control module and FPGA video detection controllers；Described FPGA video detections controller is made up of the logic control element write with Verilog hardware description languages, video pre-processing units, video object detection unit, target location output unit.
The analog video output signal end of CCD camera and the analog video input signal end of video input module are connected；The video output terminals of video input module are connected with the video pre-processing units input of FPGA video detection controllers, the synchronous control signal end of video input module is connected with the Synchronization Control end of FPGA video detection controllers, and the configuration controlling bus end of video input module is connected with the configuration controlling bus end of FPGA video detection controllers；The control signal end of the target location output unit of FPGA video detection controllers is connected with position driving with the control signal end of control module, the target position signal output bus of the target location output unit of FPGA video detection controllers is connected with position driving with the target position signal input bus of control module, and position driving is connected with the drive signal end of control module and the drive signal end of actuating motor；The target location detection input signal end of FPGA video detection controllers and the target location detection output signal end connection of sensor assembly；The input end of clock of FPGA video detection controllers and the output terminal of clock of clock module are connected；The data/address bus and address bus of FPGA video detection controllers are connected with FLASH modules, SDRAM module, the data/address bus of SDRAM1 modules and address bus respectively；The SDRAM control output ends of FPGA video detection controllers and the control signal of SDRAM module are connected, and the SDRAM1 control output ends of FPGA video detection controllers are connected with the control signal of SDRAM1 modules；The Flash control output ends of FPGA video detection controllers are connected with the control signal of Flash modules.
As shown in Fig. 2 the logic control element of the FPGA video detections controller is made up of clock frequency division module, control module.Wherein：
The input end of clock CLK and clock module of clock frequency division module output terminal of clock CLK connections；Input end of clock CLK1, the input end of clock CLK1 of video pre-processing units of the output terminal of clock CLK1 of clock frequency division module respectively with the control module of logic control element are connected；The output terminal of clock CLK2 of clock frequency division module is connected with the input end of clock CLK2 of video object detection unit；The output terminal of clock CLK3 of clock frequency division module is connected with the input end of clock CLK3 of target location output unit；
The synchronizing field frequency input terminal LLC of control module, level of synchronization input HS, synchronous vertical input VS field frequency output end LLC synchronous with corresponding video input module, level of synchronization output end HS, the VS connections of synchronous vertical output end respectively；The trigger collection signal output part READY and video input module of control module trigger collection signal input part READY connections；The target position signal output control terminal REY of control module is connected with the target position signal output control terminal REY of target location output unit；The image detection request signal control end ReQ of control module is connected with the image detection request signal control end ReQ of the image detection module of video object detection unit；The image detection enabling signal control end JcQD of the image detection module of video object detection unit is connected with the image detection enabling signal control end JcQD of video object detection unit；The image detection of control module completes signal control end SrED and the image detection of image detection module completes the SrED connections of signal control end；The instruction output end DB of control module and the Video Controller module of video pre-processing units command input DB connections；The image storage of control module completes interrupt signal input INT1 and the image storage of video pre-processing units completes the INT1 connections of interrupt signal output end；The target location detection input signal end TRI and sensor assembly of control module target location detection output signal end TRI connections.
As shown in figure 3, the video pre-processing units of the FPGA video detections controller are made up of Video Controller module, fifo module, filtration module, memory module, SDRAM control modules.Wherein：
The command input DB and logic control element of Video Controller module instruction output end DB connections；Configuration bus CB1, CB2 of Video Controller module and configuration bus CB1, CB2 of video input module are connected；The address out bus AD [21 of Video Controller module:0] with the address input bus AD [21 of the filtration module of video pre-processing units:0] connect；The image shift control output end QD of Video Controller module and the fifo module of video pre-processing units image shift control signal QD connections；The input end of clock CLK1 and logic control element of Video Controller module output terminal of clock CLK1 connections；
The analog video input data bus VI [15 of fifo module:0] with the analog video data output bus VI [15 of video input module:0] connect；The video output data bus DB1 [7 of fifo module:0]、DB2[7:0]、DB3[7:0] video input data/address bus DB1 [7 respectively with filtration module:0]、DB2[7:0]、DB3[7:0] connect；The image shift control signal QD of fifo module and the Video Controller module of video pre-processing units image shift control output end QD connections；The input end of clock CLK1 and logic control element of fifo module output terminal of clock CLK1 connections；
The video input data/address bus DB1 [7 of the filtration module of video pre-processing units:0]、DB2[7:0]、DB3[7:0] video output data bus DB1 [7 respectively with fifo module:0]、DB2[7:0]、DB3[7:0] connect；The address input bus AD [21 of filtration module:0] with the address out bus AD [21 of Video Controller module:0] connect；The video output data bus DB [7 of filtration module:0] with the video input data/address bus DB [7 of memory module:0] connect；The address out bus A1 [21 of filtration module:0] with the address input bus A1 [21 of memory module:0] connect；The input end of clock CLK1 and logic control element of filtration module output terminal of clock CLK1 connections；
The video input data/address bus DB [7 of memory module:0] with the video output data bus DB [7 of filtration module:0] connect；The address input bus A1 [21 of memory module:0] with the address out bus A1 [21 of filtration module:0] connect；The video frequency output bus D [7 of memory module:0] with SDRAM module, the data/address bus D [7 of SDRAM1 modules:0] connect；The address out bus A2 [21 of memory module:0] with the address input bus A2 [21 of SDRAM control modules:0] connect；The image storage of memory module completes interrupt signal output end INT1 and the image storage of logic control element completes the INT1 connections of interrupt signal input；The SDRAM Read-write Catrols end R/W-1 of memory module and the SDRAM control modules of video pre-processing units SDRAM Read-write Catrols end R/W-1 connections；The SDRAM pieces of memory module select control end SDCE1 to select control end SDCE1 to be connected with the SDRAM pieces of SDRAM control modules；The input end of clock CLK1 and logic control element of memory module output terminal of clock CLK1 connections；
The address input bus A2 [21 of the SDRAM control modules of video pre-processing units:0] with the address out bus A2 [21 of memory module:0] connect；The SDRAM Read-write Catrols end R/W-1 of the SDRAM control modules of video pre-processing units and the memory module of video pre-processing units SDRAM Read-write Catrols end R/W-1 connections；The SDRAM Read-write Catrols end R/W-2 of the SDRAM control modules of video pre-processing units is connected with the SDRAM Read-write Catrols end R/W-2 of video object detection unit；The SDRAM pieces of the SDRAM control modules of video pre-processing units select the SDRAM pieces of the memory module of control end SDCE1 and video pre-processing units to select control end SDCE1 connections；The SDRAM pieces of the SDRAM control modules of video pre-processing units select control end SDCE2 to select control end SDCE2 to be connected with the SDRAM pieces of video object detection unit；The address out bus A [21 of the SDRAM control modules of video pre-processing units:0] with SDRAM module, the address input bus A [21 of SDRAM1 modules:0] connect；The SDRAM Read-write Catrols end SDR/W2 connections of SDRAM Read-write Catrols end SDR/W1, SDR/W2 of the SDRAM control modules of video pre-processing units respectively with corresponding SDRAM module Read-write Catrol end SDR/W1, SDRAM1 module；The SDRAM pieces of the SDRAM control modules of video pre-processing units select control end CE1, CE2 to select the SDRAM pieces of control end CE1, SDRAM1 module to select control end CE2 connections with corresponding SDRAM module SDRAM pieces respectively；The input end of clock CLK1 and logic control element of the SDRAM control modules of video pre-processing units output terminal of clock CLK1 connections.
As shown in figure 4, the video object detection unit of the FPGA video detections controller is made up of Flash control modules, dual port RAM module, light detection module, image detection module, particle group optimizing module.Wherein：
The address input bus A2 [21 of the Flash control modules of video object detection unit:0] image detection module respectively with video object detection unit, the address out bus A2 [21 of the particle group optimizing module of video object detection unit:0] connect；Flash Read-write Catrols end FR/W1, the Flash Read-write Catrols end FR/W2 of the image detection module of video object detection unit of Flash Read-write Catrols end FR/W1, FR/W2 of the Flash control modules of video object detection unit respectively with the particle group optimizing module of video object detection unit are connected；The Flash pieces of the Flash control modules of video object detection unit select that control end FCE1, FCE2 selects control end FCE1 with the Flash pieces of the particle group optimizing module of video object detection unit respectively, the Flash pieces of the image detection module of video object detection unit select control end FCE2 to be connected；The address out bus A [21 of the Flash control modules of video object detection unit:0] with the address input bus A [21 of Flash modules:0] connect；The Flash Read-write Catrols end FR/W of the Flash control modules of video object detection unit is connected with the Flash Read-write Catrols end FR/W of Flash modules；The Flash pieces of the Flash control modules of video object detection unit select control end FCE to select control end FCE to be connected with the Flash pieces of Flash modules；The input end of clock CLK2 and logic control element of the Flash control modules of video object detection unit output terminal of clock CLK2 connections；
The dual port RAM address input bus AB1 [16 of the dual port RAM module of video object detection unit:0]、AB2[16:0] dual port RAM output bus AB1 [16 respectively with the particle group optimizing module of video object detection unit:0], the dual port RAM output bus AB2 [16 of the image detection module of video object detection unit:0] connect；The dual port RAM data/address bus DB1 [7 of the dual port RAM module of video object detection unit:0]、DB2[7:0] dual port RAM data/address bus DB1 [7 respectively with the particle group optimizing module of video object detection unit:0], the dual port RAM data/address bus DB2 [7 of the image detection module of video object detection unit:0] connect；The dual port RAM piece of the dual port RAM module of video object detection unit selects that control end CE-1, CE-2 selects control end CE-1 with the dual port RAM piece of the particle group optimizing module of video object detection unit respectively, the dual port RAM piece of the image detection module of video object detection unit selects control end CE-2 to be connected；Read-write Catrol end R/W-1, the Read-write Catrol end R/W-2 of the image detection module of video object detection unit of Read-write Catrol end R/W-1, R/W-2 of the dual port RAM module of video object detection unit respectively with the particle group optimizing module of video object detection unit are connected；The input end of clock CLK2 and logic control element of the dual port RAM module of video object detection unit output terminal of clock CLK2 connections；
The data/address bus D [7 of the light detection module of video object detection unit:0] with SDRAM module, the data/address bus D [7 of SDRAM1 modules:0] connect；The image detection request signal control end ReQ and logic control element of the light detection module of video object detection unit image detection request signal control end ReQ connections；The interrupt output end INT2 of the light detection module of video object detection unit is connected with the interrupting input end INT2 of the particle group optimizing module of video object detection unit；The input end of clock CLK2 and logic control element of the light detection module of video object detection unit output terminal of clock CLK2 connections；
The address out bus A2 [21 of the particle group optimizing module of video object detection unit:0] with the address input bus A2 [21 of the Flash control modules of video object detection unit:0] connect；The data/address bus D [7 of the particle group optimizing module of video object detection unit:0] respectively with Flash modules, SDRAM module, SDRAM1 modules data/address bus D [7:0] connect；The dual port RAM address out bus AB1 [16 of the particle group optimizing module of video object detection unit:0] with the dual port RAM address input bus AB1 [16 of dual port RAM module:0] connect；The dual port RAM module data bus DB1 [7 of the particle group optimizing module of video object detection unit:0] with the dual port RAM data/address bus DB1 [7 of dual port RAM module:0] connect；The Flash pieces of the particle group optimizing of video object detection unit select control end FCE1 to select control end FCE1 to be connected with the Flash pieces of Flash control modules；The Flash Read-write Catrols end FR/W1 of the particle group optimizing of video object detection unit is connected with the Flash Read-write Catrols end FR/W1 of Flash control modules；The dual port RAM Read-write Catrol end R/W-3 of the particle group optimizing module of video object detection unit is connected with the dual port RAM Read-write Catrol end R/W-2 of dual port RAM module；The dual port RAM piece of the particle group optimizing module of video object detection unit selects control end CE-1 to select control end CE-1 to be connected with the dual port RAM piece of dual port RAM module；The interrupting input end INT2 of the particle group optimizing module of video object detection unit is connected with the interrupt output end INT2 of the light detection module of video object detection unit；The replacing background interrupt output end INT3 of the particle group optimizing module of video object detection unit is connected with the replacing background interrupting input end INT3 of the image detection module of video object detection unit；The input end of clock CLK2 and logic control element of the particle group optimizing module of video object detection unit output terminal of clock CLK2 connections；
The address out bus A2 [21 of the image detection module of video object detection unit:0] Flash control modules with video object detection unit, the address input bus A2 [21 of image pre-processing unit:0] connect；The data/address bus D [7 of the image detection module of video object detection unit:0] with Flash modules, SDRAM module, the data/address bus D [7 of SDRAM1 modules:0] connect；The dual port RAM address out bus AB2 [16 of the image detection module of video object detection unit:0] with the dual port RAM address input bus AB2 [16 of the dual port RAM module of video object detection unit:0] connect；The dual port RAM data/address bus DB2 [7 of the image detection module of video object detection unit:0] with the dual port RAM data/address bus DB2 [7 of the dual port RAM module of video object detection unit:0] connect；The Flash pieces of the image detection module of video object detection unit select control end FCE2 to select control end FCE2 to be connected with the Flash pieces of Flash control modules；The Flash Read-write Catrols end FR/W2 of the image detection module of video object detection unit is connected with the Flash Read-write Catrols end FR/W2 of Flash control modules；Read-write Catrol end R/W-2s of the Read-write Catrol end R/W-2 of the image detection module of video object detection unit respectively with dual port RAM module, image pre-processing unit is connected；The dual port RAM piece of the image detection module of video object detection unit selects the dual port RAM piece of the dual port RAM module of control end CE-2 and image pre-processing unit to select control end CE-2 connections；The SDRAM pieces of the image detection module of video object detection unit select the SDRAM pieces of control end SDCE2 and image pre-processing unit to select control end SDCE2 connections；The image detection enabling signal control end JcQD and logic control element of the image detection module of video object detection unit image detection enabling signal control end JcQD connections；The image detection of the image detection module of video object detection unit completes signal output part SrED and the image detection of logic control element completes signal input part SrED connections；The image detection request signal control end ReQ and logic control element of the image detection module of video object detection unit image detection request signal control end ReQ connections；The replacing background interrupting input end INT3 of the image detection module of video object detection unit is connected with the replacing background interrupt output end INT3 of the particle group optimizing module of video object detection unit；The target location output signal bus YO [11 of the image detection module of video object detection unit:0] with the target location input signal bus YO [11 of target location output unit:0] connect；The input end of clock CLK2 and logic control element of the image detection module of video object detection unit output terminal of clock CLK2 connections.
As shown in figure 5, the target location output unit of the FPGA video detections controller is made up of output control module, FIFO-A modules.Wherein：
The target location input signal bus YO [11 of the FIFO-A modules of target location output unit:0] with the target location output signal bus YO [11 of the image detection module of video object detection unit:0] connect；The target location output signal bus UO [11 of the FIFO-A modules of target location output unit:0] the target location input signal bus UO [11 with control module is driven with position:0] connect；The input end of clock CLK3 and logic control element of the FIFO-A modules of target location output unit output terminal of clock CLK3 connections；
The data output control end ReAD of the output control module of target location output unit is connected with position driving with the data input control end ReAD of control module；The data sending request input RQ of the output control module of target location output unit is connected with position driving with the data sending request output end RQ of control module；The data reading signal input READ of the output control module of target location output unit is connected with position driving with the data reading signal output end READ of control module；The interrupt signal input INT4 of the output control module of target location output unit is connected with position driving with the interrupt signal output end INT4 of control module；The target position signal output control terminal REY and logic control element of the output control module of target location output unit target position signal output control terminal REY connections；The input end of clock CLK3 and logic control element of the output control module of target location output unit output terminal of clock CLK3 connections.
Detailed operation flow of the present utility model is as follows：After energization, system initialization routine is first carried out in the FPGA vision-based detection controllers of sensation target self-adapting detecting controller based on FPGA technology, the control module output order DB of logic control element is to the command input DB of the Video Controller module of image pre-processing unit, and the Video Controller module of image pre-processing unit is configured universal serial bus CB1, CB2 and carries out system configuration to video input module；After the completion of system configuration, the control module of the logic control element of FPGA vision-based detection controllers exports trigger collection signal READY to video input module, video input module starts to receive the analog input signal of ccd video camera, and be converted to the digital video signal of corresponding format, analog video input data bus VI [15 of the digital video signal through FPGA vision-based detection controllers:0], in the fifo module that the image pre-processing unit of FPGA vision-based detection controllers is input under clock CLK1 control.
The fifo module of image pre-processing unit operates the picture signal DB1 [7 that the view data of serial input is converted to 3 row parallel outputs by shift LD:0]、DB2[7:0]、DB3[7:0]；The picture signal DB1 [7 of 3 row parallel outputs of the fifo module of image pre-processing unit:0]、DB2[7:0]、DB3[7:0] it is input to parallel in filtration module, carries out 3 × 3 median filter process, median filtering algorithm is：
First by each row of the video image in fifo module according to ascending sort；The minimum value, the intermediate value of secondary series, tertial maximum of first row are taken afterwards；Finally take the intermediate value of these three values, i.e. med=med (min 1, med2, max 3).
Memory module output SDRAM Read-write Catrols end R/W-1, SDRAM piece of video pre-processing units is selected in control end SDCE1 to SDRAM control modules, corresponding SDRAM module, chip selection signal CE1, CE1 and read-write SDR/W1, SDR/W2 of SDRM1 modules are exported after SDRAM control module decoding process, by the video frequency output bus DB [7 of filtration module in the way of " table tennis " is stored:0] vision signal of the median filter process of output is respectively stored into SDRAM module and SDRM1 modules by the parity field of image.
After the pretreatment of one two field picture, the memory module output image storage of image pre-processing unit completes interrupt signal INT1 to logic control element, the trigger collection signal READY control video input modules of logic control element input next two field picture, and output image detects the view data that enabling signal ReQ is crossed to video object detection unit, control video object detection unit reading process；Video object detection unit is receiving the image detection enabling signal ReQ of logic control element, starts to detect collection image progress image light situation by light detection module.
The video object detection unit of FPGA vision-based detections controller carries out the detection of visual movement target using background subtraction detection algorithm in the present embodiment, background subtraction detection algorithm is that collection image and background image are made into gray scale difference operation, and the point that wherein gray value is not zero may be considered target point.In order to improve the accuracy of sensation target detection, many image modeling methods that background image storehouse is constituted with multiple typical background images are used to the background modeling of background subtraction detection algorithm.During actually detected, the method by choosing suitable background image in many iconic models, to improve background subtraction detection algorithm accuracy.
The light detection module of FPGA vision-based detection controllers uses image local light detection algorithm, selects monitoring scene light at five to change detection zone on collection image（50 × 150 pixels）, to be detected the average gray histogram information of image in regional area
To estimate, wherein
For the corresponding histogram of image,For grey level.Normalized is weighted to the average gray histogram of each detection topography of selection：
Wherein
It is the weight that 5 light change test point, meets。
Average gray histogram after normalized
If less than default detection threshold value T1, the interrupt output end INT2 of light detection module is set to 0；The particle group optimizing module of video object detection unit carries out adaptive optimization processing when interrupting input end INT2 is 0 to the background image model of background subtraction detection algorithm.
The particle group optimizing module of video object detection unit uses standard particle colony optimization algorithm in the present embodiment：
Wherein
,For population scale,For current iteration number of times,
,
To be distributed inBetween random number；
With
For positive integer, referred to as Studying factors, respectively cognitive parameter and social parameter,
Represent particle
Current location； Represent particle
Present speed；
Represent particle
The preferably solution searched； 
Represent the preferably solution that whole population is searched.
The particle group optimizing module of video object detection unit is when interrupting input end INT2 is 0, and particle group optimizing module output Flash pieces select control signal FCE1 and Flash read-write control signal FR/W1, pass through address out bus A2 [21:0] and data/address bus D [7:0] view data of 3 setting detection zones on each background image in many iconic models of the storage in Flash is read, the view data for gathering each same detection region on image with monitoring scene simultaneously carries out feature evolutionary operation, by the iteration optimizing mechanism of particle swarm optimization algorithm, the immediate background image of background characteristics that image is gathered with monitoring scene is found in many iconic models；
Particle swarm optimization algorithm is with the distance measure of each correspondence detection zone
The fitness function of minimum particle swarm optimization algorithm, i.e.,
Particle is encoded is using block coding form
, wherein
,
The respectively two corresponding pixels of width gray level imageThe gray value at place,
,The respectively wide and high pixel number in images match region,
The picture centre point coordinates of 3 × 3 pixel regions is represented,
For population scale.
Particle group optimizing module output dual port RAM read-write control signal R/W-3, dual port RAM piece select control signal CE-1, pass through dual port RAM address out bus AB1 [16:0], dual port RAM module data bus DB1 [7:0] optimal particle is encoded, target detection slides the size of detection window, the storage address of optimal background image deposit dual port RAM module；
After particle swarm optimization algorithm iteration optimizing, the replacing background interrupt output end INT3 of particle group optimizing module is set to 0, and notifies that the image detection module of video object detection unit carries out the renewal operation of background image model；The image detection module of video object detection unit is when replacing background interrupt output end INT3 is 0, and image detection module output read-write control signal R/W-2, dual port RAM piece select control signal CE-2, pass through dual port RAM address out bus AB2 [16:0], dual port RAM module data bus DB2 [7:0] target detection read in dual port RAM module is slided into the size for detecting window, optimal background image address, the image detection module of video object detection unit reads the background image of the storage in Flash through Flash control modules, realizes the renewal of background image in background subtraction detection algorithm.
When sensor assembly detects moving target, detect the logic control element of signal TRI to FPGA vision-based detection controllers in sensor assembly output target location, logic control element output image detection enabling signal control instruction JcQD, the image detection module of the video object detection unit of FPGA vision-based detection controllers is controlled to carry out sensation target detection, its detecting step is：
First, in order to improve on the recognition accuracy of target, the image after background difference operation, pass through and slide the target detection of a variable dimension and slide detection window.Detection window is slided in target detection and falls into a trap nomogram as the gray value of vertical direction, vertical direction gray value is chosen and is more than threshold value T2 row, and calculates its total A, if row sum A exceedes threshold value T3, is had moving target to enter or leave target detection and is slided detection window；Otherwise without motion target enters or left in target detection slides detection window；
Secondly, whether the difference for calculating the row gray value that target detection slides detection window two ends changes；If changed, reduce the width that target detection slides detection window, until the difference of row gray value is less than threshold value T4, the left side edge position that now target detection slides detection window is the marginal position of moving target, and image detection module passes through target location output signal bus YO [11:0] marginal position of moving target is stored into the fifo module of target location output unit；
Finally, the detection of image detection module output image completes signal SrED to logic control element, is ready for the target detection of next two field picture.
Present embodiment uses the image pick-up signal to CCD camera, utilize the characteristic of FPGA parallel computations, sensation target detection method based on particle swarm optimization algorithm, moving target in extract real-time video, the Detection ＆ Controling function of being realized with control module to sensation target is driven by position.
Claims (6)
1. a kind of sensation target self-adapting detecting controller based on FPGA technology, it is characterised in that：Including CCD camera, video input module, clock module, sensor assembly, position driving with control module with, FPGA video detection controllers；The analog video output signal end of CCD camera and the analog video input signal end of video input module are connected；The video output terminals of video input module are connected with the video pre-processing units input of FPGA video detection controllers, the synchronous control signal end of video input module is connected with the Synchronization Control end of FPGA video detection controllers, and the configuration controlling bus end of video input module is connected with the configuration controlling bus end of FPGA video detection controllers；The control signal end of the target location output unit of FPGA video detection controllers is connected with position driving with the control signal end of control module, the target position signal output bus of the target location output unit of FPGA video detection controllers is connected with position driving with the target position signal input bus of control module, and position driving is connected with the drive signal end of control module and the drive signal end of actuating motor；The target location detection input signal end of FPGA video detection controllers and the target location detection output signal end connection of sensor assembly；The input end of clock of FPGA video detection controllers and the output terminal of clock of clock module are connected；The data/address bus and address bus of FPGA video detection controllers are connected with FLASH modules, SDRAM module, the data/address bus of SDRAM1 modules and address bus respectively；The SDRAM control output ends of FPGA video detection controllers and the control signal of SDRAM module are connected, and the SDRAM1 control output ends of FPGA video detection controllers are connected with the control signal of SDRAM1 modules；The Flash control output ends of FPGA video detection controllers are connected with the control signal of Flash modules.
2. the sensation target self-adapting detecting controller according to claim 1 based on FPGA technology, it is characterised in that：The FPGA video detections controller is made up of the logic control element write with Verilog hardware description languages, video pre-processing units, video object detection unit, target location output unit.
3. the sensation target self-adapting detecting controller according to claim 2 based on FPGA technology, it is characterised in that：The logic control element is made up of clock frequency division module, control module.
4. the sensation target self-adapting detecting controller according to claim 2 based on FPGA technology, it is characterised in that：The video pre-processing units are made up of Video Controller module, fifo module, filtration module, memory module, SDRAM control modules.
5. the sensation target self-adapting detecting controller according to claim 2 based on FPGA technology, it is characterised in that：The video object detection unit is made up of Flash control modules, dual port RAM module, light detection module, image detection module, particle group optimizing module.
6. the sensation target self-adapting detecting controller according to claim 2 based on FPGA technology, it is characterised in that：Described target location output unit is made up of output control module, FIFO-A modules.
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