CN202383670U - Serial-to-parallel converter - Google Patents
Serial-to-parallel converter Download PDFInfo
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- CN202383670U CN202383670U CN2011205150863U CN201120515086U CN202383670U CN 202383670 U CN202383670 U CN 202383670U CN 2011205150863 U CN2011205150863 U CN 2011205150863U CN 201120515086 U CN201120515086 U CN 201120515086U CN 202383670 U CN202383670 U CN 202383670U
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Abstract
The utility model relates to a serial-to-parallel converter which comprises a computer case, wherein a power supply switch, a serial input interface and multiple parallel input interfaces are arranged on the computer case; a power circuit, a master control circuit and a serial port communication circuit are arranged in the computer case; the pin 14 and the pin 13 of the serial port communication circuit U2 are electrically connected with the pin 2 and the pin 3 of the serial input interface respectively; the pin 12 and the pin 11 of the serial port communication circuit U2 are electrically connected with the pin 5 and the pin 7 of a singlechip circuit U1 respectively; the singlechip circuit U1 is arranged in the master control circuit; the pin 16 of the singlechip circuit U1 and the pin 5 of the serial input interface are connected with the power ground; and the pin 40 of the singlechip U1 is electrically connected with a parallel output interface 1. The serial-to-parallel converter can convert a serial signal with two communication ports into a parallel output interface (I/O interface) with numerous other functions, and further, the serial-to-parallel converter also can receive and identify as well as transmit commands, and transmit data.
Description
Technical field
The utility model relates to a kind of deserializer, and power switch, serial input interface, a plurality of parallel output interface are set on the cabinet of this deserializer, and cabinet inside is provided with power circuit, governor circuit, serial communication circuit.
Background technology
In the prior art, when needing control multichannel delivery outlet control image data, owing to there is not so much delivery outlet; Just need control delivery outlet respectively, and can not control the delivery outlet image data of working simultaneously simultaneously, lose time; The control of inefficiency and completion or the data of collection are not necessarily accurately (because can not handle simultaneously; It is wrong to cause data to read), and outside parts of control or when gathering outside data, need a plurality of processors go to accomplish; Efficiency ratio is lower like this, and function ratio is difficult to realize.Chinese patent 2009l0057177.4 discloses the multiple MCU interface of a kind of automatic detection and realized the device of interface conversion, comprising: the automatic detection module of interface is used for detecting automatically the interface modes of current input signal; The SPI serial ports changes the parallel port module, is used to realize that the rs 232 serial interface signal with SPI converts the parallel port signal into; Interface modular converter according to the interface modes signal that the automatic detection module of interface detects, carries out corresponding interface and selects and change, and obtains needed interface signal.The present invention can effectively solve the mutually incompatible problem of multiple interfaces.The I/O mouth of the expansion of this patent is all fewer, can not expand a lot of roads, and certain restriction is arranged.So, need to propose a kind of deserializer.
Summary of the invention
The purpose of the utility model is to provide a kind of deserializer, and power switch, serial input interface, a plurality of parallel output interface are set on the cabinet of this deserializer, and cabinet inside is provided with power circuit, governor circuit, serial communication circuit.The utility model can will have the serial signal of two COM1s convert to and have a lot of other function parallelization output interfaces (I/O mouth), can receive order, recognition command sends order, sends data.
The purpose of the utility model is realized by following technical proposals: a kind of deserializer; A cabinet is arranged; Power switch, serial input interface, a plurality of parallel output interface are set on the said cabinet, and said cabinet inside is provided with power circuit, governor circuit, serial communication circuit; The pin 14 of said serial communication circuit U2, pin 13 are electrically connected with pin 2, the pin 3 of said serial input interface respectively, the pin 12 of serial communication circuit U2, pin 11 respectively with said governor circuit in pin 5, the pin 7 of single chip circuit U1 be electrically connected, single chip circuit U1 is arranged in the described governor circuit; The pin 16 of said single chip circuit U1 is connected power supply ground with the pin 5 of said serial input interface, and the pin 40 of said single chip circuit U1 is electrically connected with parallel output interface 1, and its pin 41 is electrically connected with parallel output interface 2; Its pin 42 is electrically connected with parallel output interface 3, and its pin 43 is electrically connected with parallel output interface 4, and its pin 44 is electrically connected with parallel output interface 5; Its pin 1 is electrically connected with parallel output interface 6, and its pin 2 is electrically connected with parallel output interface 7, and its pin 3 is electrically connected with parallel output interface 8; Its pin 18 is electrically connected with parallel output interface 9, and its pin 19 is electrically connected with parallel output interface 10, and its pin 20 is electrically connected with parallel output interface 11; Its pin 21 is electrically connected with parallel output interface 12, and its pin 22 is electrically connected with parallel output interface 13, and its pin 23 is electrically connected with parallel output interface 14; Its pin 24 is electrically connected for parallel output interface 15, and its pin 25 is electrically connected with parallel output interface 16, and its pin 26 is electrically connected with parallel output interface 17; Its pin 8 is electrically connected with parallel output interface 18; Its pin 9 is electrically connected with parallel output interface 19, and its pin 10 is electrically connected with parallel output interface 20, and its pin 11 is electrically connected with parallel output interface 21; Its pin 12 is electrically connected with parallel output interface 22; Its pin 13 is electrically connected with parallel output interface 23, and its pin 17 is electrically connected with parallel output interface 24, and its pin 28 is electrically connected with parallel output interface 25; Its pin 39 is electrically connected with parallel output interface 26, and its pin 6 is electrically connected with parallel output interface 27.
The utility model compared with prior art has following advantage:
1, the utility model converts the serial signal with two COM1s to and has other a lot of function parallelization output interfaces (I/O), can receive order, and recognition command sends order, sends data; The number of pin of input is few, and the parallel port number of pin is a lot, in theory can be near unlimited.
2, the utility model can have been accomplished very complex multipath output logic with considerably less input I/O, and the output I/O of control accomplishes multiple function, image data, control external unit.
3, the utility model can a plurality of I/O be connected in parallel and forms a pack module, accomplishes string and the control of a plurality of I/O.
4, in the utility model when power supply state, when not going here and there and changing, all parallel ports and serial ports are low level state; Do not carry out any action, when serial ports was sent order or acquisition, corresponding action was just made in corresponding parallel port; Energy consumption is low, starts rapidly.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the utility model is described further.
Fig. 1 is the external structure synoptic diagram of the utility model;
Fig. 2 is the structural representation at the utility model back side;
Fig. 3 is the electrical principle block diagram of the utility model;
Fig. 4 is the governor circuit and the telecommunication circuit schematic diagram of the utility model;
Fig. 5 is the circuit theory diagrams of the U5-U7 of embodiment two;
Fig. 6 is the circuit theory diagrams of the U8-U10 of embodiment two;
Fig. 7 is the circuit theory diagrams of the U11 of embodiment two.
Embodiment
Embodiment one:
Referring to Fig. 1, Fig. 2, Fig. 3, power switch 2, serial input interface 3, a plurality of parallel output interface 4 are set on the cabinet 1 of a kind of deserializer of the utility model, said cabinet inside is provided with power circuit 6, governor circuit 8, serial communication circuit 7; The pin 14 of said serial communication circuit U2, pin 13 are electrically connected with pin 2, the pin 3 of said serial input interface respectively; The pin 12 of serial communication circuit U2, pin 11 are electrically connected with pin 5, the pin 7 of single chip circuit U1 respectively; Single chip circuit U1 is arranged in the described governor circuit; The pin 16 of said single chip circuit U1 is connected power supply ground with the pin 5 of said serial input interface; The pin 40 of said single chip circuit U1 is electrically connected with parallel output interface 1, and its pin 41 is electrically connected with parallel output interface 2 that (its pin 41 is meant the pin 41 of single chip circuit U1, below analogizes.), its pin 42 is electrically connected with parallel output interface 3, and its pin 43 is electrically connected with parallel output interface 4; Its pin 44 is electrically connected with parallel output interface 5, and its pin 1 is electrically connected with parallel output interface 6, and its pin 2 is electrically connected with parallel output interface 7; Its pin 3 is electrically connected with parallel output interface 8, and its pin 18 is electrically connected with parallel output interface 9, and its pin 19 is electrically connected with parallel output interface 10; Its pin 20 is electrically connected with parallel output interface 11, and its pin 21 is electrically connected with parallel output interface 12, and its pin 22 is electrically connected with parallel output interface 13; Its pin 23 is electrically connected with parallel output interface 14, and its pin 24 is electrically connected for parallel output interface 15, and its pin 25 is electrically connected with parallel output interface 16; Its pin 26 is electrically connected with parallel output interface 17, and its pin 8 is electrically connected with parallel output interface 18, and its pin 9 is electrically connected with parallel output interface 19; Its pin 10 is electrically connected with parallel output interface 20, and its pin 11 is electrically connected with parallel output interface 21, and its pin 12 is electrically connected with parallel output interface 22; Its pin 13 is electrically connected with parallel output interface 23, and its pin 17 is electrically connected with parallel output interface 24, and its pin 28 is electrically connected with parallel output interface 25; Its pin 39 is electrically connected with parallel output interface 26, and its pin 6 is electrically connected with parallel output interface 27.
Referring to Fig. 1, in the present embodiment, power switch 2, serial input interface (I/O is input port/output port) 3, a plurality of parallel output interface (I/O) 4 are set on the front panel of said cabinet.AC power supply jack 5 is set on the rear panel of said cabinet, and power circuit is connected with outside 220V AC power through AC power supply jack.The startup of power circuit with close by power switch 2 control.Comprise a Switching Power Supply, a DC power supplier (model URB2405D-5W) in the described power circuit, Switching Power Supply converts direct current 24V into 5V and supplies with governor circuit, serial communication circuit for direct current 24V output, DC power supplier.The serial input interface is one 9 needle interface, only uses 4 pins, a power pin; A ground pin; Two communication interface pins, one is clock line, one is data line.
Referring to Fig. 1, Fig. 3; In the present embodiment, 24 or 27 parallel output interfaces are set altogether on the front panel of cabinet, first row is provided with parallel output interface 1-12 from left to right; Second row is provided with parallel output interface 13-24 from left to right, does not illustrate among the parallel output interface 25-27 figure.The quantity of parallel output interface can be provided with more according to actual needs.This interface is the interface of a socket type, can insert data line by inserting mode, and an interface allows the line of pegging graft.A plurality of parallel output interfaces are arranged on the printed circuit board (printed circuit board (PCB) belongs to routine techniques), write the control program that serial signal converts parallel signal among the single chip circuit U1 in advance.The deserializer of present embodiment is when power supply state; When not going here and there and changing; All parallel output interfaces and serial input interface are low level state; Do not carry out any action, when the serial input interface was sent order or acquisition, parallel accordingly output interface was just made corresponding action.
Single chip circuit U1 is arranged in the described governor circuit; The pin 4 that the pin 16 of said single chip circuit U1 and the pin 5 of said serial input interface meet power supply ground, said single chip circuit U1 connects the negative pole of electrochemical capacitor C1, and connecting resistance R1 is to power supply ground (printed circuit board (PCB) ground) again; The pin 14 of said single chip circuit U1, pin 15 meet ceramic disc capacitor C2, C3 respectively to power supply ground, and passive crystal oscillator Y1 is connected in parallel on pin 14, the pin 15 of single chip circuit U1.The model of said single chip circuit U1 is STC12C5A60S2.
The pin 14 of said serial communication circuit U2, pin 13 are electrically connected with pin 2, the pin 3 of said serial input interface respectively; The pin 1 of serial communication circuit U2, pin 3 join with positive pole, the negative pole of electrochemical capacitor C4 respectively; The pin 2 of serial communication circuit U2 connects the positive pole of the C7 of electrochemical capacitor; The pin 4 of serial communication circuit U2, pin 5 join with positive pole, the negative pole of electrochemical capacitor C5 respectively, and the pin 6 of serial communication circuit U2 connects the negative pole of electrochemical capacitor C6, and the pin 12 of serial communication circuit U2, pin 11 join with pin 5, the pin 7 of single chip circuit U1 respectively; Wherein serial communication circuit U2 is the serial communication chip, and the electric capacity of its configuration is for letting level match.The model of said serial communication circuit U2 is MAX232C.Single chip circuit U1 in the governor circuit, serial communication circuit U2 and the circuit component that is complementary are arranged on (printed circuit board (PCB) belongs to the routine techniques content) on the printed circuit board.
Other electrical symbol, label, literal among Fig. 4 of present embodiment in related (on the printed circuit board (PCB)) integrated circuit all belong to the prior art content; Do not describe one by one; Do not have electrical symbol, label, the literal of description, those skilled in the art can understand fully.
Embodiment two:
A kind of deserializer in the present embodiment is the improvement on embodiment one basis, and disclosed technology contents is not repeated in this description among the embodiment one, and embodiment one disclosed content also belongs to the disclosed content of present embodiment.
The present embodiment output interface that will walk abreast is increased to 259, for this reason, increases a plurality of single chip circuits, i.e. single chip circuit U3-single chip circuit U11.The model of said single chip circuit U3 is STC12C5A60S2, and the model of said single chip circuit U5-single chip circuit U11 is STC12C5A60S2, and the model of said single chip circuit U4 is 74HC573.
In the present embodiment, also be provided with single chip circuit U3 in the described governor circuit, the pin 40 of said single chip circuit U3 is electrically connected with parallel output interface 28, and its pin 41 is electrically connected with parallel output interface 29; Its pin 42 is electrically connected with parallel output interface 30, and its pin 43 is electrically connected with parallel output interface 31, and its pin 44 is electrically connected with parallel output interface 32; Its pin 1 is electrically connected with parallel output interface 33, and its pin 2 is electrically connected with parallel output interface 34, and its pin 3 is electrically connected with parallel output interface 35; Its pin 18 is electrically connected with parallel output interface 36, and its pin 19 is electrically connected with parallel output interface 37, and its pin 20 is electrically connected with parallel output interface 38; Its pin 21 is electrically connected with parallel output interface 39, and its pin 22 is electrically connected with parallel output interface 40, and its pin 23 is electrically connected with parallel output interface 41; Its pin 24 is electrically connected with parallel output interface 42, and its pin 25 is electrically connected with parallel output interface 43, and its pin 5 is electrically connected with parallel output interface 44; Its pin 7 is electrically connected with parallel output interface 45, and its pin 8 is electrically connected with parallel output interface 46, and its pin 9 is electrically connected with parallel output interface 47; Its pin 10 is electrically connected with parallel output interface 48, and its pin 11 is electrically connected with parallel output interface 49, and its pin 12 is electrically connected with parallel output interface 50; Its pin 13 is electrically connected with parallel output interface 51, and its pin 17 is electrically connected with parallel output interface 52, and its pin 28 is electrically connected with parallel output interface 53; Its pin 39 is electrically connected with parallel output interface 54, and its pin 6 is electrically connected with parallel output interface 55, and its pin 26 is electrically connected with parallel output interface 56;
Also be provided with single chip circuit U5 in the described governor circuit, the pin 40 of said single chip circuit U5 is electrically connected with parallel output interface 57, and its pin 41 is electrically connected with parallel output interface 58; Its pin 42 is electrically connected with parallel output interface 59, and its pin 43 is electrically connected with parallel output interface 60, and its pin 44 is electrically connected with parallel output interface 61; Its pin 1 is electrically connected with parallel output interface 62, and its pin 2 is electrically connected with parallel output interface 63, and its pin 3 is electrically connected with parallel output interface 64; Its pin 18 is electrically connected with parallel output interface 65, and its pin 19 is electrically connected with parallel output interface 66, and its pin 20 is electrically connected with parallel output interface 67; Its pin 21 is electrically connected with parallel output interface 68, and its pin 22 is electrically connected with parallel output interface 69, and its pin 23 is electrically connected with parallel output interface 70; Its pin 24 is electrically connected with parallel output interface 71, and its pin 25 is electrically connected with parallel output interface 72, and its pin 5 is electrically connected with parallel output interface 73; Its pin 7 is electrically connected with parallel output interface 74, and its pin 8 is electrically connected with parallel output interface 75, and its pin 9 is electrically connected with parallel output interface 76; Its pin 10 is electrically connected with parallel output interface 77, and its pin 11 is electrically connected with parallel output interface 78, and its pin 12 is electrically connected with parallel output interface 79; Its pin 13 is electrically connected with parallel output interface 80, and its pin 17 is electrically connected with parallel output interface 81, and its pin 28 is electrically connected with parallel output interface 82; Its pin 39 is electrically connected with parallel output interface 83, and its pin 6 is electrically connected with parallel output interface 84, and its pin 26 is electrically connected with parallel output interface 85;
Also be provided with single chip circuit U6 in the described governor circuit, the pin 40 of said single chip circuit U6 is electrically connected with parallel output interface 86, and its pin 41 is electrically connected with parallel output interface 87; Its pin 42 is electrically connected with parallel output interface 88, and its pin 43 is electrically connected with parallel output interface 89, and its pin 44 is electrically connected with parallel output interface 90; Its pin 1 is electrically connected with parallel output interface 91, and its pin 2 is electrically connected with parallel output interface 92, and its pin 3 is electrically connected with parallel output interface 93; Its pin 18 is electrically connected with parallel output interface 94, and its pin 19 is electrically connected with parallel output interface 95, and its pin 20 is electrically connected with parallel output interface 96; Its pin 21 is electrically connected with parallel output interface 97, and its pin 22 is electrically connected with parallel output interface 98, and its pin 23 is electrically connected with parallel output interface 99; Its pin 24 is electrically connected with parallel output interface 100, and its pin 25 is electrically connected with parallel output interface 101, and its pin 5 is electrically connected with parallel output interface 102; Its pin 7 is electrically connected with parallel output interface 103, and its pin 8 is electrically connected with parallel output interface 104, and its pin 9 is electrically connected with parallel output interface 105; Its pin 10 is electrically connected with parallel output interface 106, and its pin 11 is electrically connected with parallel output interface 107, and its pin 12 is electrically connected with parallel output interface 108; Its pin 13 is electrically connected with parallel output interface 109; Its pin 17 is electrically connected with parallel output interface 110, and its pin 28 is electrically connected with parallel output interface 111, and its pin 39 is electrically connected with parallel output interface 112; Its pin 6 is electrically connected with parallel output interface 113, and its pin 26 is electrically connected with parallel output interface 114;
Also be provided with single chip circuit U7 in the described governor circuit, the pin 40 of said single chip circuit U7 is electrically connected with parallel output interface 115, and its pin 41 is electrically connected with parallel output interface 116; Its pin 42 is electrically connected with parallel output interface 117, and its pin 43 is electrically connected with parallel output interface 118, and its pin 44 is electrically connected with parallel output interface 119; Its pin 1 is electrically connected with parallel output interface 120, and its pin 2 is electrically connected with parallel output interface 121, and its pin 3 is electrically connected with parallel output interface 122; Its pin 18 is electrically connected with parallel output interface 123, and its pin 19 is electrically connected with parallel output interface 124, and its pin 20 is electrically connected with parallel output interface 125; Its pin 21 is electrically connected with parallel output interface 126, and its pin 22 is electrically connected with parallel output interface 127, and its pin 23 is electrically connected with parallel output interface 128; Its pin 24 is electrically connected with parallel output interface 129, and its pin 25 is electrically connected with parallel output interface 130, and its pin 5 is electrically connected with parallel output interface 131; Its pin 7 is electrically connected with parallel output interface 132, and its pin 8 is electrically connected with parallel output interface 133, and its pin 9 is electrically connected with parallel output interface 134; Its pin 10 is electrically connected with parallel output interface 135, and its pin 11 is electrically connected with parallel output interface 136, and its pin 12 is electrically connected with parallel output interface 137; Its pin 13 is electrically connected with parallel output interface 138; Its pin 17 is electrically connected with parallel output interface 139, and its pin 28 is electrically connected with parallel output interface 140, and its pin 39 is electrically connected with parallel output interface 141; Its pin 6 is electrically connected with parallel output interface 142, and its pin 26 is electrically connected with parallel output interface 143;
Also be provided with single chip circuit U8 in the described governor circuit, the pin 40 of said single chip circuit U8 is electrically connected with parallel output interface 144, and its pin 41 is electrically connected with parallel output interface 145; Its pin 42 is electrically connected with parallel output interface 146, and its pin 43 is electrically connected with parallel output interface 147, and its pin 44 is electrically connected with parallel output interface 148; Its pin 1 is electrically connected with parallel output interface 149, and its pin 2 is electrically connected with parallel output interface 150, and its pin 3 is electrically connected with parallel output interface 151; Its pin 18 is electrically connected with parallel output interface 152, and its pin 19 is electrically connected with parallel output interface 153, and its pin 20 is electrically connected with parallel output interface 154; Its pin 21 is electrically connected with parallel output interface 155, and its pin 22 is electrically connected with parallel output interface 156, and its pin 23 is electrically connected with parallel output interface 157; Its pin 24 is electrically connected with parallel output interface 158, and its pin 25 is electrically connected with parallel output interface 159, and its pin 5 is electrically connected with parallel output interface 160; Its pin 7 is electrically connected with parallel output interface 161, and its pin 8 is electrically connected with parallel output interface 162, and its pin 9 is electrically connected with parallel output interface 163; Its pin 10 is electrically connected with parallel output interface 164, and its pin 11 is electrically connected with parallel output interface 165, and its pin 12 is electrically connected with parallel output interface 166; Its pin 13 is electrically connected with parallel output interface 167; Its pin 17 is electrically connected with parallel output interface 168, and its pin 28 is electrically connected with parallel output interface 169, and its pin 39 is electrically connected with parallel output interface 170; Its pin 6 is electrically connected with parallel output interface 171, and its pin 26 is electrically connected with parallel output interface 172;
Also be provided with single chip circuit U9 in the described governor circuit, the pin 40 of said single chip circuit U9 is electrically connected with parallel output interface 173, and its pin 41 is electrically connected with parallel output interface 174; Its pin 42 is electrically connected with parallel output interface 175, and its pin 43 is electrically connected with parallel output interface 176, and its pin 44 is electrically connected with parallel output interface 177; Its pin 1 is electrically connected with parallel output interface 178, and its pin 2 is electrically connected with parallel output interface 179, and its pin 3 is electrically connected with parallel output interface 180; Its pin 18 is electrically connected with parallel output interface 181, and its pin 19 is electrically connected with parallel output interface 182, and its pin 20 is electrically connected with parallel output interface 183; Its pin 21 is electrically connected with parallel output interface 184, and its pin 22 is electrically connected with parallel output interface 185, and its pin 23 is electrically connected with parallel output interface 186; Its pin 24 is electrically connected with parallel output interface 187, and its pin 25 is electrically connected with parallel output interface 188, and its pin 5 is electrically connected with parallel output interface 189; Its pin 7 is electrically connected with parallel output interface 190, and its pin 8 is electrically connected with parallel output interface 191, and its pin 9 is electrically connected with parallel output interface 192; Its pin 10 is electrically connected with parallel output interface 193, and its pin 11 is electrically connected with parallel output interface 194, and its pin 12 is electrically connected with parallel output interface 195; Its pin 13 is electrically connected with parallel output interface 196; Its pin 17 is electrically connected with parallel output interface 197, and its pin 28 is electrically connected with parallel output interface 198, and its pin 39 is electrically connected with parallel output interface 199; Its pin 6 is electrically connected with parallel output interface 200, and its pin 26 is electrically connected with parallel output interface 201;
Also be provided with single chip circuit U10 in the described governor circuit, the pin 40 of said single chip circuit U10 is electrically connected with parallel output interface 202, and its pin 41 is electrically connected with parallel output interface 203; Its pin 42 is electrically connected with parallel output interface 204, and its pin 43 is electrically connected with parallel output interface 205, and its pin 44 is electrically connected with parallel output interface 206; Its pin 1 is electrically connected with parallel output interface 207, and its pin 2 is electrically connected with parallel output interface 208, and its pin 3 is electrically connected with parallel output interface 209; Its pin 18 is electrically connected with parallel output interface 210, and its pin 19 is electrically connected with parallel output interface 211, and its pin 20 is electrically connected with parallel output interface 212; Its pin 21 is electrically connected with parallel output interface 213, and its pin 22 is electrically connected with parallel output interface 214, and its pin 23 is electrically connected with parallel output interface 215; Its pin 24 is electrically connected with parallel output interface 216, and its pin 25 is electrically connected with parallel output interface 217, and its pin 5 is electrically connected with parallel output interface 218; Its pin 7 is electrically connected with parallel output interface 219, and its pin 8 is electrically connected with parallel output interface 210, and its pin 9 is electrically connected with parallel output interface 211; Its pin 10 is electrically connected with parallel output interface 212, and its pin 11 is electrically connected with parallel output interface 213, and its pin 12 is electrically connected with parallel output interface 214; Its pin 13 is electrically connected with parallel output interface 225; Its pin 17 is electrically connected with parallel output interface 226, and its pin 28 is electrically connected with parallel output interface 227, and its pin 39 is electrically connected with parallel output interface 228; Its pin 6 is electrically connected with parallel output interface 229, and its pin 26 is electrically connected with parallel output interface 230;
Also be provided with single chip circuit U11 in the described governor circuit, the pin 40 of said single chip circuit U11 is electrically connected with parallel output interface 231, and its pin 41 is electrically connected with parallel output interface 232; Its pin 42 is electrically connected with parallel output interface 233, and its pin 43 is electrically connected with parallel output interface 234, and its pin 44 is electrically connected with parallel output interface 235; Its pin 1 is electrically connected with parallel output interface 236, and its pin 2 is electrically connected with parallel output interface 237, and its pin 3 is electrically connected with parallel output interface 238; Its pin 18 is electrically connected with parallel output interface 239, and its pin 19 is electrically connected with parallel output interface 240, and its pin 20 is electrically connected with parallel output interface 241; Its pin 21 is electrically connected with parallel output interface 242, and its pin 22 is electrically connected with parallel output interface 243, and its pin 23 is electrically connected with parallel output interface 244; Its pin 24 is electrically connected with parallel output interface 245, and its pin 25 is electrically connected with parallel output interface 246, and its pin 5 is electrically connected with parallel output interface 247; Its pin 7 is electrically connected with parallel output interface 248, and its pin 8 is electrically connected with parallel output interface 249, and its pin 9 is electrically connected with parallel output interface 250; Its pin 10 is electrically connected with parallel output interface 251, and its pin 11 is electrically connected with parallel output interface 252, and its pin 12 is electrically connected with parallel output interface 253; Its pin 13 is electrically connected with parallel output interface 254; Its pin 17 is electrically connected with parallel output interface 255, and its pin 28 is electrically connected with parallel output interface 256, and its pin 39 is electrically connected with parallel output interface 257; Its pin 6 is electrically connected with parallel output interface 258, and its pin 26 is electrically connected with parallel output interface 259;
The pin 37 of described single chip circuit U1, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, pin 30 are electrically connected with pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, the pin 9 of single chip circuit U4 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U3 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U5 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U6 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U7 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U8 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U9 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U10 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of single chip circuit U11 respectively.
Single chip circuit U1 controls single chip circuit U3, single chip circuit U5-single chip circuit U11 through single chip circuit U4.
The pin 4 of single chip circuit U1 is electrically connected the negative pole of electrochemical capacitor C1, and connecting resistance R1 is to power supply ground (printed circuit board (PCB) ground) again; The pin 14 of single chip circuit U1, pin 15 meet ceramic disc capacitor C2, C3 respectively to power supply ground, and passive crystal oscillator Y1 is connected in parallel on the pin 14, pin 15 of single chip circuit U1.
The pin 4 of single chip circuit U3 is electrically connected the negative pole of electrochemical capacitor C10, and connecting resistance R2 is to power supply ground again; The pin 14 of single chip circuit U3, pin 15 meet ceramic disc capacitor C8, C9 respectively to power supply ground, and passive crystal oscillator Y2 is connected in parallel on the pin 14, pin 15 of single chip circuit U3.
The pin 4 of single chip circuit U5 is electrically connected the negative pole of electrochemical capacitor C13, and connecting resistance R3 is to power supply ground again; The pin 14 of single chip circuit U5, pin 15 meet ceramic disc capacitor C11, C12 respectively to power supply ground, and passive crystal oscillator Y3 is connected in parallel on the pin 14, pin 15 of single chip circuit U5.
The pin 4 of single chip circuit U6 is electrically connected the negative pole of electrochemical capacitor C16, and connecting resistance R4 is to power supply ground again; The pin 14 of single chip circuit U6, pin 15 meet ceramic disc capacitor C14, C15 respectively to power supply ground, and passive crystal oscillator Y4 is connected in parallel on the pin 14, pin 15 of single chip circuit U6.
The pin 4 of single chip circuit U7 is electrically connected the negative pole of electrochemical capacitor C19, and connecting resistance R5 is to power supply ground again; The pin 14 of single chip circuit U7, pin 15 meet ceramic disc capacitor C17, C18 respectively to power supply ground, and passive crystal oscillator Y5 is connected in parallel on the pin 14, pin 15 of single chip circuit U7.
The pin 4 of single chip circuit U8 is electrically connected the negative pole of electrochemical capacitor C22, and connecting resistance R6 is to power supply ground again; The pin 14 of single chip circuit U8, pin 15 meet ceramic disc capacitor C20, C21 respectively to power supply ground, and passive crystal oscillator Y6 is connected in parallel on the pin 14, pin 15 of single chip circuit U8.
The pin 4 of single chip circuit U9 is electrically connected the negative pole of electrochemical capacitor C25, and connecting resistance R7 is to power supply ground again; The pin 14 of single chip circuit U9, pin 15 meet ceramic disc capacitor C23, C24 respectively to power supply ground, and passive crystal oscillator Y7 is connected in parallel on the pin 14, pin 15 of single chip circuit U9.
The pin 4 of single chip circuit U10 is electrically connected the negative pole of electrochemical capacitor C28, and connecting resistance R8 is to power supply ground again; The pin 14 of single chip circuit U10, pin 15 meet ceramic disc capacitor C26, C27 respectively to power supply ground, and passive crystal oscillator Y8 is connected in parallel on the pin 14, pin 15 of single chip circuit U10.
The pin 4 of single chip circuit U11 is electrically connected the negative pole of electrochemical capacitor C31, and connecting resistance R9 is to power supply ground again; The pin 14 of single chip circuit U11, pin 15 meet ceramic disc capacitor C29, C30 respectively to power supply ground, and passive crystal oscillator Y9 is connected in parallel on the pin 14, pin 15 of single chip circuit U11.
Claims (2)
1. a deserializer has a cabinet, it is characterized in that: power switch, serial input interface, a plurality of parallel output interface are set on the said cabinet, and said cabinet inside is provided with power circuit, governor circuit, serial communication circuit; The pin 14 of said serial communication circuit U2, pin 13 are electrically connected with pin 2, the pin 3 of said serial input interface respectively, the pin 12 of serial communication circuit U2, pin 11 respectively with said governor circuit in pin 5, the pin 7 of single chip circuit U1 be electrically connected, single chip circuit U1 is arranged in the described governor circuit; The pin 16 of said single chip circuit U1 is connected power supply ground with the pin 5 of said serial input interface, and the pin 40 of said single chip circuit U1 is electrically connected with parallel output interface 1, and its pin 41 is electrically connected with parallel output interface 2; Its pin 42 is electrically connected with parallel output interface 3, and its pin 43 is electrically connected with parallel output interface 4, and its pin 44 is electrically connected with parallel output interface 5; Its pin 1 is electrically connected with parallel output interface 6, and its pin 2 is electrically connected with parallel output interface 7, and its pin 3 is electrically connected with parallel output interface 8; Its pin 18 is electrically connected with parallel output interface 9, and its pin 19 is electrically connected with parallel output interface 10, and its pin 20 is electrically connected with parallel output interface 11; Its pin 21 is electrically connected with parallel output interface 12, and its pin 22 is electrically connected with parallel output interface 13, and its pin 23 is electrically connected with parallel output interface 14; Its pin 24 is electrically connected for parallel output interface 15, and its pin 25 is electrically connected with parallel output interface 16, and its pin 26 is electrically connected with parallel output interface 17; Its pin 8 is electrically connected with parallel output interface 18; Its pin 9 is electrically connected with parallel output interface 19, and its pin 10 is electrically connected with parallel output interface 20, and its pin 11 is electrically connected with parallel output interface 21; Its pin 12 is electrically connected with parallel output interface 22; Its pin 13 is electrically connected with parallel output interface 23, and its pin 17 is electrically connected with parallel output interface 24, and its pin 28 is electrically connected with parallel output interface 25; Its pin 39 is electrically connected with parallel output interface 26, and its pin 6 is electrically connected with parallel output interface 27.
2. deserializer according to claim 1 is characterized in that: also be provided with single chip circuit U3 in the described governor circuit, the pin 40 of said single chip circuit U3 is electrically connected with parallel output interface 28; Its pin 41 is electrically connected with parallel output interface 29, and its pin 42 is electrically connected with parallel output interface 30, and its pin 43 is electrically connected with parallel output interface 31; Its pin 44 is electrically connected with parallel output interface 32, and its pin 1 is electrically connected with parallel output interface 33, and its pin 2 is electrically connected with parallel output interface 34; Its pin 3 is electrically connected with parallel output interface 35, and its pin 18 is electrically connected with parallel output interface 36, and its pin 19 is electrically connected with parallel output interface 37; Its pin 20 is electrically connected with parallel output interface 38, and its pin 21 is electrically connected with parallel output interface 39, and its pin 22 is electrically connected with parallel output interface 40; Its pin 23 is electrically connected with parallel output interface 41, and its pin 24 is electrically connected with parallel output interface 42, and its pin 25 is electrically connected with parallel output interface 43; Its pin 5 is electrically connected with parallel output interface 44, and its pin 7 is electrically connected with parallel output interface 45, and its pin 8 is electrically connected with parallel output interface 46; Its pin 9 is electrically connected with parallel output interface 47, and its pin 10 is electrically connected with parallel output interface 48, and its pin 11 is electrically connected with parallel output interface 49; Its pin 12 is electrically connected with parallel output interface 50, and its pin 13 is electrically connected with parallel output interface 51, and its pin 17 is electrically connected with parallel output interface 52; Its pin 28 is electrically connected with parallel output interface 53; Its pin 39 is electrically connected with parallel output interface 54, and its pin 6 is electrically connected with parallel output interface 55, and its pin 26 is electrically connected with parallel output interface 56;
Also be provided with single chip circuit U5 in the described governor circuit, the pin 40 of said single chip circuit U5 is electrically connected with parallel output interface 57, and its pin 41 is electrically connected with parallel output interface 58; Its pin 42 is electrically connected with parallel output interface 59, and its pin 43 is electrically connected with parallel output interface 60, and its pin 44 is electrically connected with parallel output interface 61; Its pin 1 is electrically connected with parallel output interface 62, and its pin 2 is electrically connected with parallel output interface 63, and its pin 3 is electrically connected with parallel output interface 64; Its pin 18 is electrically connected with parallel output interface 65, and its pin 19 is electrically connected with parallel output interface 66, and its pin 20 is electrically connected with parallel output interface 67; Its pin 21 is electrically connected with parallel output interface 68, and its pin 22 is electrically connected with parallel output interface 69, and its pin 23 is electrically connected with parallel output interface 70; Its pin 24 is electrically connected with parallel output interface 71, and its pin 25 is electrically connected with parallel output interface 72, and its pin 5 is electrically connected with parallel output interface 73; Its pin 7 is electrically connected with parallel output interface 74, and its pin 8 is electrically connected with parallel output interface 75, and its pin 9 is electrically connected with parallel output interface 76; Its pin 10 is electrically connected with parallel output interface 77, and its pin 11 is electrically connected with parallel output interface 78, and its pin 12 is electrically connected with parallel output interface 79; Its pin 13 is electrically connected with parallel output interface 80, and its pin 17 is electrically connected with parallel output interface 81, and its pin 28 is electrically connected with parallel output interface 82; Its pin 39 is electrically connected with parallel output interface 83, and its pin 6 is electrically connected with parallel output interface 84, and its pin 26 is electrically connected with parallel output interface 85;
Also be provided with single chip circuit U6 in the described governor circuit, the pin 40 of said single chip circuit U6 is electrically connected with parallel output interface 86, and its pin 41 is electrically connected with parallel output interface 87; Its pin 42 is electrically connected with parallel output interface 88, and its pin 43 is electrically connected with parallel output interface 89, and its pin 44 is electrically connected with parallel output interface 90; Its pin 1 is electrically connected with parallel output interface 91, and its pin 2 is electrically connected with parallel output interface 92, and its pin 3 is electrically connected with parallel output interface 93; Its pin 18 is electrically connected with parallel output interface 94, and its pin 19 is electrically connected with parallel output interface 95, and its pin 20 is electrically connected with parallel output interface 96; Its pin 21 is electrically connected with parallel output interface 97, and its pin 22 is electrically connected with parallel output interface 98, and its pin 23 is electrically connected with parallel output interface 99; Its pin 24 is electrically connected with parallel output interface 100, and its pin 25 is electrically connected with parallel output interface 101, and its pin 5 is electrically connected with parallel output interface 102; Its pin 7 is electrically connected with parallel output interface 103, and its pin 8 is electrically connected with parallel output interface 104, and its pin 9 is electrically connected with parallel output interface 105; Its pin 10 is electrically connected with parallel output interface 106, and its pin 11 is electrically connected with parallel output interface 107, and its pin 12 is electrically connected with parallel output interface 108; Its pin 13 is electrically connected with parallel output interface 109; Its pin 17 is electrically connected with parallel output interface 110, and its pin 28 is electrically connected with parallel output interface 111, and its pin 39 is electrically connected with parallel output interface 112; Its pin 6 is electrically connected with parallel output interface 113, and its pin 26 is electrically connected with parallel output interface 114;
Also be provided with single chip circuit U7 in the described governor circuit, the pin 40 of said single chip circuit U7 is electrically connected with parallel output interface 115, and its pin 41 is electrically connected with parallel output interface 116; Its pin 42 is electrically connected with parallel output interface 117, and its pin 43 is electrically connected with parallel output interface 118, and its pin 44 is electrically connected with parallel output interface 119; Its pin 1 is electrically connected with parallel output interface 120, and its pin 2 is electrically connected with parallel output interface 121, and its pin 3 is electrically connected with parallel output interface 122; Its pin 18 is electrically connected with parallel output interface 123, and its pin 19 is electrically connected with parallel output interface 124, and its pin 20 is electrically connected with parallel output interface 125; Its pin 21 is electrically connected with parallel output interface 126, and its pin 22 is electrically connected with parallel output interface 127, and its pin 23 is electrically connected with parallel output interface 128; Its pin 24 is electrically connected with parallel output interface 129, and its pin 25 is electrically connected with parallel output interface 130, and its pin 5 is electrically connected with parallel output interface 131; Its pin 7 is electrically connected with parallel output interface 132, and its pin 8 is electrically connected with parallel output interface 133, and its pin 9 is electrically connected with parallel output interface 134; Its pin 10 is electrically connected with parallel output interface 135, and its pin 11 is electrically connected with parallel output interface 136, and its pin 12 is electrically connected with parallel output interface 137; Its pin 13 is electrically connected with parallel output interface 138; Its pin 17 is electrically connected with parallel output interface 139, and its pin 28 is electrically connected with parallel output interface 140, and its pin 39 is electrically connected with parallel output interface 141; Its pin 6 is electrically connected with parallel output interface 142, and its pin 26 is electrically connected with parallel output interface 143;
Also be provided with single chip circuit U8 in the described governor circuit, the pin 40 of said single chip circuit U8 is electrically connected with parallel output interface 144, and its pin 41 is electrically connected with parallel output interface 145; Its pin 42 is electrically connected with parallel output interface 146, and its pin 43 is electrically connected with parallel output interface 147, and its pin 44 is electrically connected with parallel output interface 148; Its pin 1 is electrically connected with parallel output interface 149, and its pin 2 is electrically connected with parallel output interface 150, and its pin 3 is electrically connected with parallel output interface 151; Its pin 18 is electrically connected with parallel output interface 152, and its pin 19 is electrically connected with parallel output interface 153, and its pin 20 is electrically connected with parallel output interface 154; Its pin 21 is electrically connected with parallel output interface 155, and its pin 22 is electrically connected with parallel output interface 156, and its pin 23 is electrically connected with parallel output interface 157; Its pin 24 is electrically connected with parallel output interface 158, and its pin 25 is electrically connected with parallel output interface 159, and its pin 5 is electrically connected with parallel output interface 160; Its pin 7 is electrically connected with parallel output interface 161, and its pin 8 is electrically connected with parallel output interface 162, and its pin 9 is electrically connected with parallel output interface 163; Its pin 10 is electrically connected with parallel output interface 164, and its pin 11 is electrically connected with parallel output interface 165, and its pin 12 is electrically connected with parallel output interface 166; Its pin 13 is electrically connected with parallel output interface 167; Its pin 17 is electrically connected with parallel output interface 168, and its pin 28 is electrically connected with parallel output interface 169, and its pin 39 is electrically connected with parallel output interface 170; Its pin 6 is electrically connected with parallel output interface 171, and its pin 26 is electrically connected with parallel output interface 172;
Also be provided with single chip circuit U9 in the described governor circuit, the pin 40 of said single chip circuit U9 is electrically connected with parallel output interface 173, and its pin 41 is electrically connected with parallel output interface 174; Its pin 42 is electrically connected with parallel output interface 175, and its pin 43 is electrically connected with parallel output interface 176, and its pin 44 is electrically connected with parallel output interface 177; Its pin 1 is electrically connected with parallel output interface 178, and its pin 2 is electrically connected with parallel output interface 179, and its pin 3 is electrically connected with parallel output interface 180; Its pin 18 is electrically connected with parallel output interface 181, and its pin 19 is electrically connected with parallel output interface 182, and its pin 20 is electrically connected with parallel output interface 183; Its pin 21 is electrically connected with parallel output interface 184, and its pin 22 is electrically connected with parallel output interface 185, and its pin 23 is electrically connected with parallel output interface 186; Its pin 24 is electrically connected with parallel output interface 187, and its pin 25 is electrically connected with parallel output interface 188, and its pin 5 is electrically connected with parallel output interface 189; Its pin 7 is electrically connected with parallel output interface 190, and its pin 8 is electrically connected with parallel output interface 191, and its pin 9 is electrically connected with parallel output interface 192; Its pin 10 is electrically connected with parallel output interface 193, and its pin 11 is electrically connected with parallel output interface 194, and its pin 12 is electrically connected with parallel output interface 195; Its pin 13 is electrically connected with parallel output interface 196; Its pin 17 is electrically connected with parallel output interface 197, and its pin 28 is electrically connected with parallel output interface 198, and its pin 39 is electrically connected with parallel output interface 199; Its pin 6 is electrically connected with parallel output interface 200, and its pin 26 is electrically connected with parallel output interface 201;
Also be provided with single chip circuit U10 in the described governor circuit, the pin 40 of said single chip circuit U10 is electrically connected with parallel output interface 202, and its pin 41 is electrically connected with parallel output interface 203; Its pin 42 is electrically connected with parallel output interface 204, and its pin 43 is electrically connected with parallel output interface 205, and its pin 44 is electrically connected with parallel output interface 206; Its pin 1 is electrically connected with parallel output interface 207, and its pin 2 is electrically connected with parallel output interface 208, and its pin 3 is electrically connected with parallel output interface 209; Its pin 18 is electrically connected with parallel output interface 210, and its pin 19 is electrically connected with parallel output interface 211, and its pin 20 is electrically connected with parallel output interface 212; Its pin 21 is electrically connected with parallel output interface 213, and its pin 22 is electrically connected with parallel output interface 214, and its pin 23 is electrically connected with parallel output interface 215; Its pin 24 is electrically connected with parallel output interface 216, and its pin 25 is electrically connected with parallel output interface 217, and its pin 5 is electrically connected with parallel output interface 218; Its pin 7 is electrically connected with parallel output interface 219, and its pin 8 is electrically connected with parallel output interface 210, and its pin 9 is electrically connected with parallel output interface 211; Its pin 10 is electrically connected with parallel output interface 212, and its pin 11 is electrically connected with parallel output interface 213, and its pin 12 is electrically connected with parallel output interface 214; Its pin 13 is electrically connected with parallel output interface 225; Its pin 17 is electrically connected with parallel output interface 226, and its pin 28 is electrically connected with parallel output interface 227, and its pin 39 is electrically connected with parallel output interface 228; Its pin 6 is electrically connected with parallel output interface 229, and its pin 26 is electrically connected with parallel output interface 230;
Also be provided with single chip circuit U11 in the described governor circuit, the pin 40 of said single chip circuit U11 is electrically connected with parallel output interface 231, and its pin 41 is electrically connected with parallel output interface 232; Its pin 42 is electrically connected with parallel output interface 233, and its pin 43 is electrically connected with parallel output interface 234, and its pin 44 is electrically connected with parallel output interface 235; Its pin 1 is electrically connected with parallel output interface 236, and its pin 2 is electrically connected with parallel output interface 237, and its pin 3 is electrically connected with parallel output interface 238; Its pin 18 is electrically connected with parallel output interface 239, and its pin 19 is electrically connected with parallel output interface 240, and its pin 20 is electrically connected with parallel output interface 241; Its pin 21 is electrically connected with parallel output interface 242, and its pin 22 is electrically connected with parallel output interface 243, and its pin 23 is electrically connected with parallel output interface 244; Its pin 24 is electrically connected with parallel output interface 245, and its pin 25 is electrically connected with parallel output interface 246, and its pin 5 is electrically connected with parallel output interface 247; Its pin 7 is electrically connected with parallel output interface 248, and its pin 8 is electrically connected with parallel output interface 249, and its pin 9 is electrically connected with parallel output interface 250; Its pin 10 is electrically connected with parallel output interface 251, and its pin 11 is electrically connected with parallel output interface 252, and its pin 12 is electrically connected with parallel output interface 253; Its pin 13 is electrically connected with parallel output interface 254; Its pin 17 is electrically connected with parallel output interface 255, and its pin 28 is electrically connected with parallel output interface 256, and its pin 39 is electrically connected with parallel output interface 257; Its pin 6 is electrically connected with parallel output interface 258, and its pin 26 is electrically connected with parallel output interface 259;
The pin 37 of described single chip circuit U1, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, pin 30 are electrically connected with pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, the pin 9 of single chip circuit U4 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U3 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U5 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U6 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U7 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U8 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U9 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U10 respectively; The pin 19 of single chip circuit U4, pin 18, pin 17, pin 16, pin 15, pin 14, pin 13, pin 12 are electrically connected with pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, the pin 30 of U11 respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205150863U CN202383670U (en) | 2011-12-12 | 2011-12-12 | Serial-to-parallel converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205150863U CN202383670U (en) | 2011-12-12 | 2011-12-12 | Serial-to-parallel converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202383670U true CN202383670U (en) | 2012-08-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205150863U Expired - Fee Related CN202383670U (en) | 2011-12-12 | 2011-12-12 | Serial-to-parallel converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202383670U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111371708A (en) * | 2020-04-28 | 2020-07-03 | 吴晓明 | Novel Morse code receiving and transmitting system |
-
2011
- 2011-12-12 CN CN2011205150863U patent/CN202383670U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111371708A (en) * | 2020-04-28 | 2020-07-03 | 吴晓明 | Novel Morse code receiving and transmitting system |
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