CN202364205U - Receiver circuit and device - Google Patents

Receiver circuit and device Download PDF

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Publication number
CN202364205U
CN202364205U CN2011202382040U CN201120238204U CN202364205U CN 202364205 U CN202364205 U CN 202364205U CN 2011202382040 U CN2011202382040 U CN 2011202382040U CN 201120238204 U CN201120238204 U CN 201120238204U CN 202364205 U CN202364205 U CN 202364205U
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China
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signal
circuit
filtering
sluggish
input signal
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CN2011202382040U
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Chinese (zh)
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曾妮
林大松
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STMicroelectronics Shenzhen R&D Co Ltd
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STMicroelectronics Shenzhen R&D Co Ltd
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Abstract

Disclosed are a receiver circuit and a device. The receiver circuit comprises a filter circuit, a first comparator and a driver block. The filter circuit is used for receiving input signals and generating filtered signals. The first comparator is used for comparing the filtered signals with threshold voltage. The driver block is used for generating receiver output signals. The receiver circuit also comprises an input comparator, a signal adjusting circuit and an amplitude limit circuit. The input comparator is used for detecting low voltage on the input signals. The signal adjusting circuit is used for driving the filtered signals toward a specific value so that the length of short time pulse waveform interference at the output place of the first comparator is shortened. Meanwhile, the amplitude limit circuit is used for detecting and removing the short time pulse waveform interference so that amplitude limiter output signals are generated. The amplitude limiter output signals are received by the driver block, and the receiver output signals are output by the driver block, wherein the receiver output signals do not include the short time pulse waveform interference and the delay does not exceed 7.5us, thereby providing anti-interference to ISO pulse.

Description

Receiver circuit and equipment
Technical field
The utility model relates generally to local internet (LIN) circuit, and relates more specifically to provide the LIN receiver to the vulnerability to jamming of interrupt source output (ISO) pulse.
Background technology
Local internet (LIN) realizes being used for the transmitter and receiver at this intra network communication usually.Receiver circuit is easy to receive the influence of the interference on the input signal, the receiver output that this interference can lead to errors.Particularly, receiver is easy to receive the influence of radio frequency (RF) pulse and ISO pulse, causes on receiver output signal, wrong low state occurring.In attempting the process that output slows down to the receiver of mistake, according to consistency (conformance) test with suitable emission Rule Design known receiver circuit the vulnerability to jamming to the RF pulse is provided.Yet these known receiver circuits still are easy to receive the influence of ISO pulse.Thus, have the demand to following LIN receiver circuit, this LIN receiver circuit produces the output signal that the influence to the ISO pulse that on the input signal of receiver, occurs has vulnerability to jamming.
The utility model content
The disclosure provides a kind of LIN receiver circuit that provides the vulnerability to jamming of ISO pulse.In one embodiment; The LIN receiver comprises comparator circuit; Operation is used for comparing through the input signal of filtering and first hysteresis threshold or second hysteresis threshold; And export sluggish signal, if said signal through filtering is less than or equal to said first hysteresis threshold then said sluggish signal has first state, and if said signal through filtering more than or equal to said second hysteresis threshold then said sluggish signal has second state; Operation is used to detect the circuit of low transient voltage of the input signal of non-filtered, and wherein said low transient voltage will produce the effective short-time pulse waveform interference (glitch) that continues very first time length on said sluggish signal; Voltage-regulating circuit, operation is used for adjusting said voltage of signals through filtering in response to the detection of said low transient voltage, shortens to second time span littler than said very first time length so that said effective short-time pulse waveform is disturbed; And amplitude limiter (deglitcher) circuit, operation is used for disturbing from said sluggish input and the effective short-time pulse waveform of removing said shortening, and generates the output signal.
In an optional execution mode according to the utility model; Amplitude limiter circuit comprises delay circuit; The delay circuit operation is used to receive sluggish signal and exports delayed signal; Delayed signal has the first delayed trailing edge after the trailing edge of sluggish signal, and wherein first trailing edge is postponed according to the 3rd time span littler than very first time length.
In an optional execution mode according to the utility model, the 3rd time span is more than or equal to second time span.
In an optional execution mode according to the utility model; Amplitude limiter circuit also comprises output circuit; The output circuit operation is used for when the effective short-time pulse waveform that does not detect shortening disturbs; Export sluggish signal as the output signal, and when the effective short-time pulse waveform that detects shortening disturbs, export delayed signal as the output signal.
In an optional execution mode according to the utility model, this circuit also comprises filter, and this filter is used to receive the input signal of non-filtered and produces the input signal through filtering.
In an optional execution mode according to the utility model, be used to detect the circuit that hangs down transient voltage and comprise comparator, this comparator operations is used to receive the input signal of non-filtered, and the input signal and first reference voltage of non-filtered compared.
In an optional execution mode according to the utility model; This voltage-regulating circuit comprises the adjustment circuit; This adjustment circuit operation is used to receive the enable signal of second reference voltage and the detection of the low transient voltage of indication; Wherein when detecting low transient voltage, this adjustment circuit will drive to second reference voltage through the input signal of filtering, and through the input signal of filtering less than second reference voltage.
In an optional execution mode according to the utility model, low transient voltage indication influences the interrupt source output pulse of the input signal of non-filtered.
In an optional execution mode according to the utility model, effectively the short-time pulse waveform interference is second state of the mistake on the sluggish signal.
In an optional execution mode according to the utility model, this circuit is the receiver circuit in the local internet.
In another embodiment, the LIN receiver circuit comprises comparator circuit, and the receiving inputted signal and first reference voltage, and output comparator signal are indicated the existence of the low transient voltage on the said input signal; Voltage-regulating circuit; Receive the said comparator signal and second reference voltage; And when there is said low transient voltage in the indication of said comparator signal on said input signal; Output adjustment electric current, when said input signal through filtering during less than said second reference voltage, said adjustment electric current will drive to said second reference voltage through the input signal of filtering; Hysteresis circuitry; Said input signal and first hysteresis threshold or second hysteresis threshold through filtering compared; And produce sluggish signal; If said input signal through filtering is less than or equal to said first hysteresis threshold then said sluggish signal has first state, and if said input signal through filtering more than or equal to said second hysteresis threshold then said sluggish signal has second state, wherein as the result of said low transient voltage; Said sluggish signal will have effective short-time pulse waveform to be disturbed; And wherein, said input signal through filtering is driven to said second reference voltage, shorten the length that the said effective short-time pulse waveform on the said sluggish signal disturbs through said adjustment electric current when said input signal through filtering during less than said second reference voltage; And amplitude limiter circuit, receive said sluggish signal and said comparator signal, and disturb through effective short-time pulse waveform of removing said shortening and to produce the output signal.
In an optional execution mode according to the utility model, low transient voltage indication influences the interrupt source output pulse of input signal.
In an optional execution mode according to the utility model, it is the second wrong state that the effective short-time pulse waveform on the sluggish signal disturbs.
In an optional execution mode according to the utility model, receiver circuit also comprises driver-level, and this driver-level receives the output signal from amplitude limiter circuit, and the output receiver circuit output signal.
In an optional execution mode according to the utility model, receiver circuit also comprises filter circuit, this filter circuit receiving inputted signal, and produce input signal through filtering.
In an optional execution mode according to the utility model, receiver circuit comprises the receiver in the local internet.
In an optional execution mode according to the utility model; When comparator signal is not indicated on the input signal when having low transient voltage; The output signal equals sluggish signal; When existing low transient voltage and sluggish signal to be first state on the comparator signal indication input signal, the output signal equals to have the sluggish signal of delayed trailing edge.
In an optional execution mode according to the utility model, delayed trailing edge is postponed according to the time quantum that disturbs more than or equal to the effective short-time pulse waveform that shortens.
In an optional execution mode according to the utility model, delayed trailing edge is postponed according to the time quantum less than effectively short-time pulse waveform interference.
The disclosure also provides a kind of equipment, and this equipment comprises: be used for input signal is carried out filtering to produce the device through the signal of filtering; Be used for the device that will compare through the signal of filtering and first hysteresis or second hysteresis; Be used to export the device of sluggish signal, if be less than or equal to first hysteresis then sluggish signal has first state through the signal of filtering, and if through the signal of filtering more than or equal to second hysteresis then sluggish signal has second state; Be used to detect the device of the low transient voltage on the input signal, wherein low transient voltage will produce the effective short-time pulse waveform that continues very first time length and disturb on sluggish signal; Be used for the detection in response to low transient voltage, adjustment is through the voltage of signals of filtering, effective short-time pulse waveform is disturbed the device that shortens to second time span littler than very first time length; Be used to detect the device of effective short-time pulse waveform interference of the shortening on the sluggish signal; And be used for removing effective short-time pulse waveform interference of shortening from sluggish signal, to produce the device of output signal.
In an optional execution mode according to the utility model, the device that is used to adjust through the voltage of signals of filtering also comprises: if be used for signal through filtering less than reference voltage, and then will be through the signal voltage of filtering device to the reference voltage adjustment.
In an optional execution mode according to the utility model; The device that is used to remove effective short-time pulse waveform interference of the shortening on the sluggish signal comprises: the device that is used to export calibrated signal; Calibrated signal has first trailing edge, and first trailing edge is postponed according to the 3rd time span littler than very first time length after the trailing edge of sluggish signal.
In an optional execution mode according to the utility model, the 3rd time span is more than or equal to second time span.
In an optional execution mode according to the utility model, low transient voltage indication influences the interrupt source output pulse of input signal.
In an optional execution mode according to the utility model, effectively short-time pulse waveform disturbs second state of the mistake that is sluggish signal.
In an optional execution mode according to the utility model, receiver circuit comprises the receiver in the local internet.
The disclosure also provides a kind of method, and this method comprises: input signal is carried out filtering to produce the signal through filtering; Said signal and first hysteresis or second hysteresis through filtering compared; Export sluggish signal; If said signal through filtering is less than or equal to said first hysteresis then said sluggish signal has first state, and if said signal through filtering more than or equal to said second hysteresis then said sluggish signal has second state; Detect the low transient voltage on the said input signal, wherein said low transient voltage will produce the effective short-time pulse waveform that continues very first time length and disturb on said sluggish signal; In response to the detection of said low transient voltage, adjust said voltage of signals through filtering, so that being disturbed, said effective short-time pulse waveform shortens to second time span littler than said very first time length; The effective short-time pulse waveform that detects the said shortening on the said sluggish signal disturbs; And disturb from the effective short-time pulse waveform that said sluggish signal is removed said shortening, to produce the output signal.
From the specific descriptions below in conjunction with the embodiment of advantages, aforementioned and further feature of the present disclosure and advantage will become more obvious.Specific descriptions and accompanying drawing just are used to explain the disclosure, rather than the scope of restriction the utility model, and the scope of the utility model is limited accompanying claims and equivalent thereof.
Description of drawings
Through the mode illustrative embodiment of example, wherein similarly reference number is indicated similar part in the accompanying drawing of not drawn on scale, and wherein:
Figure 1A, Figure 1B, Fig. 1 C and Fig. 1 D illustrate and are used to test the exemplary configuration that the RF pulse of injecting and ISO pulse are had the circuit of vulnerability to jamming, the exemplary embodiment and the corresponding timing parameters and the voltage level of LIN bus;
Fig. 2 A, Fig. 2 B, Fig. 2 C and Fig. 2 D illustrate the waveform of ISO pulse ISO1, ISO2a, ISO3a and ISO3b respectively;
Fig. 3 illustrates conventional LIN receiver circuit;
Fig. 4 A, Fig. 4 B and Fig. 4 C illustrate the waveform corresponding to the input signal that is received by conventional LIN receiver circuit shown in Figure 3;
Fig. 5 illustrates the exemplary embodiment of LIN receiver circuit of the present disclosure;
Fig. 6 A and Fig. 6 B illustrate the detailed view of the delay circuit that provides among Fig. 5 respectively and corresponding to the waveform of the input signal that receives at the delay circuit place;
Fig. 7 shows the detailed view of the adjustment circuit that in the receiver circuit shown in Fig. 5, provides;
Fig. 8 A and Fig. 8 B illustrate waveform and the comparison of the waveform of each assembly that does not have the shown in Figure 5 disclosed LIN receiver circuit of adjusting circuit of each assembly of the shown in Figure 5 disclosed LIN receiver circuit with adjustment circuit;
Fig. 9 shows the detailed view of the amplitude limiter circuit (deglitching circuitry) that in the receiver circuit shown in Fig. 5, provides;
Figure 10 A, Figure 10 B and Figure 10 C illustrate the exemplary circuit situation, with the operation of the amplitude limiter circuit shown in the exploded view 9;
Figure 11 shows the simulation result of the LIN receiver circuit that provides among Fig. 3, and this LIN receiver circuit has and when input signal is in recessiveness (recessive) state, appears at the ISO1 pulse on this input signal;
Figure 12 shows the simulation result of the LIN receiver circuit that provides among Fig. 5, and this LIN receiver circuit has the ISO1 pulse that when input signal is in recessive state, appears on this input signal;
Figure 13 shows the simulation result of the LIN receiver circuit that provides among Fig. 3, and this LIN receiver circuit has and when input signal is in dominance (dominant) state, recessive state and between recessive state and dominance condition, change, appears at the ISO3b pulse on this input signal; And
Figure 14 shows the simulation result of the LIN receiver circuit that provides among Fig. 5, and this LIN receiver circuit has and when input signal is in dominance condition, recessive state and between recessive state and dominance condition, change, appears at the ISO3b pulse on this input signal.
Embodiment
Under the supply voltage VBAT of 14V, test the receiver circuit of discussing here to the two vulnerability to jamming of RF pulse and ISO pulse.Exemplary test configurations 100 has been shown in Figure 1A.Test configurations 100 comprises receiver circuit to be tested 102, and wherein receiver circuit 102 is connected in series at LIN bus 103 places and resistor R i, capacitor C and interrupt source 104.Resistor R i is the internal resistor of interrupt source 104, and capacitor C is the coupling capacitor that is connected to LIN bus 103.In the exemplary embodiment, LIN bus 103 can be according to being described and illustrated LIN at the LIN Specification Package Revision 2.1 of distribution on November 24th, 2006 (through with reference to its content is incorporated into this) by LIN Consortium.Thus, in Figure 1B, illustrate the example of LIN bus 103 in more detail, and in Fig. 1 C, illustrate example waveform and the signal that is associated with exemplary L IN bus 103.
Test configurations 100 shown in Figure 1A is designed to the introducing interruption pulse (RF or ISO) at LIN bus 103 places.Interrupt source 104 provides this pulse to be injected in (LIN bus 103 places) receiver circuit 102, and wherein this pulse can be RF pulse or ISO pulse.The RF pulse is in 1MHz in the scope of 1000MHz, and the ISO pulse can be ISO1 pulse, ISO2a pulse, ISO3a pulse and ISO3b pulse.These pulses illustrate in greater detail and are summarized as follows in corresponding Fig. 2 A, Fig. 2 B, Fig. 2 C and Fig. 2 D.Generally speaking, test configurations 100 is operated through ISO pulse or RF pulse are injected in the LIN bus 103.As following illustrated, LIN bus 103 provides input signal LIN_bus to receiver circuit 102, and receiver circuit 102 produces receivers output signal RXD.The output signal RXD of analysis receiver circuit 102 has vulnerability to jamming to confirm the interruption pulse whether receiver circuit 102 is provided the interrupt source 104 by LIN bus 103 places then.
The example of LIN bus 103 has been shown in Figure 1B as stated.LIN bus 103 is provided at being connected between transmitter circuitry (not shown) and the receiver circuit 102 in the network such as vehicle-mounted (automotive) network.Fig. 1 C illustrates the timing parameters of the LIN bus 103 shown in Figure 1B; Wherein TXD is (same from transmitter circuitry; Not shown) input signal that receives, and LIN_bus is the open-drain output of transmitter circuitry, this also is applicable to the LIN input signal that offers receiver circuit 102.For correctly transmitting and receiving of bit, suppose at the bit sample time of receiver t Bit(t in one embodiment, Bit=50 μ s) the LIN_bus signal is available under locate the to have correct voltage level situation of (dominance or recessiveness).In Fig. 1 D, illustrate the dominance condition and the recessive state of LIN_bus signal, wherein V SUPExpression is for the builtin voltage power supply of the electronic building brick in the LIN 103.It will be appreciated that internal electric source V SUPCan be different with supply voltage VBAT.This possibly be the result that protecting filter element and dynamic electric voltage on the bus change.In addition, according to before coming design example property LIN circuit 103, so that satisfy suitable uniformity test through encapsulating the standard that provides in the revised edition 2.1 with reference to the LIN standard of incorporating into.
The chart 202 that Fig. 2 A illustrates exemplary ISO1 pulse 201 and describes its parameter.As in describing subsequently, will be able to conspicuous, when input signal LIN_bus was in recessive state, ISO1 pulse 201 was negative pulses, this negative pulse causes receiver to produce the low output of the mistake on the RXD.
The chart 204 that Fig. 2 B illustrates exemplary ISO2a pulse 203 and describes its parameter.When input signal LIN_bus when recessive state changes dominance condition into, ISO2a pulse 203 is positive pulses, this positive pulse causes receiver to produce the too early low output on the RXD.
The chart 206 that Fig. 2 C illustrates exemplary ISO3a pulse 205 and describes its parameter.ISO3a pulse 205 is negative pulses, and it is too fast so that the trailing edge that can't be detected that this negative pulse has possibility.Yet its rising edge is slower, so it has produced influence to the LIN_bus signal as positive pulse (being similar to the ISO2a pulse).Thus, make receiver produce the too early low output on the RXD when input signal LIN_bus ISO3a pulse 205 when recessive state is transformed into dominance condition.ISO3a pulse 205 is narrower than ISO1 pulse and ISO2a pulse shown in Fig. 2 A and Fig. 2 B, and can remove through inner filter sometimes.Yet these inner filters possibly be invalid for high-amplitude ISO3a pulse.Fig. 2 C also provides another waveform 207, and this waveform 207 shows the t shown in the chart 206 r, t dAnd U sParameter.
The chart 209 that Fig. 2 D illustrates exemplary ISO3b pulse 208 and describes its parameter.ISO3b pulse 208 is positive pulses, and it is too fast so that the rising edge that can't be detected that this positive pulse has possibility.Yet its trailing edge is slower, so it has produced influence to the LIN_bus signal as negative pulse (being similar to the ISO1 pulse).Thus, when input signal LIN_bus was in recessive state, ISO3b pulse 208 caused receiver to produce the low output of the mistake on the RXD.Be similar to the ISO3a pulse, ISO3b pulse 208 is narrower than ISO1 pulse and ISO2a pulse, and can remove through inner filter sometimes.Yet these inner filters possibly be invalid for high-amplitude ISO3b pulse.Fig. 2 D also provides another waveform 210, and this waveform 210 shows the t shown in the chart 209 r, t dAnd U sParameter.
The analysis of the output signal RXD that is produced by receiver circuit 102 comprises two rules of the vulnerability to jamming that is used to evaluate 102 pairs of ISO pulses of receiver circuit: destroy and function.If satisfy to destroy rule and function regular the two, then receiver circuit 102 provides the abundant vulnerability to jamming to the ISO pulse.Destroy usually and evaluate according to the voltage sustained periods of time that is connected to the device of LIN bus 103.Because ISO pulse and RF pulse possibly cause the rapid voltage fluctuation at LIN bus 103 places, so the device of coupling should be able to be handled these fluctuations and not destroy the LIN_bus signal with it.Although, can be independent of the function rule and evaluate this destruction to the destruction of other devices maybe to export signal RXD relevant with the ISO pulse that occurs on the LIN bus 103 and RF pulse and the receiver circuit that is produced.Therefore,, receiver circuit disclosed herein is interpreted as the satisfied rule of destroying, and evaluates the receiver output signal RXD of receiver circuit disclosed herein according to the function rule for showing purpose to the vulnerability to jamming of ISO pulse and RF pulse.
The evaluation of function is dual.At first, not having the receiver output signal RXD of injected pulse should be less than 7.5 μ s with the time difference that the receiver with injected pulse is exported between the signal RXD (being also referred to as the RXD signal of interruption here).In other words, when the ISO pulse was injected, the output signal RXD of receiver circuit 102 should not postpone to surpass 7.5 μ s.Secondly, the RXD voltage of signals level of interruption should not meaned that short-time pulse waveform disturbs (glitch) should not be present on the output signal RXD by erroneous trigger.If these two conditions all satisfy, then assessment of function is successful.Possibly not illustrate the test configurations shown in Figure 1A although it should be understood that subsequent figures, test configurations can be applied to the various embodiment of receiver circuit so that suitable vulnerability to jamming test is provided.
Fig. 3 illustrates the conventional LIN receiver circuit 300 that is coupled to pull-up circuit 302 and data/address bus LIN input pin 303, and wherein receiver circuit 300 is supplied power by battery supply VBAT.Receiver 300 is corresponding to the receiver circuit among Figure 1A 102 and comprise the LIN input signal LIN_bus that is received from data/address bus input pin 303, the RC filter 304 through the LIN of filtering signal LIN_filter, the driver block 308 that produces sluggishness (hysteresis) comparator 306 of logic output signal RXI and receiver output signal RXD is provided are provided.
RC filter 304 comprises resistor R 1 and capacitor C1.RC filter 304 receives LIN input signal LIN_bus from input pin 303, and this signal is carried out filtering produces the input signal LIN_filter through filtering with input place at hysteresis comparator 306.
The input signal LIN_filter that hysteresis comparator 306 receives through filtering from RC filter 304 in first input place compares it with the threshold voltage vt h that receives in second input place, and produces logic output signal RXI.Threshold voltage vt h shown in Figure 3 represents high threshold voltage Vth (high) or low threshold voltage Vth (low).Those of ordinary skills it will be appreciated that comparator circuit can convert following hysteresis circuitry to, and this hysteresis circuitry is designed to make that input (for example Vth) can be one of two different values (for example Vth (high) or Vth (low)).Hysteresis comparator 306 provides has higher threshold voltage Vth (high) and than the lag function of low threshold voltage Vth (low).When input signal LIN_bus becomes dominance condition, drop to the voltage of being less than or equal to Vth (low) through the input signal LIN_filter of filtering, and comparator output signal RXI step-down.When input signal LIN_bus becomes recessive state, rise to the voltage that is greater than or equal to Vth (high) through the input signal LIN_filter of filtering, and comparator output signal RXI uprises.Further specify foregoing below in conjunction with Fig. 4 A, Fig. 4 B and Fig. 4 C.
Driver block 308 is from hysteresis comparator 306 RLs output signal RXI and produce receiver output signal RXD.Driver block 308 is used as the driver-level of receiver circuit 300 and comprises non-(NOT) door 310 and transistor 312, and transistor 312 provides open-drain (open-drain) output of receiver output signal RXD.Driver block 308 is coupled to pull-up circuit 302; Wherein pull-up circuit 302 comprises pullup resistor 314 and external voltage power supply 316; Pullup resistor 314 will be exported signal RXD and force at the open-drain place, and external voltage power supply 316 plays the effect of the level shift between internal logic supply voltage and external logic supply voltage.When RXI signal when being high, the grid of transistor 312 ends, mean transistor 312 by and RXD equal external voltage power supply 316.When the RXI signal when low, the gate turn-on of transistor 312, and transistor 312 is pulled to ground connection with the RXD signal.
RC filter 304 provides the suitable vulnerability to jamming that radio frequency (RF) pulse is injected with hysteresis comparator 306 for receiver 300 shown in Figure 3; Yet, being described below, circuit 300 is subject to the infringement of ISO pulse (for example ISO1, ISO3b etc.).When the ISO pulse was injected in the LIN input pin 303, input signal LIN_bus was driven to lower voltage value usually, generally was lower than ground connection (seeing Fig. 4 B and Fig. 4 C).If the ISO pulse when input signal LIN_bus is in dominance condition, occurs; Then be in Vth (low) threshold voltage or be lower than Vth (low) threshold voltage, so comparator output signal RXI generally can not influence receiver output signal RXD for low and ISO pulse through the input signal LIN_filter of filtering.Yet; If when input signal LIN_bus be in recessive state (seeing Fig. 4 B) or be between recessive state and the dominance condition transformation (promptly; When the LIN_bus signal ISO pulse and correct comparator output signal RXI occur still for high when recessive state falls into dominance condition---see Fig. 4 C) time ISO pulse appears; Then the ISO pulse makes below the input signal LIN_filter of filtering drops to than low threshold voltage Vth (low) prematurely; Thereby make logic output signal RXI step-down by error, cause too early low receiver output signal RXD.The low state of the mistake that on receiver output signal RXD and logic output signal RXI, occurs (time period that too early low state perhaps wherein occurs) is that the short-time pulse waveform of being considered disturbs.
Fig. 4 A, Fig. 4 B and Fig. 4 C are provided for illustrating above-mentioned disclosure; Wherein Fig. 4 A illustrates the operation of the receiver circuit 300 of the ISO pulse with any injection; Fig. 4 B illustrates the operation of the receiver circuit 300 of the ISO pulse with the injection when appearing at input signal LIN_bus and being in recessive state, and Fig. 4 C illustrates the operation of the receiver circuit 300 of the ISO pulse with the injection when appearing at input signal LIN_bus and being in the transformation between recessive state and the dominance condition.Fig. 4 A shows exemplary L IN_bus waveform 402, exemplary L IN_filter waveform 404 and exemplary RXI/RXD waveform 406.In the embodiment shown in fig. 3, RXI signal and RXD signal have same waveform as and therefore in Fig. 4 A, Fig. 4 B and Fig. 4 C, are shown as single RXI/RXD waveform.When input signal LIN_bus waveform 402 changes, also change through the input signal LIN_filter of filtering waveform 404.As stated; Hysteresis comparator 306 provides lag function; Wherein when through the input signal LIN_filter of filtering waveform 404 during more than or equal to higher threshold voltage Vth (high) RXI/RXD waveform 406 uprise, and when being less than or equal to than low threshold voltage Vth (low) through the input signal LIN_filter of filtering waveform 404 RXI/RXD waveform 406 step-downs.
Fig. 4 B illustrates exemplary input signal LIN_bus waveform 408, and it has the ISO pulse 410 that when input signal LIN_bus is in recessive state, occurs.Through rise to more than the high threshold voltage Vth (high) once more at LIN_filter signal 412 before, LIN_filter signal 412 is driven into below the low threshold voltage Vth (low), thereby ISO pulse 410 is reflected in the LIN_filter signal waveform 412.When ISO pulse 410 is driven into low threshold voltage Vth (low) when following with LIN_filter signal 412, cause the inaccurate low output 414 of RXI/RXD waveform 416 in a period of time (that is, short-time pulse waveform disturbs).Because short-time pulse waveform disturbs 410 to be present on the RXD waveform 416, so receiver circuit 300 can not be realized at least one in the functional conditions.So, receiver circuit 300 shown in Figure 3 can't provide the vulnerability to jamming to the ISO pulse to when input signal LIN_bus is in recessive state, occurring.
Fig. 4 C illustrates exemplary input signal LIN_bus waveform 418, and it has the ISO pulse 420 that when recessive state is converted to dominance condition, occurs as input signal LIN_bus.Through the point 424 places the LIN_filter signal is driven into prematurely below the low threshold voltage Vth (low), thereby ISO pulse 420 is reflected in the LIN_filter signal waveform 422.As shown in the corresponding RXI/RXD waveform 426, reaching too early of low threshold voltage Vth (low) causes RXI/RXD signal step-down prematurely.Once more with reference to LIN_filter signal waveform 422; After ISO pulse 420 occurs; LIN_filter signal waveform 422 rise once more with reach its expection signal path (promptly; The signal path that occurs is in addition had the ISO pulse that is not present on the input signal LIN_bus), wherein it reaches low voltage threshold Vth (low) at point 428 places.Therefore, correct RXI/RXD signal will be at point 428 places rather than at point 424 place's step-downs.So, RXI/RXD waveform 426 is included in a little 424 and put the low state 430 of the mistake (too early) between 426 at time period T '.Because short-time pulse waveform disturbs 430 to be present on the RXD waveform 426, so receiver circuit 300 can not reach at least one in the functional conditions equally.So, receiver circuit 300 shown in Figure 3 can't provide the vulnerability to jamming to the ISO pulse that when recessive state is converted to dominance condition, occurs as input signal LIN_bus.
The disclosure provides a kind of LIN receiver circuit, and this LIN receiver circuit provides the vulnerability to jamming to the ISO pulse.Fig. 5 illustrates the exemplary embodiment according to LIN receiver circuit 500 of the present disclosure, and wherein receiver circuit 500 is coupled to pull-up circuit 502 and data/address bus LIN input pin 503 (being also referred to as LIN input pin or input pin here).The circuit that disclosed receiver circuit 500 comprises is similar to and comprises shown in Figure 3 and circuit above-described receiver 300.For example; Disclosed receiver circuit 500 is supplied power by battery supply VBAT; Receive LIN input signal LIN_bus from LIN bus 503; And comprise RC filter 504, hysteresis comparator 506 and driver block 508; This RC filter 504 receives LIN input signal LIN_bus and produces through the LIN of filtering signal LIN_filter, and hysteresis comparator 506 receives the LIN_filter signal, itself and threshold voltage vt h are compared and produce logic output signal RXI, and driver block 508 produces receiver output signal RXD.RC filter 504 is similar to aforesaid RC filter 304 such operations.
Hysteresis comparator 506 is similar to the operation of aforesaid comparator 306 ground.So, hysteresis comparator 506 provides has higher threshold voltage Vth (high) and than the lag function of low threshold voltage Vth (low), wherein higher threshold voltage Vth (high) and in Fig. 5, be expressed as Vth than low threshold voltage Vth (low).Although higher threshold voltage Vth (high) and can change according to various design preference than low threshold voltage Vth (low); But in the exemplary embodiment shown in Fig. 5; Higher threshold voltage Vth (high) equals 0.55*VBAT, equals 0.45*VBAT than low threshold voltage Vth (low).Therefore, when when the LIN of filtering signal LIN_filter is equal to or greater than Vth (high), logic output signal RXI uprises.On the contrary, when when the LIN of filtering signal LIN_filter is less than or equal to Vth (low), logic output signal RXI step-down.It will be appreciated that the value to threshold voltage vt h (high) and Vth (low) distribution is an example here, threshold voltage vt h (high) and Vth (low) are not limited to example value disclosed herein.
Driver block 508 is similar to the operation of aforesaid IOB 308 ground.So, driver block 508 is used as the driver-level of receiver circuit 500, and comprises the transistor 510 of NOT door 509 and the open-drain output that receiver output signal RXD is provided.Driver block 508 is coupled to pull-up circuit 502; Wherein pull-up circuit 502 comprises pullup resistor 511 and external voltage power supply 512; Pullup resistor 511 will be exported signal RXD and force at the open-drain place, and external voltage power supply 512 plays the effect of the level shift between internal logic supply voltage and external logic supply voltage.In exemplary embodiment shown in Figure 5, external voltage power supply 512 can be about 3V-5V, thereby plays the effect of the level shifter between the external circuit (not shown) of voltage source VBAT and reception receiver output signal RXD.It will be appreciated that the voltage at external voltage power supply 512 places is example values, and this exemplary voltage value is not intended to limit the scope of the present disclosure.
Except foregoing circuit, receiver circuit 500 shown in Figure 5 also comprises input comparator 514, signal adjustment circuit 516 and amplitude limiter circuit 518.Usually, input comparator 514 determines when LIN pin 503 is driven into low voltage value (possibly pass through the ISO pulse).Confirm that in response to this signal adjustment circuit 516 can be driven into the particular value bigger than the voltage at LIN_bus place with the LIN_filter signal, shorten the time span of output error value on the RXI signal (being that short-time pulse waveform disturbs) thus.Simultaneously, the short-time pulse waveform that amplitude limiter circuit 518 detects on the RXI disturbs, and produces amplitude limiter output signal RXO.Amplitude limiter output signal RXO is received by driver block 508, driver block 508 output receivers output signal RXD.In order to satisfy the functional conditions of ISO vulnerability to jamming test, receiver output signal RXD does not comprise the short-time pulse waveform interference and time shift (that is, postponing) is no more than 7.5 μ s.So, LIN receiver circuit 500 of the present disclosure provides the two vulnerability to jamming of ISO pulse and RF pulse.
Input comparator 514 operations are used for when dropping to the existence that detects the ISO pulse below the predetermined voltage Vin through the voltage of confirming input pin 503 places.Predetermined voltage Vin can be set at specific low voltage value (for example negative value), make when LIN_bus drop to scheduled voltage Vin when following deduction ISO pulse occur.As shown in Figure 5, input comparator 514 receives LIN input signal LIN_bus from input pin 503, and LIN input signal LIN_bus and scheduled voltage Vin are compared.Input comparator 514 produces logic output signal MD then, and whether LIN_bus is greater than scheduled voltage Vin in indication.For example, for Vin=-2.5V, input comparator 514 compares LIN_bus and-2.5V.If LIN_bus＞-2.5V, MD=0 then, if LIN_bus＜-2.5V, then MD=1.It should be understood that the scheduled voltage Vin that provides at input comparator 514 places can select according to various factors.For example, scheduled voltage Vin can be set at particular value so that satisfy the requirement of battery in the uniformity test/ground connection displacement.
The driven that signal adjustment circuit 516 operation is used for when input comparator 514 detects existing of ISO pulse LIN_filter (in extremely first input place of sluggish comparator 506) is a specific voltage.Generally speaking, this compulsory magnitude of voltage (VREF is described below) is chosen as the scheduled voltage Vin that connects greater than in input place to input comparator 514.For example, according to the example of front, if Vin=-2.5V, then LIN_filter can be forced 0.5*VBAT, wherein VBAT=14V.In fact, be forced to higher value, reduced the LIN_filter signal and recovered perhaps to equal more precisely the required time quantum of high threshold voltage Vth (high) (thereby on RXI, producing correct high state) through voltage with the LIN_filter place.In this example, replace returning to Vth (high) from-2.5V, the LIN_filter signal returns to Vth (high) from 0.5*VBAT effectively.In fact, the adjustment of LIN_filter signal has been eliminated the LIN_filter signal and has been returned to 0.5*VBAT with consumed time from-2.5V.So, signal adjustment circuit 516 has shortened the time span that on logic output signal RXI, occurs mistake as the result of ISO pulse effectively.Particularly; Selection coercive voltage value VREF makes it shorten the mistake on the RXI effectively so that kind of following more specifically explanation is passed through amplitude limiter circuit 518 detections and removal mistake, thereby mistake does not appear on amplitude limiter output signal RXO or the receiver output signal RXD.
Signal adjustment circuit 516 comprises delay circuit 520, and this delay circuit 520 receives input comparator output signal MD and to adjustment circuit 522 enable signal EN_MP is provided.In certain embodiments, if the rising edge of enable signal EN_MP does not have to postpone the time period greater than 1.0 μ s, then can trigger adjustment circuit 522 by accident through the RF pulse in the 1MHz-1000MHz scope.Therefore, in the exemplary embodiment shown in Fig. 6 A and Fig. 6 B, delay circuit 520 comprises first signal delay circuit 610 that is used for the about 1.2 μ s of the rise edge delay of enable signal EN_MP.Additionally, because the signal LIN_filter through filtering of output place of 516 pairs of RC filters 504 of signal adjustment circuit is responsive, so the trailing edge of enable signal EN_MP allows to be postponed through the stable time quantum of the signal LIN_filter of filtering being enough to.So, delay circuit 520 also comprises the secondary signal delay circuit 620 (present embodiment hypothesis LIN_filter signal is stable less than 3.0 μ s the time) that is used for the trailing edge of enable signal EN_MP is postponed about 3.0 μ s.The output of first signal delay circuit 610 and secondary signal delay circuit 620 be to or (OR) input of door 630, this OR door 630 produces enable signal EN_MP.
Fig. 6 B illustrates the waveform according to the exemplary L IN_bus input signal 640 of the delay circuit 520 shown in Fig. 6 A, exemplary input comparator output signal MD 642 and exemplary enable signal EN_MP 644.Waveform among Fig. 6 B is provided the effect that property waveform as an example is used for the delay circuit 520 that pictorial image 6A provides.When LIN_bus input signal 640 is lower than the scheduled voltage Vin that input place at input comparator 514 provides (shown in Fig. 6 B mid point 645); Input comparator output signal MD 642 uprises, and first signal delay circuit 610 is with the rise edge delay 1.2 μ s of enable signal EN_MP 644.When LIN_bus input signal 640 rises to scheduled voltage Vin when above (shown in Fig. 6 B mid point 650), input comparator output signal MD 642 step-downs, and secondary signal delay circuit 620 postpones 3 μ s with the trailing edge of enable signal EN_MP 644.Those of ordinary skills it will be appreciated that; Here provide the time of delay that provides and be used for illustrating and describing the exemplary time of the present disclosure; And this time of delay can be according to some factors vary, and these some factors include but not limited to signal delay time between frequency and the circuit inner assembly of time width parameter, RF pulse of ISO pulse.
Fig. 7 provides the more detailed icon of adjustment circuit 522 shown in Figure 5.The operation of adjustment circuit 522 is used to receive and can be applied to through the input signal LIN_filter of filtering (a) from the enable signal EN_MP of delay circuit 520 and (b) reference voltage VREF (above briefly mention).When enable signal EN_MP is low, adjustment circuit 522 and un-activation, and thereby the input signal LIN_filter through filtering is not produced any adjustment.Additionally, if when enable signal EN_MP uprises through the input signal LIN_filter of filtering greater than reference voltage VREF, then the input signal LIN_filter through filtering is not adjusted.Yet, if enable signal EN_MP uprises and through the input signal LIN_filter of filtering less than reference voltage VREF, the electric current through transistor M4 and diode D2 makes reference voltage VREF be applied to the input signal LIN_filter through filtering.Correspondingly, adjustment circuit 522 will be forced to through the input signal LIN_filter of filtering adjustment perhaps " on draw " to the value of reference voltage VREF.The effect of adjustment circuit 522 is described below in conjunction with the waveform that provides among Fig. 8 A and Fig. 8 B in more detail.
Fig. 8 A and Fig. 8 B partly are provided for illustrating 522 pairs in when the ISO pulse appears at input signal LIN_bus and the is in recessive state adjustment circuit effects through the input signal LIN_filter of filtering and corresponding RXI signal.Fig. 8 A illustrates the exemplary input signal LIN_bus waveform 802 with the ISO1 pulse 804 of during recessive state, injecting, the input comparator of correspondence is exported the RXI signal waveform 812 through the input signal LIN_filter of filtering waveform 810 and correspondence of signal MD waveform 806, enable signal EN_MP waveform 808, correspondence.The waveform that provides among Fig. 8 A is designed to illustrate receiver circuit 500 and under the situation of not adjusting circuit 522, will how operates.Fig. 8 B illustrates the waveform identical with Fig. 8 A, but the waveform among Fig. 8 B is corresponding to LIN receiver circuit 500 of the present disclosure shown in Figure 5, and thereby the effect of diagram adjustment circuit 522.
At Fig. 8 A and Fig. 8 B in the two; When input signal LIN_bus waveform 802 drops to scheduled voltage Vin when following; Input comparator output signal MD uprises (existing with signalisation ISO pulse in fact); In case and input signal LIN_bus waveform 802 surpasses Vin then, input comparator output signal MD is step-down once more.According to above-mentioned discussion, when MD waveform 806 uprised, enable signal EN_MP waveform 808 postponed to uprise behind the D1 first.When the MD step-down, enable signal EN_MP waveform 808 is step-down behind the second delay D2.
As previously mentioned, the waveform shown in Fig. 8 A is corresponding to the exemplary embodiment of the LIN receiver that does not have adjustment circuit 522.Therefore, do not disturbed 814, wherein T=3.8 μ s for example by the short-time pulse waveform that adjustment and RXI signal waveform 812 do not produce on the present time section T through the input signal LIN_filter of filtering waveform 810 (shown in Fig. 8 A).Because the waveform shown in Fig. 8 B is corresponding to the LIN receiver circuit 500 of the present disclosure with adjustment circuit 522, so when enable signal EN_MP waveform 808 uprises, adjusted through the input signal LIN_filter of filtering waveform 810 (shown in Fig. 8 B).When enable signal EN_MP waveform 808 uprises, through the input signal LIN_filter of filtering waveform 810 less than reference voltage level VREF.Therefore, adjustment circuit 522 will drive for reference voltage level VREF, shown in reference number 816 through the input signal LIN_filter of filtering., also adjusted and dropped to Vth (low) below and the RXI point of step-down (referring to reference number 818) and through time of point (referring to the reference number 820) appearance that the input signal LIN_filter of filtering rises to more than the Vth (high) and RXI uprises subsequently subsequently through the input signal LIN_filter of filtering through adjustment from input signal LIN_filter through filtering.As reference voltage level VREF under the situation about uprising during greater than the voltage at LIN_filter place at enable signal EN_MP, then appear at a little 818 and the time span put between 820 shorten.Correspondingly, the length of the short-time pulse waveform interference 814 that on RXI waveform 812, occurs also shortens to time period P, wherein P＜T=3.8 μ s.Shown in Fig. 8 B, adjustment circuit 522 has shortened the short-time pulse waveform that on RXI signal 812, occurs effectively and has disturbed 814 length.
As stated, the hysteresis comparator 506 in disclosed LIN receiver circuit 500 is similar to the operation of the hysteresis comparator 306 that provides among Fig. 3.Hysteresis comparator 506 receives input signal LIN_filter through filtering, itself and threshold voltage vt h is compared and produce logic output signal RXI.Logic output signal RXI is received by amplitude limiter circuit 518 then, and wherein amplitude limiter circuit 518 operations are used to detect the short-time pulse waveform interference that on the RXI signal, is produced by the ISO pulse, and produces amplitude limiter output signal RXO.Generally speaking; When amplitude limiter circuit 518 detects the short-time pulse waveform interference on the RXI signal; Amplitude limiter circuit 518 is hanged down output (promptly through the trailing edge with the RXI signal with the mistake that is enough to effectively remove on the RXI; The short-time pulse waveform interference) time quantum postpones, and comes to remove short-time pulse waveform from the RXI signal and disturbs.Below in conjunction with Fig. 9, Figure 10 A, Figure 10 B and Figure 10 C the detailed description to amplitude limiter circuit 518 is provided.
Fig. 9 provides the detailed icon to the amplitude limiter circuit 518 that in receiver circuit 500 shown in Figure 5, provides.Amplitude limiter circuit 518 receiving inputted signal ENABLE, RXI and MD, wherein ENABLE is the enable signal that is used for amplitude limiter circuit 518, and RXI is hysteresis comparator 506 output signals, and MD is input comparator 514 output signals.Amplitude limiter circuit 518 output choppers output signal RXO, wherein amplitude limiter output signal RXO can be the original perhaps delayed RXI signal RXI_delay (disturbing if on RXI, detect short-time pulse waveform) of RXI signal (if not existing short-time pulse waveform to disturb on the RXI).
Receive the RXI signal at delay circuit 902 places, wherein delay circuit 902 postpones 3.8 μ s to produce the RXI_delay signal, shown in Figure 10 A with the trailing edge of RXI signal.Be designed to following time quantum the time of delay that provides by delay circuit 902; This time quantum is enough to make the RXI_delay signal to have following trailing edge, and this trailing edge is postponed the enough time and compensate the low output of mistake (this combines Figure 10 B further to discuss below) that the result as the ISO pulse occurs on the RXI signal.According to the above-mentioned and illustrated embodiment of combination Fig. 8 B, the contraction in length that the short-time pulse waveform that signal adjustment circuit 516 will occur on RXI disturbs is time period P, wherein P＜T=3.8 μ s; Therefore, in the present embodiment, be set at 3.8 μ s the time of delay of delay circuit 902.Because receiver output signal RXD equals amplitude limiter output signal RXO; And amplitude limiter output signal RXO can equal the RXI_delay signal; So it should be understood that the direct delay that can cause the RXD signal time of delay in some cases that provides by delay circuit 902.Therefore, in order to satisfy output signal RXD condition time of delay of the function rule be used for confirming ISO pulse vulnerability to jamming, by the time of delay that delay circuit 902 provides should be greater than 7.5 μ s.It should be understood that the 3.8 μ s that provided by delay circuit 902 postpone to be provided the exemplary time quantum as being enough to compensate the short-time pulse waveform interference that on the RXI signal, occurs.Correspondingly, in certain embodiments, delay circuit 902 can provide less than other time of delay of about 7.5 μ s (as long as should keep enough being used for the short-time pulse waveform interference compensation time of delay).
Input pin place at trigger 904 also receives the RXI signal, wherein the operation of trigger 904 and therefore amplitude limiter circuit 518 by the ENABLE signal enabling.Trigger 904 receives input comparator output signal MD at its clock pin place, and produces signal EN_GLITCH.The EN_GLITCH signal is received at MUX 906 places and is used to select suitable amplitude limiter to export signal RXO.Be defaulted as RXO=RXI.Therefore, if EN_GLITCH=0, then MUX 906 selects RXO=RXI, and if EN_GLITCH=1, then MUX 906 selects RXO=RXI_delay.Generally speaking, when amplitude limiter circuit 518 starts, be height and b at a) RXI) when input comparator output signal MD uprised, the EN_GLITCH signal uprised.Additionally, the rising edge subsequently of working as a) RXI signal occur (for example) in the end that short-time pulse waveform disturbs or b) the RXI_delay signal trailing edge occurs subsequently the time, the EN_GLITCH step-down.It should be understood that when RXI when low, input signal LIN_bus is in dominance condition or changes recessive state into from dominance condition.When this happens, the ISO pulse makes the LIN_bus signal descend, but will can not cause the short-time pulse waveform on RXI to disturb, because RXI has been low.Therefore, circuit 500 of the present disclosure does not relate to this situation.Further describe the operation of amplitude limiter circuit shown in Figure 9 518 below according to the exemplary circuit condition shown in Figure 10 A, Figure 10 B and Figure 10 C.
Figure 10 A illustrates the exemplary RXI signal and corresponding RXI_delay signal that is produced by delay circuit shown in Figure 9 902.Shown in Figure 10 A, the RXI_delay signal has the rising edge 1002 that occurs at 1004 essentially identical time of the rising edge place with the RXI signal, and has the trailing edge 1006 that 3.8 μ s occur in trailing edge 1008 backs of RXI signal.As described above, the delayed trailing edge 1006 of RXI_delay signal is designed to surpass the time span P of any short-time pulse waveform interference that on the RXI signal, occurs.Although in Figure 10 B and Figure 10 C, do not spell out, it will be appreciated that the trailing edge of RXI_delay signal is postponed 3.8 μ s about the trailing edge of its corresponding RXI signal.
Figure 10 B illustrates the EN_GLITCH signal and the amplitude limiter output signal RXO of exemplary RXI signal, corresponding RXI_delay signal, exemplary input comparator output signal MD, correspondence to the example (being similar to the condition shown in Fig. 8 B) that the ISO pulse wherein during the recessive state of input signal, occurs.Shown in Figure 10 B, the RXI signal has the short-time pulse waveform disturbed one 010 (that is the low state of mistake) that appears on the time period P (wherein P＜3.8 μ s).In example shown in Figure 10 B, the EN_GLITCH signal have with 1014 essentially identical times of the rising edge of the MD signal rising edge 1012 that occurs of place and with the trailing edge 1016 that occurs of place of essentially identical time of the rising edge 1018 (in the end of short-time pulse waveform disturbed one 010) of RXI signal.When EN_GLITCH when low, RXO=RXI, and as EN_GLITCH when being high, RXO=RXI_delay.Shown in Figure 10 B, because postponing the length P of 3.8 μ s and short-time pulse waveform disturbed one 010, the trailing edge of RXI_delay signal is shorter than 3.8 μ s, so short-time pulse waveform disturbed one 010 is not apparent in the RXI_delay signal.Therefore, be present in the time durations on the RXI at short-time pulse waveform disturbed one 010, the EN_GLITCH signal is high, and RXO=RXI_delay.So, amplitude limiter output signal RXO provides in fact through filtering or through the RXI of amplitude limit signal version.Therefore, shown in Figure 10 B, disclosed receiver circuit 500 provides the vulnerability to jamming to the ISO pulse that during the recessive state of input signal LIN_bus, occurs.
Figure 10 C illustrates the example that the ISO pulse wherein input signal LIN_bus changes the time period of dominance condition into from recessive state during, occurs.In this example, Figure 10 C illustrates exemplary L IN_bus signal waveform 1020, corresponding MD signal waveform 1022, adjustment circuit enable signal EN_MP waveform 1024, LIN_filter waveform 1026, RXI signal waveform 1028, corresponding RXI_delay signal waveform 1030, EN_GLITCH signal waveform 1032 and amplitude limiter exported signal RXO waveform 1034.The LIN_bus signal has exemplary ISO pulse 1036, makes the MD signal uprise, and makes that the EN_MP signal uprises after first postpones.Through making the LIN_filter signal descend too early (this causes the too early trailing edge 1038 on RXI signal waveform 1028), and pulse 1036 is reflected on the LIN_filter signal waveform 1026.According to Fig. 9, when the MD signal uprised, the EN_GLITCH signal also uprised, because RXI this moment also is high.EN_GLITCH signal waveform 1032 remains height, uprises or b up to a) RXI signal) till the RXI_delay signal step-down; Therefore when RXI_delay signal waveform 1030 during at trailing edge 1040 place step-downs, EN_GLITCH signal waveform 1032 is at trailing edge 1042 place's step-downs.Shown in Figure 10 C, when EN_GLITCH signal waveform 1032 when low, RXO waveform 1034 equals RXI, and when EN_GLITCH signal waveform 1032 when being high, RXO waveform 1034 equals RXI_delay.
In the embodiment shown in Figure 10 C, adjustment circuit 522 is forced to VREF at point 1044 places with LIN_filter signal waveform 1026.Yet, because VREF is less than Vth (high), so that RXI signal waveform 1028 remains is low.Therefore; RXI signal waveform 1028 is included in the too early low state that its trailing edge 1038 places occur; Wherein this too early low state is wrong low state; The starting point of the low state of this mistake is at trailing edge 1038 places, and its end point is difficult to detect under the situation of the rising edge that is not caused by adjustment circuit 522.Yet because the beginning of too early low state is normally known, so EN_GLITCH signal waveform 1032 uprises when the MD signal uprises, and the RXO signal equals RXI_delay, till trailing edge 1040 appearance of RXI_delay signal waveform 1030.In the present example, the delay of correct output signal RXO equals 3.8 μ s-T ', and wherein T ' is the length of hanging down state too early.In other words; T ' equals the time quantum between following two points; One of them point is will be driven into the point below the Vth (low) through the LIN_filter of filtering signal by ISO pulse 1036, and another point is if ISO pulse 1036 do not occur then will drop to the point below the Vth (low) through the LIN_filter of filtering signal.ISO pulse therein 1036 does not cause that short-time pulse waveform disturbs in the situation of (that is, T '=0), and the maximum duration section that correct RXO signal can postpone will be 3.8 μ s.This situation for example can comprise following situation, wherein ISO pulse 1036 make the LIN_filter signal reach Vth (low) if, there is not the ISO pulse in the while then the LIN_filter signal will reach Vth (low).Because the situation of this worst condition causes the delay of 3.8 μ s; And 3.8 μ s postpone restriction less than 7.5 μ s, so disclosed receiver circuit 500 also provides the vulnerability to jamming to the ISO pulse that when recessive state changes dominance condition into, occurs as input signal LIN_bus.
With reference to Fig. 5, in case receive amplitude limiter output signal RXO from amplitude limiter circuit 518, driver block 508 is with regard to output receiver output signal RXD once more.When RXO=1, the grid of transistor 510 ends, and means that transistor 510 ends and RXD equals external voltage power supply 512.When RXO=0, the gate turn-on of transistor 510 and transistor 510 are pulled to ground connection with RXD.According to foregoing, it is regular with function that receiver output signal RXD satisfies the destruction rule that is used for confirming to the vulnerability to jamming of ISO pulse.As previously mentioned, think that receiver circuit 500 satisfies the destruction evaluation.Because receiver output signal RXD does not comprise the low state of mistake and does not postpone to surpass 7.5 μ s, so satisfy assessment of function yet.So, receiver circuit 500 of the present disclosure provides the sufficient vulnerability to jamming to the ISO pulse.
Figure 11-Figure 14 provides the simulation result of the operation of the receiver circuit of the present disclosure 500 that provides among the receiver circuit 300 that provides in the pictorial image 3 and Fig. 5.Figure 11 show when input signal LIN_bus is in recessive state, on input signal LIN_bus, occur under ISO1 pulse 1102 situation, the simulation result 1100 of circuit 300 among Fig. 3.In this emulation (and emulation shown in Figure 12), the amplitude of ISO1 pulse is set at-100V, and this is the situation of the worst condition of ISO1 pulse.According to above-mentioned open, simulation result 1100 shows that the receiver circuit 300 among Fig. 3 produces wrong low output 1104 on the RXD signal, and thereby the ISO1 pulse that during the recessive state of input signal LIN_bus, occurs is not had vulnerability to jamming.
Figure 12 shows the simulation result 1200 of the disclosed receiver circuit 500 that provides among Fig. 5, and this receiver circuit has the ISO1 pulse 1202 that when input signal LIN_bus is in recessive state, on input signal LIN_bus, occurs.The condition of this emulation is similar to the condition that provides among Figure 11, so that can compare the output signal RXD in each emulation.The simulation result 1200 that provides among Figure 12 shows that the receiver circuit 500 among Fig. 5 does not produce wrong low state on the RXD signal, and RXD signal delay is not surpassed 7.5 μ s.Therefore, the ISO1 pulse that during the recessive state of input signal LIN_bus, occurs of 500 pairs of receiver circuits has vulnerability to jamming.
Figure 13 shows the simulation result 1300 of the LIN receiver circuit 300 that provides among Fig. 3, and this LIN receiver circuit has the ISO3b pulse 1302 that when input signal LIN_bus is in dominance condition, recessive state and the transformation between recessive state and dominance condition, on input signal LIN_bus, occurs.In this emulation (and emulation shown in Figure 14), the amplitude of ISO3b pulse is set at+100V, and this is the situation of the worst condition of ISO3b pulse.Shown in simulation result 1300, the appearance of ISO3b pulse 1302 causes the low state 1304 of the mistake on output signal RXD.So, the receiver circuit 300 that provides among Fig. 3 can't provide the vulnerability to jamming to the ISO3b pulse 1302 that on input signal LIN_bus, occurs.
Figure 14 shows the simulation result 1400 of the LIN receiver circuit 500 that provides among Fig. 5, and this LIN receiver circuit has the ISO3b pulse 1402 that when input signal LIN_bus is in dominance condition, recessive state and the transformation between recessive state and dominance condition, on input signal LIN_bus, occurs.The condition of this emulation is similar to the condition that provides among Figure 13, so that can compare the output signal RXD in each emulation.The simulation result 1400 that provides among Figure 14 shows that the receiver circuit 500 among Fig. 5 does not produce wrong low state on the RXD signal, and RXD signal delay is not surpassed 7.5 μ s.Therefore, the ISO3b pulse that on input signal LIN_bus, occurs of 500 pairs of receiver circuits has vulnerability to jamming.
It should be understood that receiver circuit disclosed herein comprise change under the situation of the spirit of the present disclosure set forth in the claim that can below not breaking away from, provide and scope or change some aspect.

Claims (22)

1. a circuit is characterized in that, said circuit comprises:
Comparator circuit; Operation is used for comparing through the input signal of filtering and first hysteresis threshold or second hysteresis threshold; And export sluggish signal; If said signal through filtering is less than or equal to said first hysteresis threshold then said sluggish signal has first state, and if said signal through filtering more than or equal to said second hysteresis threshold then said sluggish signal has second state;
Operation is used to detect the circuit of low transient voltage of the input signal of non-filtered, and wherein said low transient voltage will produce the effective short-time pulse waveform interference that continues very first time length on said sluggish signal;
Voltage-regulating circuit, operation is used for adjusting said voltage of signals through filtering in response to the detection of said low transient voltage, shortens to second time span littler than said very first time length so that said effective short-time pulse waveform is disturbed; And
Amplitude limiter circuit, operation are used for disturbing from said sluggish input and the effective short-time pulse waveform of removing said shortening, and generate the output signal.
2. circuit according to claim 1; It is characterized in that; Said amplitude limiter circuit comprises delay circuit; Said delay circuit operation is used to receive said sluggish signal and exports delayed signal, and said delayed signal has the first delayed trailing edge after the trailing edge of said sluggish signal, and wherein said first trailing edge is postponed according to the 3rd time span littler than said very first time length.
3. circuit according to claim 2 is characterized in that, said the 3rd time span is more than or equal to said second time span.
4. circuit according to claim 2; It is characterized in that; Said amplitude limiter circuit also comprises output circuit, and said output circuit operation is used for when the effective short-time pulse waveform that does not detect said shortening disturbs, exporting said sluggish signal as said output signal; And when the effective short-time pulse waveform that detects said shortening disturbs, export said delayed signal as said output signal.
5. circuit according to claim 1 is characterized in that said circuit also comprises filter, and said filter is used to receive the input signal of said non-filtered and produces said input signal through filtering.
6. circuit according to claim 1; It is characterized in that; The said circuit that is used to detect low transient voltage comprises comparator, and said comparator operations is used to receive the input signal of said non-filtered, and the input signal and first reference voltage of said non-filtered compared.
7. circuit according to claim 1; It is characterized in that; Said voltage-regulating circuit comprises the adjustment circuit, and said adjustment circuit operation is used to receive the enable signal of second reference voltage and the detection of the said low transient voltage of indication, wherein when detecting said low transient voltage; Said adjustment circuit drives said input signal through filtering to said second reference voltage, and said input signal through filtering is less than said second reference voltage.
8. circuit according to claim 1 is characterized in that, the interrupt source output pulse of the input signal of the said non-filtered of said low transient voltage indication influence.
9. circuit according to claim 1 is characterized in that, it is second state of the mistake on the said sluggish signal that said effective short-time pulse waveform disturbs.
10. circuit according to claim 1 is characterized in that, said circuit is the receiver circuit in the local internet.
11. a receiver circuit is characterized in that, said receiver circuit comprises:
Comparator circuit, the receiving inputted signal and first reference voltage, and have the comparator signal of hanging down transient voltage on the said input signal of output indication;
Voltage-regulating circuit; Receive the said comparator signal and second reference voltage; And when there is said low transient voltage in the indication of said comparator signal on said input signal; Output adjustment electric current, when said input signal through filtering during less than said second reference voltage, said adjustment electric current will drive to said second reference voltage through the input signal of filtering;
Hysteresis circuitry; Said input signal and first hysteresis threshold or second hysteresis threshold through filtering compared; And produce sluggish signal; If said input signal through filtering is less than or equal to said first hysteresis threshold then said sluggish signal has first state, and if said input signal through filtering more than or equal to said second hysteresis threshold then said sluggish signal has second state, wherein as the result of said low transient voltage; Said sluggish signal will have effective short-time pulse waveform to be disturbed; And when said input signal through filtering during, said input signal through filtering is driven to said second reference voltage, shorten the length that the said effective short-time pulse waveform on the said sluggish signal disturbs through said adjustment electric current less than said second reference voltage; And
Amplitude limiter circuit receives said sluggish signal and said comparator signal, and disturbs through effective short-time pulse waveform of removing said shortening and to produce the output signal.
12. receiver circuit according to claim 11 is characterized in that, said receiver circuit also comprises driver-level, and said driver-level receives said output signal from said amplitude limiter circuit, and the output receiver circuit output signal.
13. receiver circuit according to claim 11 is characterized in that, said receiver circuit also comprises filter circuit, and said filter circuit receives said input signal, and produces said input signal through filtering.
14. receiver circuit according to claim 11 is characterized in that, said receiver circuit comprises the receiver in the local internet.
15. receiver circuit according to claim 11; It is characterized in that; When said comparator signal is not indicated when having said low transient voltage on the said input signal; Said output signal equals said sluggish signal, and when said comparator signal indicated that to have said low transient voltage and said sluggish signal on the said input signal be said first state, said output signal equaled to have the said sluggish signal of delayed trailing edge.
16. receiver circuit according to claim 15 is characterized in that, said delayed trailing edge is postponed by the time quantum that disturbs according to the effective short-time pulse waveform more than or equal to said shortening.
17. receiver circuit according to claim 15 is characterized in that, said delayed trailing edge is postponed according to the time quantum that disturbs less than said effective short-time pulse waveform.
18. an equipment is characterized in that, said equipment comprises:
Be used for input signal is carried out filtering to produce the device through the signal of filtering;
Be used for device that said signal and first hysteresis or second hysteresis through filtering compared;
Be used to export the device of sluggish signal; If said signal through filtering is less than or equal to said first hysteresis then said sluggish signal has first state, and if said signal through filtering more than or equal to said second hysteresis then said sluggish signal has second state;
Be used to detect the device of the low transient voltage on the said input signal, wherein said low transient voltage will produce the effective short-time pulse waveform that continues very first time length and disturb on said sluggish signal;
Be used for detection, adjust said voltage of signals, so that said effective short-time pulse waveform is disturbed the device that shortens to second time span littler than said very first time length through filtering in response to said low transient voltage;
Be used to detect the device of effective short-time pulse waveform interference of the said shortening on the said sluggish signal; And
Be used for removing effective short-time pulse waveform interference of said shortening, to produce the device of output signal from said sluggish signal.
19. equipment according to claim 18 is characterized in that, the device that is used to adjust said voltage of signals through filtering also comprises:
If be used for said signal through filtering, then with the device of said signal voltage through filtering to said reference voltage adjustment less than said reference voltage.
20. equipment according to claim 18 is characterized in that, the device that is used to remove effective short-time pulse waveform interference of the said shortening on the said sluggish signal comprises:
Be used to export the device of calibrated signal, said calibrated signal has first trailing edge, and said first trailing edge is postponed according to the 3rd time span littler than said very first time length after the trailing edge of said sluggish signal.
21. equipment according to claim 20 is characterized in that, said the 3rd time span is more than or equal to said second time span.
22. equipment according to claim 18 is characterized in that, said equipment comprises the receiver in the local internet.
CN2011202382040U 2011-06-30 2011-06-30 Receiver circuit and device Expired - Lifetime CN202364205U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102857245A (en) * 2011-06-30 2013-01-02 意法半导体研发(深圳)有限公司 LIN (local Internet) receiver for providing immunity against ISO (interrupted source output) pulse
CN106716845A (en) * 2014-09-26 2017-05-24 德国捷德有限公司 Method and security module for adaptation of a reference value for generation of a bit stream

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102857245A (en) * 2011-06-30 2013-01-02 意法半导体研发(深圳)有限公司 LIN (local Internet) receiver for providing immunity against ISO (interrupted source output) pulse
CN102857245B (en) * 2011-06-30 2015-04-15 意法半导体研发(深圳)有限公司 LIN (local Internet) receiver for providing immunity against ISO (interrupted source output) pulse
CN106716845A (en) * 2014-09-26 2017-05-24 德国捷德有限公司 Method and security module for adaptation of a reference value for generation of a bit stream
CN106716845B (en) * 2014-09-26 2020-04-07 捷德移动安全有限责任公司 Method and security module for matching reference values for generating a bitstream

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