CN202353659U - Circuit for inputting video signal - Google Patents
Circuit for inputting video signal Download PDFInfo
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- CN202353659U CN202353659U CN2011205182239U CN201120518223U CN202353659U CN 202353659 U CN202353659 U CN 202353659U CN 2011205182239 U CN2011205182239 U CN 2011205182239U CN 201120518223 U CN201120518223 U CN 201120518223U CN 202353659 U CN202353659 U CN 202353659U
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- module
- nmos pipe
- nmos
- pipe
- video signal
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Abstract
The utility model discloses a circuit for inputting a video signal. The circuit comprises an input terminal, a clamping voltage point setting module, a voltage reducing and discharging path module, an output point protection module, a clamping step-up source current module and a clamping step-up strengthening and protecting module, wherein the input terminal is used for inputting the video signal; the clamping voltage point setting module is connected with a second node; the clamping step-up strengthening and protecting module is connected with a third node; the clamping voltage point setting module sets a clamping voltage point; the voltage reducing and discharging path module is used for discharging the input terminal; the output point protection module performs low electric potential limitation on voltage of the second node; and the clamping step-up strengthening and protecting module is used for supplying a second current source in the clamping voltage point setting module and clamping the electrical potential of the third node. By the circuit, the clamping of the top of an input video synchronization pulse is realized, the offset of direct-current level of the signal is established when an alternating current coupling input form is adopted, and when a negative voltage input form is adopted, the direct-current level is automatically regulated.
Description
Technical field
The utility model relates to a kind of video signal input circuit.
Background technology
In the video processing circuit of single power supply, can introduce output DC (direct current) imbalance level, the therefore general AC coupled that adopts vision signal.The DC level of signal is rebuild after setting image brightness; And guarantee that signal drops in the linear work district of next stage; This operation is known as " biasing ", according to video waveform and required precision and the stability of bias point, can adopt different circuits.
Sine wave signals such as audio signal can use capacitance-resistance (RC) coupling to set up stable bias voltage.But have only carrier chrominance signal (C) to be similar to a sine wave in the S video (S-Video).Brightness (Y), composite signal (Cvbs) and RGB are complicated wave forms, change along a direction from a reference level, and the sync waveform that below reference level, can also superpose.Sort signal needs a kind of biasing means that is specifically designed to vision signal, is known as clamp because it with the extreme value " clamp " of signal at reference voltage, and another extreme value still can change.
Shown in Figure 1 is existing a kind of clamp circuit; Patent No. application number is the scheme in 201010167197 " video signal input circuit "; Comprise the clamp circuit (210) that is fixed as the voltage of the sync tip that in vision signal, comprises assigned voltage; Be used to determine the level shift circuit (220) with the operating point of the tie point of late-class circuit 201, and suppress the Weak current source (230) that the voltage of input terminal (IN1) rises.This circuit has a lot of defectives, and when not having the negative voltage input, this partial circuit is not that full impregnated is bright to vision signal; Being provided with that DC is ordered is fixing restricted; This part is bigger to PSRR (PSRR) Effect on Performance of system, is not easy to improve; When carrying out the clamper function, driving force is very limited.
Summary of the invention
The purpose of the utility model is to overcome the defective of prior art and a kind of video signal input circuit is provided; Realization is to the clamper of input video sync tip, when the AC coupled input form, sets up the biasing of signal DC level and when negative voltage is imported, DC level automatically adjusted.
The technical scheme that realizes above-mentioned purpose is:
A kind of video signal input circuit; Supply power by a power supply (VDD); Comprise that the input terminal (IN) of incoming video signal, the clamp voltage point that is connected to Section Point (L2) mutually are provided with module (101), step-down discharge path module (102), output point protection module (103) and clamper and boost and draw current module (104); And clamper boosts and strengthens and protection module (105), wherein
Said clamp voltage point is provided with module (101) and comprises first to fourth NMOS pipe, first current source (12), second current source (13) and a voltage source (15), wherein:
The source electrode of the one NMOS pipe (1) links to each other with the drain electrode that the 2nd NMOS manages (2); NMOS pipe (1) drain electrode connect first current source (12);
The source electrode of the 3rd NMOS pipe (3) links to each other with the drain electrode that the 4th NMOS manages (4); The drain electrode of the 3rd NMOS pipe (3) connects second current source (13);
The grid of the one NMOS pipe (1) is managed deleting extremely all of (3) with the 3rd NMOS and is linked to each other with voltage source (15);
The grid of the drain electrode of the one NMOS pipe (1), the 2nd NMOS pipe (2) is connected to first node (L1) mutually with the grid that the 4th NMOS manages (4);
Said clamper is boosted and is drawn current module (104) to comprise PMOS pipe (9) and first resistance (10); Wherein: a PMOS manages (9); Its source electrode connects said power supply (VDD); Grid is connected to the 3rd node (L3) mutually with the drain electrode that the 3rd NMOS manages (3), and drain electrode connects an end of said input terminal (IN) and first resistance (10); The other end of said first resistance (10) is connected to Section Point (L2) mutually with the source electrode that the 4th NMOS manages (4);
Said step-down discharge path module (102) is used for input terminal (IN) is discharged;
Said output point protection module (103) carries out the low level restriction to the voltage of Section Point (L2);
Said clamper is boosted and is strengthened being connected in the 3rd node (L3) with protection module (105), is used for additional to second current source (13), and the current potential of the 3rd node (L3) is carried out clamper.
Above-mentioned video signal input circuit, wherein, said clamper is boosted and is strengthened comprising that with protection module (105) the 2nd PMOS pipe (7) and the 3rd PMOS manage (8), wherein:
The 2nd PMOS manages (7), and its source electrode connects said power supply (VDD), and grid all links to each other with the source electrode of the 3rd PMOS pipe (8) with drain electrode;
The grid of the 3rd PMOS pipe (8) all is connected to the 3rd node (L3) with drain electrode.
Above-mentioned video signal input circuit, wherein, said step-down discharge path module (102) comprises that second resistance (5) of series connection and electric current leak (14), and wherein: second resistance (5) is connected to Section Point (L2), and electric current leaks (14) ground connection.
Above-mentioned video signal input circuit, wherein, said output point protection module (103) comprises the 5th NMOS pipe (11), the drain electrode of the 5th NMOS pipe (11) is connected to Section Point (L2), grid and source grounding.
Above-mentioned video signal input circuit, wherein, said clamp voltage point is provided with module (101) and also comprises first electric capacity (6), and an end of this first electric capacity (6) connects said power supply (VDD), and the other end is connected to the 3rd node (L3).
Above-mentioned video signal input circuit, wherein, said NMOS pipe (1) is the NMOS pipe that diode is connected with the 2nd NMOS pipe (2); Said the 2nd PMOS pipe (7) and the 3rd PMOS pipe (8) be that diode is connected PMOS manage; The NMOS pipe that said the 5th NMOS pipe (11) connects for backward diode.
The beneficial effect of the utility model: the utility model is realized the clamper to the input video sync tip, when the AC coupled input form, sets up the biasing of signal DC level and when negative voltage is imported, DC level is automatically adjusted.Specifically, when the direct current input form was worked, incoming level was in the 0-1.4V scope, and this moment, the utility model circuit module was not worked, and input signal is realized that full impregnated is bright; When the AC coupled input form was worked, when incoming level lied prostrate greater than zero, the clamper function was not still worked, and dc point is provided; When the AC coupled input form was worked, when incoming level lied prostrate less than zero, circuit clamper function enabled, and has realized the automatic regulatory function of circuit working point.
Description of drawings
Fig. 1 is the circuit diagram of a kind of clamp circuit of prior art;
Fig. 2 is the circuit structure diagram of the video signal input circuit of the utility model;
Fig. 3 is that the video signal input circuit of the utility model is applied to the AC coupled sketch map in when input;
Fig. 4 is that the video signal input circuit of the utility model is applied to the direct-current coupling sketch map in when input.
Embodiment
To combine accompanying drawing that the utility model is described further below.
See also Fig. 2, the video signal input circuit 200 of the utility model by power vd D power supply, is connected between prime equipment 201 and the late-class circuit 202, also is connected with second electric capacity 16 between prime equipment 201 and the late-class circuit 202.
The video signal input circuit 200 of the utility model comprises that the input terminal IN of incoming video signal, the clamp voltage point that is connected to Section Point L2 mutually are provided with module 101, step-down discharge path module 102, output point protection module 103 and clamper and boost and draw current module 104; And clamper is boosted and is strengthened and protection module 105; Wherein
The clamp voltage point is provided with module 101 and comprises first to fourth NMOS pipe 1-4, first current source 12, second current source 13, voltage source 15 and first electric capacity 6, wherein:
The source electrode of the one NMOS pipe 1 links to each other with the drain electrode of the 2nd NMOS pipe 2; NMOS pipe 1 drain electrode connect first current source 12;
The source electrode of the 3rd NMOS pipe 3 links to each other with the drain electrode of the 4th NMOS pipe 4; The drain electrode of the 3rd NMOS pipe 3 connects second current source 13;
The grid of the one NMOS pipe 1 links to each other with voltage source 15 with deleting extremely all of the 3rd NMOS pipe 3;
The grid of the drain electrode of the one NMOS pipe 1, the 2nd NMOS pipe 2 is connected to first node L1 mutually with the grid of the 4th NMOS pipe 4;
One end of first electric capacity 6 connects power vd D, and the other end connects the drain electrode of the 3rd NMOS pipe 3, promptly is connected to the 3rd node L3;
Clamper is boosted and is drawn current module 104 to comprise PMOS pipe 9 and first resistance 10, wherein:
The source electrode of the one PMOS pipe 9 connects power vd D; Its grid is connected to the 3rd node L3 mutually with the drain electrode of the 3rd NMOS pipe 3; Its drain electrode connects an end of the input terminal IN and first resistance 10, and the other end of this first resistance 10 is connected to Section Point L2 mutually with the source electrode of the 4th NMOS pipe 4;
For the 4th NMOS pipe 4, when VL1-VL2＞VTH4, the 4th NMOS manages 4 conductings, also is VL1-VTH4＞VL2.Wherein, VL1 refers to the bias voltage of first node L1, and VL2 refers to the bias voltage of Section Point L2, and VTH4 refers to the on state threshold voltage of the 4th NMOS pipe 4.Therefore, can regulate VL1, make that the 4th NMOS managed 4 conductings when input voltage was lower than a certain magnitude of voltage, thereby realize the setting of clamp voltage point through design.
Clamper is boosted and is drawn current module 104 when this circuit gets into clamper function enabled, can carry out large current charge to input terminal IN fast, guarantees that the rapid clamper of input terminal IN is to the expection magnitude of voltage; Simultaneously, clamper is boosted and is drawn current module 104 and the 3rd, the 4th NMOS pipe 3,4 to form feedback loop, when carrying out clamper work, can guarantee stable work.
Step-down discharge path module 102 comprises that second resistance 5 of series connection leaks 14 with electric current, and wherein: second resistance 5 is connected to Section Point L2, and electric current leaks 14 ground connection; DC level is drawn high because of the input clamper as input terminal IN; After incoming video signal recovers the input of normal positive voltage; Need discharge to input terminal IN drops to the level that needs with the direct voltage with this input terminal IN, and step-down discharge path module 102 realizes the step-down discharging function.
Output point protection module 103 comprises that the drain electrode of the 5th NMOS pipe 11, the five NMOS pipe 11 is connected to Section Point L2, grid and source grounding.The voltage of 103 couples of Section Point L2 of output point protection module carries out the low level restriction.
Clamper is boosted and is strengthened comprising the 2nd PMOS pipe the 7 and the 3rd PMOS pipe 8 with protection module 105, and wherein: the source electrode of the 2nd PMOS pipe 7 connects power vd D, and grid is managed 8 source electrode with the 3rd PMOS and linked to each other with draining all; The grid of the 3rd PMOS pipe 8 all is connected to the 3rd node L3 with drain electrode.Clamper is boosted and is strengthened with protection module 105 two effects being arranged, and the one, after the 4th NMOS manages 4 conductings when carrying out clamper, additional as to second current source 13; Make circuit get into normal operating state rapidly; The 2nd, the current potential of the 3rd node L3 is carried out clamper, circuit gets into after the clamper operating state, the voltage VL3 of the 3rd node L3 by clamper rapidly at VDD-2*Vgs voltage place; Wherein, VDD refers to the voltage of power vd D, supposes that here the source gate voltage of the 2nd PMOS pipe the 7 and the 3rd PMOS pipe 8 equates, is Vgs.Thereby make this circuit when clamping state, output current keeps being stabilized in the maximum place, and circuit is played current limliting.
Total at present embodiment, NMOS pipe 1 is the NMOS pipe that diode is connected with the 2nd NMOS pipe 2; The 2nd PMOS pipe 7 and the 3rd PMOS pipe 8 be that diode is connected PMOS manage; The NMOS pipe that the 5th NMOS pipe 11 connects for backward diode.
See also Fig. 3, the sketch map when being applied to the AC coupled input for the utility model.See also Fig. 4, the sketch map when being applied to the direct-current coupling input for the utility model. Electric capacity 16,17,18 is ac coupling capacitor, and 201,301,401 is prime equipment, and 200,300,400 is the video signal input circuit of the utility model, and 202,302,402 is back level signal processing circuit.Wherein, the typical application value of electric capacity 16,17,18 is 0.1uF, and the typical application value of resistance 19,20,21,22,23,24 is 75 ohm, and the typical application value of electric capacity 25,26,27 is 220uF.
At this moment, in the time of in incoming video signal clearly is limited to the 0-1.4V interval, can adopt the direct-current coupling mode of operation.This moment, the video signal input circuit of the utility model was that full impregnated is bright to the vision signal of importing, and the clamper function is turn-offed;
When AC coupled was imported, if signal amplitude is still in 0-1.4 volt scope the time, the clamper function was still turn-offed, but the video signal input circuit of the utility model is an incoming video signal DC level is provided;
When AC coupled was imported, if signal amplitude is lower than zero, when the vision signal sync tip occurred in other words, the clamper function was opened, and regulated the DC level of incoming video signal automatically.
Ordinary circumstance decline vision signal sync tip is set to be lower than slightly zero position.
In sum, the utility model is realized the clamper to the input video sync tip, when the AC coupled input form, sets up the biasing of signal DC level and when negative voltage is imported, DC level is automatically adjusted.Simultaneously, the utility model is simple in structure, is easy to realize, and is with low cost.
Above embodiment only supplies to explain the usefulness of the utility model; But not to the restriction of the utility model; The technical staff in relevant technologies field under the situation of spirit that does not break away from the utility model and scope, can also make various conversion or modification; Therefore all technical schemes that are equal to also should belong to the category of the utility model, should be limited each claim.
Claims (6)
1. video signal input circuit; Supply power by a power supply (VDD); It is characterized in that, comprise that the input terminal (IN) of incoming video signal, the clamp voltage point that is connected to Section Point (L2) mutually are provided with module (101), step-down discharge path module (102), output point protection module (103) and clamper and boost and draw current module (104), and clamper is boosted and strengthened and protection module (105); Wherein
Said clamp voltage point is provided with module (101) and comprises first to fourth NMOS pipe, first current source (12), second current source (13) and a voltage source (15), wherein:
The source electrode of the one NMOS pipe (1) links to each other with the drain electrode that the 2nd NMOS manages (2); NMOS pipe (1) drain electrode connect first current source (12);
The source electrode of the 3rd NMOS pipe (3) links to each other with the drain electrode that the 4th NMOS manages (4); The drain electrode of the 3rd NMOS pipe (3) connects second current source (13);
The grid of the one NMOS pipe (1) is managed deleting extremely all of (3) with the 3rd NMOS and is linked to each other with voltage source (15);
The grid of the drain electrode of the one NMOS pipe (1), the 2nd NMOS pipe (2) is connected to first node (L1) mutually with the grid that the 4th NMOS manages (4);
Said clamper is boosted and is drawn current module (104) to comprise PMOS pipe (9) and first resistance (10); Wherein: a PMOS manages (9); Its source electrode connects said power supply (VDD); Grid is connected to the 3rd node (L3) mutually with the drain electrode that the 3rd NMOS manages (3), and drain electrode connects an end of said input terminal (IN) and first resistance (10); The other end of said first resistance (10) is connected to Section Point (L2) mutually with the source electrode that the 4th NMOS manages (4);
Said step-down discharge path module (102) is used for input terminal (IN) is discharged;
Said output point protection module (103) carries out the low level restriction to the voltage of Section Point (L2);
Said clamper is boosted and is strengthened being connected in the 3rd node (L3) with protection module (105), is used for additional to second current source (13), and the current potential of the 3rd node (L3) is carried out clamper.
2. video signal input circuit according to claim 1 is characterized in that, said clamper is boosted and strengthened comprising that with protection module (105) the 2nd PMOS pipe (7) and the 3rd PMOS manage (8), wherein:
The 2nd PMOS manages (7), and its source electrode connects said power supply (VDD), and grid all links to each other with the source electrode of the 3rd PMOS pipe (8) with drain electrode;
The grid of the 3rd PMOS pipe (8) all is connected to the 3rd node (L3) with drain electrode.
3. video signal input circuit according to claim 1 and 2; It is characterized in that; Said step-down discharge path module (102) comprises that second resistance (5) of series connection and electric current leak (14), and wherein: second resistance (5) is connected to Section Point (L2), and electric current leaks (14) ground connection.
4. video signal input circuit according to claim 3 is characterized in that, said output point protection module (103) comprises the 5th NMOS pipe (11), and the drain electrode of the 5th NMOS pipe (11) is connected to Section Point (L2), grid and source grounding.
5. video signal input circuit according to claim 1 is characterized in that, said clamp voltage point is provided with module (101) and also comprises first electric capacity (6), and an end of this first electric capacity (6) connects said power supply (VDD), and the other end is connected to the 3rd node (L3).
6. video signal input circuit according to claim 4 is characterized in that, said NMOS pipe (1) is the NMOS pipe that diode is connected with the 2nd NMOS pipe (2); Said the 2nd PMOS pipe (7) and the 3rd PMOS pipe (8) be that diode is connected PMOS manage; The NMOS pipe that said the 5th NMOS pipe (11) connects for backward diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205182239U CN202353659U (en) | 2011-12-13 | 2011-12-13 | Circuit for inputting video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205182239U CN202353659U (en) | 2011-12-13 | 2011-12-13 | Circuit for inputting video signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202353659U true CN202353659U (en) | 2012-07-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205182239U Withdrawn - After Issue CN202353659U (en) | 2011-12-13 | 2011-12-13 | Circuit for inputting video signal |
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| Country | Link |
|---|---|
| CN (1) | CN202353659U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497496A (en) * | 2011-12-13 | 2012-06-13 | 上海贝岭股份有限公司 | Video signal input circuit |
| CN106911251A (en) * | 2015-12-22 | 2017-06-30 | 上海贝岭股份有限公司 | Boost power converter |
| CN114217116A (en) * | 2022-02-21 | 2022-03-22 | 苏州贝克微电子股份有限公司 | Current detection circuit with controllable detection current |
-
2011
- 2011-12-13 CN CN2011205182239U patent/CN202353659U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497496A (en) * | 2011-12-13 | 2012-06-13 | 上海贝岭股份有限公司 | Video signal input circuit |
| CN102497496B (en) * | 2011-12-13 | 2013-09-25 | 上海贝岭股份有限公司 | Video signal input circuit |
| CN106911251A (en) * | 2015-12-22 | 2017-06-30 | 上海贝岭股份有限公司 | Boost power converter |
| CN106911251B (en) * | 2015-12-22 | 2020-05-22 | 上海贝岭股份有限公司 | Step-down power converter |
| CN114217116A (en) * | 2022-02-21 | 2022-03-22 | 苏州贝克微电子股份有限公司 | Current detection circuit with controllable detection current |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120725 Effective date of abandoning: 20130925 |
|
| RGAV | Abandon patent right to avoid regrant |