CN202340201U - Field programmable gate array (FPGA)-based speed setting controller for brushless direct current motor - Google Patents
Field programmable gate array (FPGA)-based speed setting controller for brushless direct current motor Download PDFInfo
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- CN202340201U CN202340201U CN2011203417244U CN201120341724U CN202340201U CN 202340201 U CN202340201 U CN 202340201U CN 2011203417244 U CN2011203417244 U CN 2011203417244U CN 201120341724 U CN201120341724 U CN 201120341724U CN 202340201 U CN202340201 U CN 202340201U
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- fpga
- brushless
- speed setting
- setting controller
- direct current
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Abstract
The utility model discloses a field programmable gate array (FPGA)-based speed setting controller for a brushless direct current motor. The FPGA-based speed setting controller comprises the brushless direct current motor and a three-phase bridge type switch, wherein the brushless direct current motor is connected with the three-phase bridge type switch; the three-phase bridge type switch is connected with a direct current power supply; and the brushless direct current motor comprises a rotor and a stator. The FPGA-based speed setting controller is characterized by also comprising an FPGA chip, wherein the FPGA chip is connected with the three-phase bridge type switch and a brushless direct current motor rotor position detection signal respectively; a pulse width modulation (PWM) signal generator, a master control logic combinational circuit, a finite state machine (FSM) filter and a rotating speed sampling and calculation unit are arranged in the FPGA chip; the FSM filter is connected with the brushless direct current motor rotor position detection signal and the master control logic combinational circuit respectively; and the PWM signal generator is connected with the rotating speed sampling and calculation unit and the master control logic combinational circuit respectively. The hardware structure of the FPGA-based speed setting controller is simplified; the FPGA-based speed setting controller has a simpler interface circuit and a flexible online configuration function, and is convenient to maintain; the arithmetic speed can be effectively increased; the reliability of the FPGA-based speed setting controller is enhanced; and the cost is decreased.
Description
Technical field
The utility model relates to a kind of motor speed adjusting controller, more particularly, relates to a kind of brushless DC motor speed setting controller based on FPGA (Field-Programmable Gate Array, field programmable gate array).
Background technology
Under the scientific and technological progress; Electronic technology and control technology are fast-developing; Particularly the X in brushless DC motor control technology is day by day ripe and perfect, yet this makes that also control rate, data-handling capacity, the stability of X in brushless DC motor control device are more challenging.Existing brushless DC motor speed setting controller hardware configuration; Current main employing digital signal processor (Digital Signal Processing; Abbreviation DSP), single-chip microcomputer (Single Chip Microcomputer; Be called for short MCU) with three kinds of modes such as application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit, abbreviation ASIC) controller.
Calculate and complicated commutation modulation in order to accomplish data acquisition at a high speed, generally speaking, can adopt dsp chip to realize controlled function with software mode; Though this control mode is more flexible, its construction cycle is long, and it is many to take the CPU time; Control rate is slow; Stability is not high, will adopt the design of two DSP in order to improve performance sometimes, and this makes the entire system cost performance descend.When adopting MCU control, because single-chip microcomputer command function of when realizing control itself is not strong, the used excessive cycle of multiplication and division, data transaction speed is slow excessively, and processing speed can't reach requirement, makes that the performance of brshless DC motor can not be brought into play fully.When adopting application-specific integrated circuit (ASIC) control, these chip internals are furnished with the Electric Machine Control special module, and are easy to use, but the The whole control algorithm is still realized by software programming.Along with the increase of the complexity and the software function of algorithm, the real-time of control system computing is affected.In the abominable application scenario of some environment, receive external interference easily based on the control system of software programming, make to use to be restricted.
In the X in brushless DC motor control process, not only to accomplish data acquisition at a high speed and calculate, also will accomplish the complicated calculations and the commutation modulation of a plurality of control rings; Therefore, with demand, design a kind of speed setting controller; Make its hardware configuration more simply, effectively improve the speed of computing; And the stability of raising data processing, and avoid external interference effectively, become a subject under discussion of being badly in need of solution on the application market.
The utility model content
In order to overcome deficiency of the prior art, the purpose of the utility model is to provide a kind of brushless DC motor speed setting controller based on FPGA, can effectively improve brushless DC motor speed setting controller stability, data processing speed and antijamming capability.
For realizing above-mentioned purpose, the utility model adopts following technical scheme:
Brushless DC motor speed setting controller based on FPGA; Comprise brushless DC motor, three-phase bridge switch; Brushless DC motor links to each other with the three-phase bridge switch, and the three-phase bridge switch connects DC power supply, and brushless DC motor comprises rotor and stator; Lay the distributed winding of three-phase (or heterogeneous) of symmetry on the stator, rotor surface then forms magnetic pole by permanent magnet.Be attached with the magneto-dependent sensor of 120 ° of electrical degrees of three mutual deviations at stator winding end iron core notch.Brushless DC motor speed setting controller based on FPGA; Also has respectively the fpga chip that links to each other with brushless DC motor rotor position detection signal with the three-phase bridge switch; Wherein be provided with pwm signal generator, master control logic combinational circuit, FSM filter and rotating speed sampling and computing unit in the fpga chip; The FSM filter links to each other with said master control logic combinational circuit with said brushless DC motor rotor position detection signal respectively, and the pwm signal generator links to each other with said master control logic combinational circuit with computing unit with the rotating speed sampling respectively.
Wherein, under the DC power supply situation, the terminal of each phase winding of laying on the stator must link through the positive and negative end of electronic switch and power supply.
On the stator of brushless DC motor, lay the distributed winding of three-phase (or heterogeneous) of symmetry, rotor surface then forms magnetic pole by permanent magnet, so be equivalent to replace with permanent magnet the synchronous motor of rotor-exciting winding on the structure.In order to collect the clock signal of rotor space position, be attached with the magneto-dependent sensor of 120 ° of electrical degrees of three mutual deviations at stator winding end iron core notch
Need earlier through Si Mite inverter shaping and light-coupled isolation by the clock signal of the three-phase rotor space position that magneto-dependent sensor produced, go into the master control logic combination circuit through the FSM filter filtering is laggard again.Other has arbitrary phase clock signal then to get into rotating speed sampling and computing unit; Determined the adjustable duty ratio of PWM by fixing pulse duration b set point and the definite TP set point of rotating speed sampling calculated value; Thereby export six way switch control signals by the master control logic combinational circuit, realize rotating speed control.
The beneficial effect of the utility model: the characteristics that the utility model is made up of the module of software and hardware of complicacy to existing brushless DC motor speed-adjusting and control system; Proposition is based on the brushless DC motor speed setting controller architecture of FPGA; According to SOC(system on a chip) door aboundresources and the good characteristics of real-time, introduced the practical implementation logical circuit of pwm signal generator and hardware filtering device etc.Compare with traditional speed setting controller, hardware configuration is simplified, and has comparatively succinct interface circuit and Configuration Online function flexibly.Can improve arithmetic speed effectively, be convenient to safeguard, reliability strengthens and reduce cost.
Description of drawings
Fig. 1 is the structural representation of the utility model;
Fig. 2 is the structural representation of the utility model brushless DC motor;
Fig. 3 is the circuit diagram of the utility model three-phase bridge switch and brushless DC motor threephase stator winding terminal;
Fig. 4 is the utility model hardware filtering trigger and logic combination circuit figure;
Fig. 5 is the utility model pwm signal generator hardware configuration.
In Fig. 2: the 1-stator; The 2-p-m rotor; The 3-transducer.
Embodiment
See also Fig. 1, the utility model comprises brushless DC motor, three-phase bridge switch, and brushless DC motor links to each other with the three-phase bridge switch, and the three-phase bridge switch connects DC power supply, and brushless DC motor comprises rotor and stator.Brushless DC motor speed setting controller based on FPGA; Fpga chip (dashed rectangle is represented among Fig. 1) also links to each other with brushless DC motor rotor position detection signal with the three-phase bridge switch respectively; Wherein be provided with pwm signal generator, master control logic combinational circuit, FSM filter and rotating speed sampling and computing unit in the fpga chip; The FSM filter links to each other with the master control logic combinational circuit with brushless DC motor rotor position detection signal respectively, and the pwm signal generator links to each other with said master control logic combinational circuit with computing unit with the rotating speed sampling respectively.
See also Fig. 2; Architectural feature for the utility model brushless DC motor; In the present embodiment, brushless DC motor comprises rotor and stator, on the stator of brushless DC motor, lays the distributed winding of three-phase (or heterogeneous) of symmetry; Rotor surface then forms magnetic pole by permanent magnet and forms a p-m rotor, so be equivalent to replace with permanent magnet the synchronous motor of rotor-exciting winding on the structure.In order to collect the clock signal of rotor space position, be attached with the transducer of 120 ° of electrical degrees of three mutual deviations at stator winding end iron core notch, this transducer is a magneto-dependent sensor in the present embodiment.
In the present embodiment, behind the FSM filter filtering, get into the master control logic combinational circuit more again through Si Mite inverter shaping and light-coupled isolation by first need of the clock signal of the three-phase rotor space position that magneto-dependent sensor produced.Other has the clock signal of the arbitrary phase rotor space position in the three-phase then to get into rotating speed sampling and computing unit; The definite TP set point of rotating speed sampling calculated value that is obtained by fixing pulse duration b set point and rotating speed sampling computing unit has determined the adjustable duty ratio of PWM; Thereby export six way switch control signals by the master control logic circuit, thereby realize rotating speed control.
In the present embodiment because stator current is by commutating and commutation with sequential discontinuous ground with the synchronizing cycle of rotor rotation, so air-gap rotating magnetic field is step-type, thereby and rotor magnetic pole between electromagnetic torque pulsation is arranged slightly.For stator current is produced in air gap and the synchronous rotating magnetic field of rotor; Under the DC power supply situation; The terminal of each phase winding must be connected with the positive and negative end of power supply through electronic switch; Please refer to Fig. 3, be three-phase bridge switch and wherein a kind of connected mode of three-phase winding terminal, promptly the terminal A of each phase winding, B, C are respectively through electronic switch S
1, S
3, S
5With positive source E
+Link to each other, and respectively through electronic switch S
4, S
6, S
2With power cathode E
-Link to each other.
See also Fig. 4; The utility model hardware filtering trigger and logic combination circuit; Because the collection of the clock signal of rotor space position and transmission are in motor operation and the adverse circumstances with big current switching, are disturbed like signal, might make the switching-over step-out or stop operation.Need the clock signal of the rotor space position after the shaping is carried out hardware filtering for this reason; This filter patterns is based on the logical definition to signal level; Be that time varying signal is in the orderly function of clock pulse control; As observed three identical level " 1 " continuously or " 0 " just is defined as " 1 " or " 0 ", in other words, have only when the signal period greater than clock triple during the cycle; The clock signal of rotor space position could be normal through filter, probability of miscarriage of justice when this has just reduced the signal level switching widely.
In the present embodiment, in the hardware environment of fpga chip, use FSM map analysis method can realize hardware filtering easily and efficiently.Adopt hardware filtering can improve the reliability of system.In order to realize hardware filtering, need use two FSM figure, one of which is individual for declaring " 1 ", and another is for declaring " 0 ".Need launch two d type flip flop D
1And D
2Realize with the master control logic combinational circuit.
See also Fig. 5, wherein τ
0Be system clock cycle, T
PSetting can be from cpu instruction and bus.Pulsewidth b set point does not become with rotating speed, the pwm comparator of can when initialization, packing into.In each circulation of signal flow, whenever the output and the T of clock counter
PWhen set point equates, T
PComparator is just exported a high level pulse, on the one hand with rest-set flip-flop set, locks new T simultaneously
PSet point, and the new counting of enabling counting device.And when the count value of output pulse width comparator equates with its set point, having produced a high level pulse equally, its unique task is with trigger reset, thereby produces pwm signal at its Q end.
In sum; The characteristics that the utility model is made up of the module of software and hardware of complicacy to existing brushless DC motor speed-adjusting and control system; Proposition is based on the brushless DC motor speed setting controller architecture of FPGA; According to SOC(system on a chip) door aboundresources and the good characteristics of real-time, introduced the practical implementation logical circuit of pwm signal generator and hardware filtering device etc.Compare with traditional speed setting controller, hardware configuration is simplified, and has comparatively succinct interface circuit and Configuration Online function flexibly.Can improve arithmetic speed effectively, be convenient to safeguard, reliability strengthens and reduce cost.
Claims (6)
1. brushless DC motor speed setting controller based on FPGA; It comprises brushless DC motor, three-phase bridge switch; Said brushless DC motor links to each other with said three-phase bridge switch; Said three-phase bridge switch connects DC power supply; Said brushless DC motor comprises rotor and stator; It is characterized in that: also comprise fpga chip, said fpga chip links to each other with said brushless DC motor rotor position detection signal with said three-phase bridge switch respectively, is provided with pwm signal generator, master control logic combinational circuit, FSM filter and rotating speed sampling and computing unit in the wherein said fpga chip; Said FSM filter links to each other with said master control logic combinational circuit with said brushless DC motor rotor position detection signal respectively, and said pwm signal generator links to each other with said master control logic combinational circuit with computing unit with said rotating speed sampling respectively.
2. the brushless DC motor speed setting controller based on FPGA according to claim 1 is characterized in that: the filter patterns of said FSM filter is based on the logical definition of signal level.
3. the brushless DC motor speed setting controller based on FPGA according to claim 1 is characterized in that: three-phase or the heterogeneous distributed winding of laying symmetry on the said stator.
4. the brushless DC motor speed setting controller based on FPGA according to claim 1, it is characterized in that: rotor surface forms magnetic pole by permanent magnet.
5. the brushless DC motor speed setting controller based on FPGA according to claim 3 is characterized in that: the magneto-dependent sensor that is attached with 120 ° of electrical degrees of three mutual deviations at stator winding end iron core notch.
6. the brushless DC motor speed setting controller based on FPGA according to claim 3 is characterized in that: the terminal of said distributed winding is connected with the positive and negative end of DC power supply through electronic switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203417244U CN202340201U (en) | 2011-09-13 | 2011-09-13 | Field programmable gate array (FPGA)-based speed setting controller for brushless direct current motor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203417244U CN202340201U (en) | 2011-09-13 | 2011-09-13 | Field programmable gate array (FPGA)-based speed setting controller for brushless direct current motor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202340201U true CN202340201U (en) | 2012-07-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203417244U Expired - Fee Related CN202340201U (en) | 2011-09-13 | 2011-09-13 | Field programmable gate array (FPGA)-based speed setting controller for brushless direct current motor |
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|---|---|
| CN (1) | CN202340201U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429524A (en) * | 2015-12-15 | 2016-03-23 | 李哲 | FPGA-based brushless direct current motor speed regulating system |
-
2011
- 2011-09-13 CN CN2011203417244U patent/CN202340201U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429524A (en) * | 2015-12-15 | 2016-03-23 | 李哲 | FPGA-based brushless direct current motor speed regulating system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120718 Termination date: 20130913 |