CN202332230U - Shift register, gate drive circuit and liquid crystal display device thereof - Google Patents
Shift register, gate drive circuit and liquid crystal display device thereof Download PDFInfo
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- CN202332230U CN202332230U CN 201120478684 CN201120478684U CN202332230U CN 202332230 U CN202332230 U CN 202332230U CN 201120478684 CN201120478684 CN 201120478684 CN 201120478684 U CN201120478684 U CN 201120478684U CN 202332230 U CN202332230 U CN 202332230U
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Abstract
The utility model discloses a shift register, a gate drive circuit and a liquid crystal display device thereof, and relates to the field of liquid crystal display, in order to achieve the aim that after the power supply of the liquid crystal display device is closed, residual images disappear rapidly, thus the image quality of the liquid crystal display device is improved. The shift register comprises an upper pulling unit, an upper pulling driving unit, a lower pulling unit, a lower pulling driving unit, a resetting unit, a separating unit and a switch unit, wherein the separating unit is connected with the upper pulling unit, and is used for separating a gate line of the gate drive circuit and the upper pulling unit after the liquid crystal display device is closed; and the switch unit is connected with the gate line, and is used for improving the electric potential of the gate line of the gate drive circuit after the liquid crystal display device is closed. The shift register and the gate drive circuit provided by the utility model are applied to the liquid crystal display device.
Description
Technical field
The utility model relates to field of liquid crystal display, relates in particular to a kind of shift register, gate driver circuit and liquid crystal indicator thereof.
Background technology
In demonstration field, plane; Liquid crystal indicator is with its in light weight, characteristics such as volume is little, thin thickness that have; Be widely used in the terminal presentation facility of various sizes; In recent years, along with science and technology development, a kind of gate drivers occurred and directly be produced on the new technique on the glass substrate through the mask plate coating technique with liquid crystal indicator---GIP (Gate in Panel) technology.Though the framework based on the technological gate drivers of GIP is varied; But the shift register of a plurality of cascades is set on the substrate of liquid crystal panel exactly generally speaking; The gating of shift register controlling level grid line with close; From function replaced traditional liquid crystal panel grid-driving integrated circuit be connected the brilliant film of covering of usefulness (Chip on Film, be called for short COF), greatly reduce the cost and the thickness of liquid crystal panel.
In existing technology, the gate driver circuit of existing GIP type liquid crystal indicator comprises the many signal line and the shift register that is used for stored signal data that are used to provide signal.
As shown in Figure 1, signal wire comprises:
The enabling signal line is used for to shift register input drive signal STV.
The degrade signal line is used for to shift register input low level VSS.
First signal wire and secondary signal line are used for the complementary clock pulse signal to shift register being provided, i.e. first clock signal clk and second clock signal CLKB.
The unit that shift register comprises has:
Pull-up unit, on draw driver element, drop-down unit, drop-down driver element and reset unit, descend like Fig. 1.
Pull-up unit comprises the 3rd thin film transistor (TFT) M3.The grid of M3 is connected with the drain electrode of the first film transistor M1, and the source electrode of M3 is connected with first signal wire, and the drain electrode of M3 is to output terminal output grid line drive signal Gate1, and this grid line drive signal also is the input signal of next shift register.
On draw driver element to comprise the first film transistor M1, the 13 thin film transistor (TFT) M13 and capacitor C 1.The source electrode of M1 all is being connected the enabling signal line with grid, and the drain electrode of M1 is connected with an end of capacitor C 1; The grid of M13 is connected with the secondary signal line, and the M13 source electrode is connected with the enabling signal line, and the M13 drain electrode is connected with the drain electrode of M1; The end of C1 and the drain electrode of M1 also are simultaneously that the drain electrode of M13 connects, and the other end is connected with the drain electrode of M3.On draw driver element to be used to drive the unlatching of pull-up unit.
Drop-down unit comprises the tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11 and the 12 thin film transistor (TFT) M12.The grid of M10 is connected with PD point among Fig. 1, and promptly the grid of M10 is connected with the drain electrode of the 5th thin film transistor (TFT) M5, and the source electrode of M10 is connected with the drain electrode of M1 and M13, and the drain electrode of M10 is connected with the degrade signal line; The grid of M11 the same with M10 with Fig. 1 in the PD point be connected, the source electrode of M11 is connected with the drain electrode of M3, the drain electrode of M11 is also the same with M10 to be connected with the degrade signal line; The source electrode of M12 is connected with the drain electrode of M3, and the grid of M12 is connected with the secondary signal line, and the drain electrode of M12 is connected with the degrade signal line.Drop-down unit is used for when Fig. 1 PU point and grid line drive signal Gate1 are disarmed state, to its input low voltage signal, reduces its noise.
Drop-down driver element comprises the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9.The grid of M5 is connected with PD_CN point among Fig. 1, and the source electrode of M5 is connected with the secondary signal line, and the drain electrode of M5 is connected with the PD point; The grid of M6 is connected with some PU, and the source electrode of M6 is connected with the drain electrode of M5, and the drain electrode of M6 is connected with the degrade signal line; The grid of M8 is connected with the grid of M6, promptly is connected with the PU point, and the source electrode of M8 is connected with the PD_CN point, and the drain electrode of M8 is connected with the degrade signal line; The grid of M9 is connected with the secondary signal line with source electrode, and the M9 drain electrode is connected with the PD_CN point.Drop-down driver element is realized the driving to drop-down unit through the control to node PD_CN and node PD current potential.
Reset unit comprises the second thin film transistor (TFT) M2 and the 4th thin film transistor (TFT) M4.The grid of M2 is connected with the output terminal of the shift register of next stage, and the source electrode of M2 is connected with the PU point, and the drain electrode of M2 is connected with the degrade signal line; The grid of M4 is connected with the output terminal of the shift register of next stage, and the source electrode of M4 and the drain electrode of M3 are that the output terminal of first order shift register is connected, and the drain electrode of M4 is connected with the degrade signal line.Reset unit is opened when next stage shift register output noble potential, and the grid line drive signal Gate1 of first order shift register is reverted to electronegative potential.
Fig. 2 is the timing waveform of this gate driver circuit when GIP type liquid crystal indicator operate as normal; As shown in Figure 2; When enabling signal alignment first order shift register input drive signal STV, draw driver element to open on this moment PU point current potential drawn high to be noble potential, first clock signal clk is an electronegative potential and second clock signal CLKB is a noble potential simultaneously; Through adopting suitable M8 and M9, can be so that PD_CN and PD node all remain on electronegative potential; At next constantly, CLK is a noble potential, and pull-up unit M3 opens; Export noble potential the output terminal of first order shift register to, this moment, grid line drive signal Gate1 was a noble potential, made the TFT conducting; Voltage on the data line can be loaded on the pixel electrode; Have image to show on the then corresponding pixel cell, this grid line drive signal Gate1 draws driver element as the drive signal of next stage shift register on the unlatching next stage shift register simultaneously; Then; CLKB is a noble potential, and second level shift register is equivalent to the CLK signal of first order shift register, and driving partial grid line drive signal Gate2 is noble potential; The signal Gate2 of noble potential is as the reset signal input of first order shift register simultaneously; Open reset unit, M4 is reset to electronegative potential with grid line drive signal Gate1, and M2 drags down the PU node potential; Simultaneously, drop-down unit is opened, and M10 drags down the PU current potential, and M11 and M12 play the effect that rapidly the Gate1 signal potential is dragged down, and the conducting of TFT is broken off, and reduces the output image noise.
The corresponding one-level gate driver circuit of each row grid line, the output signal of each grade gate driver circuit is the drive signal of next stage gate driver circuit, the mutual cascade of a plurality of gate driver circuits is as shown in Figure 1, can realize lining by line scan of whole grid lines thus.
The inventor finds in the process that realizes the utility model; Existing GIP type liquid crystal display grid electrode drive circuit; Behind the liquid crystal indicator power-off, grid line is thoroughly closed, and the electric charge of the charged particle that causes retaining in the pixel electrode is difficult for scattering and disappearing; The time that afterimage disappears is longer, has influenced the quality of liquid crystal display picture.
The utility model content
The utility model technical matters to be solved is to provide a kind of shift register, gate driver circuit and liquid crystal indicator thereof; Can be implemented in the transient purpose of afterimage behind the liquid crystal indicator power-off, improve the image quality of liquid crystal indicator.
For solving the problems of the technologies described above, the utility model shift register, gate driver circuit and liquid crystal indicator thereof adopt following technical scheme:
A kind of shift register; Said shift register comprises: pull-up unit, on draw driver element, drop-down unit, drop-down driver element and reset unit; Also comprise with pull-up unit and being connected; Be used for after liquid crystal indicator is closed the isolated location that grid line and said pull-up unit with gate driver circuit break off, and be connected, be used for closing the switch element of the grid line current potential of back raising gate driver circuit at said liquid crystal indicator with the grid line of gate driver circuit.
Said pull-up unit comprises the 3rd thin film transistor (TFT); The grid of said the 3rd thin film transistor (TFT) connects the first film transistor drain; The source electrode of said the 3rd thin film transistor (TFT) connects first signal wire that is used for providing first clock signal to said shift register, and the drain electrode of said the 3rd thin film transistor (TFT) connects the grid line of gate driver circuit;
Draw driver element to comprise the first film transistor, the 13 thin film transistor (TFT) and electric capacity on said; The transistorized source electrode of said the first film is connected the enabling signal line that is used for providing drive signal to said shift register with grid; Said the first film transistor drain is connected with an end of electric capacity; The grid of said the 13 thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to shift register; The source electrode of said the 13 thin film transistor (TFT) be used for providing the enabling signal line of drive signal to be connected to said shift register; The drain electrode of said the 13 thin film transistor (TFT) is connected with the first film transistor drain, and an end of electric capacity is connected with the first film transistor drain, and the other end is connected with the drain electrode of the 3rd thin film transistor (TFT);
Said drop-down unit comprises the tenth thin film transistor (TFT), the 11 thin film transistor (TFT) and the 12 thin film transistor (TFT); The grid of said the tenth thin film transistor (TFT) is connected with the drain electrode of the 5th thin film transistor (TFT); The source electrode of said the tenth thin film transistor (TFT) is connected with the first film transistor drain; The drain electrode of said the tenth thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 11 thin film transistor (TFT) is connected with the drain electrode of the 5th thin film transistor (TFT); The source electrode of said the 11 thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT); The drain electrode of said the 11 thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The source electrode of said the 12 thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), the grid of said the 12 thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to said shift register, the drain electrode of said the 12 thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register;
Said drop-down driver element comprises the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT); The grid of said the 5th thin film transistor (TFT) is connected with the drain electrode of said the 9th thin film transistor (TFT); The source electrode of said the 5th thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to said shift register; The drain electrode of said the 5th thin film transistor (TFT) is connected with the source electrode of said the tenth thin film transistor (TFT); The grid of said the 6th thin film transistor (TFT) is connected with the grid of said the 3rd thin film transistor (TFT); The source electrode of said the 6th thin film transistor (TFT) is connected with the drain electrode of said the 5th thin film transistor (TFT); The drain electrode of said the 6th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 8th thin film transistor (TFT) is connected with the grid of said the 6th thin film transistor (TFT), and the source electrode of said the 8th thin film transistor (TFT) is connected with the drain electrode of the 9th thin film transistor (TFT), the drain electrode of said the 8th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 9th thin film transistor (TFT) and source electrode be used for providing the secondary signal line of second clock signal to be connected to said shift register, the drain electrode of said the 9th thin film transistor (TFT) is connected with the grid of said the 5th thin film transistor (TFT) and the source electrode of the 8th thin film transistor (TFT);
Said reset unit comprises second thin film transistor (TFT) and the 4th thin film transistor (TFT); The grid of said second thin film transistor (TFT) is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of said second thin film transistor (TFT) is connected with the grid of said the 3rd thin film transistor (TFT); The drain electrode of said second thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 4th thin film transistor (TFT) is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of said the 4th thin film transistor (TFT) is connected with the drain electrode of said the 3rd thin film transistor (TFT), the drain electrode of said the 4th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register.
Said isolated location comprises the 14 thin film transistor (TFT); The grid of said the 14 thin film transistor (TFT) connects the first power supply signal line that is used for providing drive signal to said isolated location; The source electrode of said the 14 thin film transistor (TFT) connects the drain electrode of the 3rd thin film transistor (TFT) of said pull-up unit, and the drain electrode of said the 14 thin film transistor (TFT) connects the grid line of said gate driver circuit.
Said switch element comprises the 15 thin film transistor (TFT); The grid of said the 15 thin film transistor (TFT) is connected the second source signal wire that is used for providing drive signal to said switch element with source electrode, the drain electrode of said the 15 thin film transistor (TFT) connects the grid line of the gate driver circuit that comprises said shift register.
A kind of gate driver circuit; Comprise signal wire and above-mentioned shift register; Said signal wire comprises: enabling signal line, degrade signal line, first signal wire and secondary signal line; It is characterized in that, also comprise: the first power supply signal line and the second source signal wire that is used for providing drive signal that are used for providing drive signal to said switch element to said isolated location;
The output signal of the said first power supply signal line is always high level when the liquid crystal indicator operate as normal, the output signal of said second source signal wire is always low level when the liquid crystal indicator operate as normal;
The output signal of the said first power supply signal line is identical after liquid crystal indicator is closed with the output signal of said second source signal wire.
The said first power supply signal line is connected with the grid of said the 14 thin film transistor (TFT), and said second source signal wire is connected with source electrode with the grid of said the 15 thin film transistor (TFT).
A kind of liquid crystal indicator comprises several grades of above-mentioned gate driver circuits, and wherein, first order gate driver circuit is connected with the enabling signal line of said liquid crystal indicator, is connected through the enabling signal line between other grade gate driver circuit and the gate driver circuit.
In the embodiment of the utility model, when liquid crystal indicator was closed, gate driver circuit output signal was under the effect of the output signal of second source signal wire; Keep high potential a period of time; Make the TFT conducting, charged particle residual on the pixel electrode can be transferred on the data line, is transferred to public electrode via data line again; Last via a certain circuit board that is connected with public electrode, charged particle with electric charge and airborne charged particle neutralize, be exhausted.Realized that after liquid crystal indicator was closed, pixel electrode discharged rapidly, the transient function of afterimage has improved picture quality during shutdown.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiment of the utility model, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the gate driver circuit synoptic diagram of the GIP type liquid crystal indicator of prior art;
Fig. 2 is the gate driver circuit timing waveform of the GIP type liquid crystal indicator of prior art;
Fig. 3 is the shift register cell synoptic diagram of GIP type liquid crystal indicator among the utility model embodiment;
Fig. 4 is the gate driver circuit synoptic diagram of GIP type liquid crystal indicator among the utility model embodiment;
Fig. 5 is the circuit diagram of output second source signal line among the utility model embodiment;
Fig. 6 is the gate driver circuit timing waveform of GIP type liquid crystal indicator among the utility model embodiment.
Embodiment
The utility model embodiment provides a kind of shift register, gate driver circuit and liquid crystal indicator thereof, can be implemented in the liquid crystal indicator power-off after afterimage rapidly disappear, improved the image quality of liquid crystal indicator.
Below in conjunction with accompanying drawing the utility model embodiment is described in detail.
The utility model embodiment provides a kind of shift register, gate driver circuit and liquid crystal indicator thereof, preferably, is that example describes with GIP type shift register, gate driver circuit and liquid crystal indicator thereof.
As shown in Figure 3; This GIP type shift register comprises: pull-up unit 11, on draw driver element 12, drop-down unit 13, drop-down driver element 14 and reset unit 15; Also comprise with pull-up unit 11 and being connected; Be used for after GIP type liquid crystal indicator is closed the grid line of gate driver circuit and the isolated location 16 of said pull-up unit 11 disconnections; And be connected with the grid line of gate driver circuit, be used for closing the switch element 17 that the grid line current potential of gate driver circuit is improved in the back at said GIP type liquid crystal indicator.
As shown in Figure 4; Said pull-up unit 11 comprises the 3rd thin film transistor (TFT) M3; The grid of said the 3rd thin film transistor (TFT) M3 connects the drain electrode of the first film transistor M1; The source electrode of M3 connects first signal wire that is used for providing first clock signal clk to said shift register, and the drain electrode of M3 connects the grid line of gate driver circuit;
Draw driver element 12 to comprise the first film transistor M1, the 13 thin film transistor (TFT) M13 and capacitor C 1 on said; The source electrode of said the first film transistor M1 is connected the enabling signal line that is used for providing drive signal STV to said shift register with grid; The drain electrode of M1 is connected with an end of capacitor C 1; The grid of said the 13 thin film transistor (TFT) M13 be used for providing the secondary signal line of second clock signal CLKB to be connected to shift register; The source electrode of M13 be used for providing the enabling signal line of drive signal STV to be connected to said shift register; The drain electrode of M13 is connected with the drain electrode of the first film transistor M1, and an end of capacitor C 1 is connected with the drain electrode of the first film transistor M1, and the other end is connected with the drain electrode of the 3rd thin film transistor (TFT) M3;
Said drop-down unit 13 comprises the tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11 and the 12 thin film transistor (TFT) M12; The grid of said the tenth thin film transistor (TFT) M10 is connected with the drain electrode of the 5th thin film transistor (TFT) M5; The source electrode of M10 is connected with the drain electrode of the first film transistor M1; The drain electrode of M10 be used for providing the degrade signal line of low level VSS to be connected to said shift register; The grid of said the 11 thin film transistor (TFT) M11 is connected with the drain electrode of the 5th thin film transistor (TFT) M5; The source electrode of M11 is connected with the drain electrode of the 3rd thin film transistor (TFT) M3, the drain electrode of M11 be used for providing the degrade signal line of low level VSS to be connected to said shift register, the source electrode of said the 12 thin film transistor (TFT) M12 is connected with the drain electrode of the 3rd thin film transistor (TFT) M3; The grid of M12 be used for providing the secondary signal line of second clock signal CLKB to be connected to said shift register, the drain electrode of M12 be used for providing the degrade signal line of low level VSS to be connected to said shift register;
Said drop-down driver element 14 comprises the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9; The grid of said the 5th thin film transistor (TFT) M5 is connected with the drain electrode of said the 9th thin film transistor (TFT) M9; The source electrode of M5 be used for providing the secondary signal line of second clock signal CLKB to be connected to said shift register; The drain electrode of M5 is connected with the source electrode of said the tenth thin film transistor (TFT) M10; The grid of said the 6th thin film transistor (TFT) M6 is connected with the grid of said the 3rd thin film transistor (TFT) M3; The source electrode of M6 is connected with the drain electrode of said the 5th thin film transistor (TFT) M5; The drain electrode of M6 be used for providing the degrade signal line of low level VSS to be connected to said shift register; The grid of said the 8th thin film transistor (TFT) M8 is connected with the grid of said the 6th thin film transistor (TFT) M6, and the source electrode of M8 is connected with the drain electrode of the 9th thin film transistor (TFT) M9, the drain electrode of M8 be used for providing the degrade signal line of low level VSS to be connected to said shift register; The grid of said the 9th thin film transistor (TFT) M9 and source electrode be used for providing the secondary signal line of second clock signal CLKB to be connected to said shift register, the drain electrode of M9 is connected with the grid of said the 5th thin film transistor (TFT) M5 and the source electrode of the 8th thin film transistor (TFT) M8;
Said reset unit 15 comprises the second thin film transistor (TFT) M2 and the 4th thin film transistor (TFT) M4; The grid of the said second thin film transistor (TFT) M2 is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of M2 is connected with the grid of said the 3rd thin film transistor (TFT) M3; The drain electrode of M2 be used for providing the degrade signal line of low level VSS to be connected to said shift register; The grid of said the 4th thin film transistor (TFT) M4 is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of M4 is connected with the drain electrode of said the 3rd thin film transistor (TFT) M3, the drain electrode of M4 be used for providing the degrade signal line of low level VSS to be connected to said shift register.
Said isolated location 16 comprises the 14 thin film transistor (TFT) M14; The grid of said the 14 thin film transistor (TFT) M14 connects the first power supply signal line that is used for providing drive signal VDD to said isolated location; The source electrode of M14 connects the drain electrode of the 3rd thin film transistor (TFT) M3 of said pull-up unit 11, and the drain electrode of M14 connects the grid line of said gate driver circuit.
Said switch element 17 comprises the 15 thin film transistor (TFT) M15; The grid of said the 15 thin film transistor (TFT) M15 is connected the second source signal wire that is used for providing drive signal VDDB to said switch element with source electrode, the drain electrode of M15 connects the grid line of said gate driver circuit.
The utility model embodiment also provides a kind of GIP type gate driver circuit; As shown in Figure 4; Comprise signal wire and above-mentioned shift register; Said signal wire comprises: be used for to said shift register provide drive signal STV the enabling signal line, be used for to said shift register provide low level VSS the degrade signal line, be used for first signal wire of first clock signal clk being provided and being used for providing the secondary signal line of second clock signal CLKB to said shift register to said shift register, also comprise: the first power supply signal line and the second source signal wire that is used for providing drive signal VDDB that are used for providing drive signal VDD to said switch element to said isolated location;
The output signal VDD of the said first power supply signal line is always high level when GIP type liquid crystal indicator operate as normal, the output signal VDDB of said second source signal wire is always low level when GIP type liquid crystal indicator operate as normal; It is identical that the output signal VDD of the said first power supply signal line and the output signal VDDB of said second source signal wire close the back at GIP type liquid crystal indicator.
By on can know, exist certain variation relation between the output signal VDD of the first power supply signal line among Fig. 4 and the output signal VDDB of second source signal wire, can find out the concrete variation relation between VDD and the VDDB according to Fig. 5.
As shown in Figure 5, the grid of the 16 thin film transistor (TFT) M16 connects capacitor C 2, and source electrode connects the first power supply signal line, and drain electrode connects the second source signal wire; The grid of the 17 thin film transistor (TFT) M17 connects the first power supply signal line; Source electrode connects the second source signal wire; Drain electrode connects the degrade signal line; VDDB is equivalent to the output signal of circuit shown in Figure 5, and the waveform sequential chart of VDD and VDDB is as shown in Figure 6, the variation relation of detailed hereafter VDD and VDDB.
When GIP type liquid crystal indicator operate as normal; The output signal VDD of the first power supply signal line is a noble potential; The then source electrode of M17 and drain electrode conducting, the drain electrode of M17 connects the degrade signal line, and the second source signal wire is equivalent to directly be connected with the degrade signal line; Output signal VDDB is the low level VSS of degrade signal line, so the output signal VDDB of second source signal wire is always low level when GIP type liquid crystal indicator operate as normal.
When GIP type liquid crystal indicator is closed; Promptly this moment GIP type liquid crystal indicator power supply break off, the output signal VDD of the first power supply signal line not saltus step immediately to electronegative potential, but through after a while excessively slowly drop to electronegative potential; When VDD is noble potential; Capacitor C 2 is in charged state, and when VDD began to descend, capacitor C 2 began discharge.When selecting the 16 suitable thin film transistor (TFT) M16 and the 17 thin film transistor (TFT) M17 can be implemented in VDD to begin to descend the source electrode of the 17 thin film transistor (TFT) M17 with drain no longer conducting; And the 16 thin film transistor (TFT) M16 is under the discharge process of capacitor C 2 and before capacitor C 2 discharge processes finish, source electrode with drain still conducting.Then be equivalent to this moment second source signal wire and directly be connected with the first power supply signal line, it is identical with the output signal VDD of the first power supply signal line that the second source signal wire is exported signal VDDB.
The said first power supply signal line is connected with the grid of said the 14 thin film transistor (TFT) M14, and said second source signal wire is connected with source electrode with the grid of said the 15 thin film transistor (TFT) M15.
The utility model embodiment also provides a kind of GIP type liquid crystal indicator; Comprise several grades of above-mentioned gate driver circuits; Wherein, First order gate driver circuit is connected with the enabling signal line of said liquid crystal indicator, is connected through the enabling signal line between other grade gate driver circuit and the gate driver circuit.
Promptly except the first order; The enabling signal line of each grade gate driver circuit is connected with the grid line of upper level gate driver circuit; Each grade grid line is when having useful signal output; The next stage gate driver circuit receives this useful signal and starts, and can realize lining by line scan of all grid lines of liquid crystal indicator thus.
To first order gate driver circuit; Like Fig. 4 and shown in Figure 6, when GIP type liquid crystal indicator operate as normal, the output signal VDDB of the output signal VDD of the first power supply signal line and second source signal wire is opposite at this moment; VDD is a noble potential; VDDB is an electronegative potential, and the grid of said first power supply signal line and said the 14 thin film transistor (TFT) M14 is connected, and the grid of said second source signal wire and said the 15 thin film transistor (TFT) M15 is connected with source electrode.Then the grid of the 14 thin film transistor (TFT) M14 is a high level at this moment, its source electrode and drain electrode conducting, and the grid line that is equivalent to gate driver circuit directly is connected with the drain electrode of M3; And the 15 thin film transistor (TFT) M15 is not switched on, and the output signal VDDB of second source signal wire does not impact the output signal Gate1 of this gate driver circuit.
When GIP type liquid crystal indicator is closed; Promptly the power supply of GIP type liquid crystal indicator breaks off at this moment, and by noted earlier, first power supply signal line output this moment signal VDD is identical with second source signal wire output signal VDDB; Select suitable the 14 thin film transistor (TFT) M14 and the 15 thin film transistor (TFT) M15; Can make that under the effect of identical VDD of current potential and VDDB the source electrode that grid connects the M14 of the first power supply signal line breaks off the disconnection of M14 with drain electrode; Make the grid line of this gate driver circuit and the shift register of this gate driver circuit keep apart, prevent to give the discharge deleterious impact of grid line at power remove backward shift register; And grid connects the source electrode and drain electrode conducting of second source signal wire M15; To the grid line output output signal Gate1 identical of this gate driver circuit with VDDB, when the Gate1 current potential is higher than certain value, the TFT conducting; Charged particle residual on the pixel electrode can be transferred on the data line; Be transferred to public electrode via data line again, last via a certain circuit board that is connected with public electrode, charged particle with electric charge and airborne charged particle neutralize, be exhausted.
Need to prove; Though said process is to explain with first order shift register; But because the structure of each grade gate driver circuit is in full accord; When realizing that the pairing pixel electrode of first order gate driver circuit discharges rapidly, the pairing pixel electrode of other grade gate driver circuit has also been realized rapid discharge.
In the technical scheme of present embodiment, when liquid crystal indicator was closed, gate driver circuit output signal was under the effect of the output signal of second source signal wire; Keep high potential a period of time; Make the TFT conducting, charged particle residual on the pixel electrode can be transferred on the data line, is transferred to public electrode via data line again; Last via a certain circuit board that is connected with public electrode, charged particle with electric charge and airborne charged particle neutralize, be exhausted.Realized that after liquid crystal indicator was closed, pixel electrode discharged rapidly, the transient function of afterimage has improved picture quality during shutdown.This utility model manufacture craft realizes on existing streamline easily, when practicing thrift cost, reaches the purpose of rapid elimination shutdown image retention.
The above; Be merely the embodiment of the utility model; But the protection domain of the utility model is not limited thereto; Any technician who is familiar with the present technique field can expect changing or replacement in the technical scope that the utility model discloses easily, all should be encompassed within the protection domain of the utility model.Therefore, the protection domain of the utility model should be as the criterion with the protection domain of said claim.
Claims (7)
1. shift register; Said shift register comprises: pull-up unit, on draw driver element, drop-down unit, drop-down driver element and reset unit; It is characterized in that; Also comprise with pull-up unit and being connected; Be used for after GIP type liquid crystal indicator is closed the isolated location that grid line and said pull-up unit with gate driver circuit break off, and be connected, be used for closing the switch element of the grid line current potential of back raising gate driver circuit at said GIP type liquid crystal indicator with the grid line of gate driver circuit.
2. shift register according to claim 1 is characterized in that,
Said pull-up unit comprises the 3rd thin film transistor (TFT); The grid of said the 3rd thin film transistor (TFT) connects the first film transistor drain; The source electrode of said the 3rd thin film transistor (TFT) connects first signal wire that is used for providing first clock signal to said shift register, and the drain electrode of said the 3rd thin film transistor (TFT) connects the grid line of gate driver circuit;
Draw driver element to comprise the first film transistor, the 13 thin film transistor (TFT) and electric capacity on said; The transistorized source electrode of said the first film is connected the enabling signal line that is used for providing drive signal to said shift register with grid; Said the first film transistor drain is connected with an end of electric capacity; The grid of said the 13 thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to shift register; The source electrode of said the 13 thin film transistor (TFT) be used for providing the enabling signal line of drive signal to be connected to said shift register; The drain electrode of said the 13 thin film transistor (TFT) is connected with the first film transistor drain, and an end of electric capacity is connected with the first film transistor drain, and the other end is connected with the drain electrode of the 3rd thin film transistor (TFT);
Said drop-down unit comprises the tenth thin film transistor (TFT), the 11 thin film transistor (TFT) and the 12 thin film transistor (TFT); The grid of said the tenth thin film transistor (TFT) is connected with the drain electrode of the 5th thin film transistor (TFT); The source electrode of said the tenth thin film transistor (TFT) is connected with the first film transistor drain; The drain electrode of said the tenth thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 11 thin film transistor (TFT) is connected with the drain electrode of the 5th thin film transistor (TFT); The source electrode of said the 11 thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT); The drain electrode of said the 11 thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The source electrode of said the 12 thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), the grid of said the 12 thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to said shift register, the drain electrode of said the 12 thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register;
Said drop-down driver element comprises the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT); The grid of said the 5th thin film transistor (TFT) is connected with the drain electrode of said the 9th thin film transistor (TFT); The source electrode of said the 5th thin film transistor (TFT) be used for providing the secondary signal line of second clock signal to be connected to said shift register; The drain electrode of said the 5th thin film transistor (TFT) is connected with the source electrode of said the tenth thin film transistor (TFT); The grid of said the 6th thin film transistor (TFT) is connected with the grid of said the 3rd thin film transistor (TFT); The source electrode of said the 6th thin film transistor (TFT) is connected with the drain electrode of said the 5th thin film transistor (TFT); The drain electrode of said the 6th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 8th thin film transistor (TFT) is connected with the grid of said the 6th thin film transistor (TFT), and the source electrode of said the 8th thin film transistor (TFT) is connected with the drain electrode of the 9th thin film transistor (TFT), the drain electrode of said the 8th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 9th thin film transistor (TFT) and source electrode be used for providing the secondary signal line of second clock signal to be connected to said shift register, the drain electrode of said the 9th thin film transistor (TFT) is connected with the grid of said the 5th thin film transistor (TFT) and the source electrode of the 8th thin film transistor (TFT);
Said reset unit comprises second thin film transistor (TFT) and the 4th thin film transistor (TFT); The grid of said second thin film transistor (TFT) is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of said second thin film transistor (TFT) is connected with the grid of said the 3rd thin film transistor (TFT); The drain electrode of said second thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register; The grid of said the 4th thin film transistor (TFT) is connected with the enabling signal line of the next stage gate driver circuit of the gate driver circuit that comprises said shift register; The source electrode of said the 4th thin film transistor (TFT) is connected with the drain electrode of said the 3rd thin film transistor (TFT), the drain electrode of said the 4th thin film transistor (TFT) be used for providing low level degrade signal line to be connected to said shift register.
3. shift register according to claim 1 is characterized in that,
Said isolated location comprises the 14 thin film transistor (TFT); The grid of said the 14 thin film transistor (TFT) connects the first power supply signal line that is used for providing drive signal to said isolated location; The source electrode of said the 14 thin film transistor (TFT) connects the drain electrode of the 3rd thin film transistor (TFT) of said pull-up unit, and the drain electrode of said the 14 thin film transistor (TFT) connects the grid line of said gate driver circuit.
4. shift register according to claim 1 is characterized in that,
Said switch element comprises the 15 thin film transistor (TFT); The grid of said the 15 thin film transistor (TFT) is connected the second source signal wire that is used for providing drive signal to said switch element with source electrode, the drain electrode of said the 15 thin film transistor (TFT) connects the grid line of the gate driver circuit that comprises said shift register.
5. gate driver circuit; Comprise signal wire and like each described shift register of claim 1 to 4; Said signal wire comprises: enabling signal line, degrade signal line, first signal wire and secondary signal line; It is characterized in that, also comprise: the first power supply signal line and the second source signal wire that is used for providing drive signal that are used for providing drive signal to said switch element to said isolated location;
The output signal of the said first power supply signal line is always high level when the liquid crystal indicator operate as normal, the output signal of said second source signal wire is always low level when the liquid crystal indicator operate as normal;
The output signal of the said first power supply signal line is identical after liquid crystal indicator is closed with the output signal of said second source signal wire.
6. gate driver circuit according to claim 5 is characterized in that,
The said first power supply signal line is connected with the grid of said the 14 thin film transistor (TFT), and said second source signal wire is connected with source electrode with the grid of said the 15 thin film transistor (TFT).
7. liquid crystal indicator; It is characterized in that; Comprise several grades like claim 5 or 6 described gate driver circuits; Wherein, first order gate driver circuit is connected with the enabling signal line of said liquid crystal indicator, is connected through the enabling signal line between other grade gate driver circuit and the gate driver circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120478684 CN202332230U (en) | 2011-11-25 | 2011-11-25 | Shift register, gate drive circuit and liquid crystal display device thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120478684 CN202332230U (en) | 2011-11-25 | 2011-11-25 | Shift register, gate drive circuit and liquid crystal display device thereof |
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| Publication Number | Publication Date |
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| CN202332230U true CN202332230U (en) | 2012-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201120478684 Expired - Lifetime CN202332230U (en) | 2011-11-25 | 2011-11-25 | Shift register, gate drive circuit and liquid crystal display device thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103280177A (en) * | 2012-12-05 | 2013-09-04 | 上海中航光电子有限公司 | Grid driver and detecting method thereof |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| CN105185293A (en) * | 2015-10-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Display panel, driving method thereof, and display device |
| WO2016078264A1 (en) * | 2014-11-19 | 2016-05-26 | 京东方科技集团股份有限公司 | Shift register unit, shift register, grid driving circuit and display device |
| CN109410886A (en) * | 2018-12-27 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN110727149A (en) * | 2019-11-20 | 2020-01-24 | 京东方科技集团股份有限公司 | Display substrate, preparation method and display device |
| CN113744679A (en) * | 2021-07-29 | 2021-12-03 | 北京大学深圳研究生院 | Grid driving circuit and display panel |
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2011
- 2011-11-25 CN CN 201120478684 patent/CN202332230U/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103280177A (en) * | 2012-12-05 | 2013-09-04 | 上海中航光电子有限公司 | Grid driver and detecting method thereof |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| CN103700358B (en) * | 2013-12-31 | 2016-06-15 | 合肥京东方光电科技有限公司 | A kind of GIP type liquid crystal indicator |
| US10140938B2 (en) | 2013-12-31 | 2018-11-27 | Boe Technology Group Co., Ltd. | GIP type liquid crystal display device |
| WO2016078264A1 (en) * | 2014-11-19 | 2016-05-26 | 京东方科技集团股份有限公司 | Shift register unit, shift register, grid driving circuit and display device |
| CN105185293A (en) * | 2015-10-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Display panel, driving method thereof, and display device |
| CN105185293B (en) * | 2015-10-19 | 2017-10-24 | 京东方科技集团股份有限公司 | A kind of display panel, its driving method and display device |
| CN109410886A (en) * | 2018-12-27 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN110727149A (en) * | 2019-11-20 | 2020-01-24 | 京东方科技集团股份有限公司 | Display substrate, preparation method and display device |
| CN113744679A (en) * | 2021-07-29 | 2021-12-03 | 北京大学深圳研究生院 | Grid driving circuit and display panel |
| CN113744679B (en) * | 2021-07-29 | 2024-02-09 | 北京大学深圳研究生院 | Gate drive circuit and display panel |
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Granted publication date: 20120711 |