CN202331438U - Digital program disk encryption system - Google Patents
Digital program disk encryption system Download PDFInfo
- Publication number
- CN202331438U CN202331438U CN2011204410327U CN201120441032U CN202331438U CN 202331438 U CN202331438 U CN 202331438U CN 2011204410327 U CN2011204410327 U CN 2011204410327U CN 201120441032 U CN201120441032 U CN 201120441032U CN 202331438 U CN202331438 U CN 202331438U
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Abstract
A digital program disk encryption system comprises a digital program hard disk with an SATA (Serial Advanced Technology Attachment) interface, an encryption circuit and an integral sealed hard disk box. The digital program hard disk and the encryption system are fixedly packed in the sealed hard disk box; pins 1 to 7, 13, 17 to 22 of an encryption circuit interface CN1 are correspondingly connected with pins 1 to 7, 13, and 17 to 22 of an encryption interface CN2; pins 11, 12 and 13 of the encryption interface CN2 are grounded; an ICSPDAT and an ICSPCLK at the interface CN1 are correspondingly connected with pins 1 and 3 of an encryption chip U1; the pin 1 of the encryption chip U1 is connected with a 3.3V power supply via a resistor R3; the pin 3 of the encryption chip U1 is connected with the 3.3V power supply via a resistor R4; the pin 2 of the encryption chip U1 is grounded; the pin 5 of the encryption chip U1 is connected with the 3.3V power supply; the pin 6 of the encryption chip U1 is connected with a grid G of a field-effect tube Q1 and one end of a resistor R2; a source electrode S of the filed-effect tube Q1 is connected with the other end of the resistor R2 and a +5V power supply; a drain electrode D of the field-effect tube Q1 is connected with the V5 end of the interface CN2.
Description
Technical field
The utility model relates to a kind of digital program disk encryption system, belongs to electronic technology field.
Background technology
The equipment of digital movies mobile playing is a lot of on the market; There are software package and program data in the hard disk in the projection equipment; If hard disc data is not through encrypting; Will be stolen, read, distort and delete by the disabled user and can not get effective protection, thereby cause the massive losses that to retrieve to producer; Data encryption is the important means of protection digital asset information security; So More and more factories is all in the most effectual way of seeking fixed disk data enciphering energetically.
At present, two kinds on general component software of data protection technology that adopts in the hard disk and hardware, the former utilizes software to encrypt, and the latter accomplishes special encryption chip to encrypt from hardware view in the hard disk.The HD encryption of carrying out with the software program mode is easy to be read and crack through update routine; So think that at present hardware encipher is more reliable; The security of traditional hardware encryption method of the prior art is still undesirable, and still there is very big hidden danger in the safety of hard disc data.
The utility model content
The utility model problem to be solved is to above defective, and a kind of safe digital program disk encryption system is provided.
For addressing the above problem; The utility model adopts following technical scheme: the digital program disk encryption system; It is characterized in that: said digital program disk encryption system comprises digital program hard disk, the encrypted circuit of SATA interface and the sealing hard-disk cartridge that can not disassemble, and digital program hard disk and encrypted circuit cure package are in the sealing hard-disk cartridge;
Encrypted circuit comprises interface CN1, interface CN2, encryption chip U1, FET Q1, resistance R 2, resistance R 3 and resistance R 4;
Interface CN1 is used for being connected with external unit; Interface CN2 is used for connecting encrypted circuit and digital program hard disk; 1 to 7 pin of 1 to 7 pin of interface CN1,13 pin and 17 to 22 pin and interface CN2,13 pin and 17 to 22 pin are corresponding to be connected 11, the 12 and 13 pin ground connection of interface CN2; ICSPDAT on the interface CN1 and ICSPCLK and encryption chip U1 1,3 pin is corresponding is connected; 1 pin of encryption chip U1 connects the 3.3V power supply through resistance R 3; 3 pin of encryption chip U1 connect the 3.3V power supply through resistance R 4; The 2 pin ground connection of encryption chip U1; 5 pin of encryption chip U1 connect the 3.3V power supply; 6 pin of encryption chip U1 connect the grid G of FET Q1, an end of resistance R 2; The other end of the source S connecting resistance R2 of FET Q1 and+5V power supply; The V5 end of the drain D connection interface CN2 of FET Q1.
Further improvement as technique scheme:
Said digital program disk encryption system comprises:
Interface circuit comprises interface CN3, encryption chip U3, communication interface JP1, capacitor C 4 and capacitor C 5; The corresponding connection of 1,2,3,5,6 pin of 1,2,3,5,6 pin of communication interface JP1 and interface CN3; The corresponding connection of 1,3 pin of 11,12 pin of interface CN3 and encryption chip U3; The 2 pin ground connection of encryption chip U3; 5 pin of encryption chip U3 connect the 3.3V power supply on the communication interface JP1; 14,15 of interface CN3 is connected with 16 pin on the communication interface JP1+5V and through capacitor C 4 ground connection; 20,21 of interface CN3 is connected with 22 pin on the communication interface JP1+12V and through capacitor C 5 ground connection; Interface CN3 adopts standard SATA joint cable to be connected with interface CN1;
Said encrypted circuit comprises:
3.3V power circuit comprises voltage stabilizing chip U2, resistance R 1, capacitor C 1, capacitor C 2 and capacitor C 3; 1 pin of voltage stabilizing chip U2 connect 3 pin, the resistance R 1 of voltage stabilizing chip U2 an end, capacitor C 3 an end and+the 5V power supply; 4 pin of another termination voltage stabilizing chip U2 of resistance R 1; The 2 pin ground connection of voltage stabilizing chip U2; 5 pin of voltage stabilizing chip U2 are the 3.3V output terminal, through capacitor C 1, capacitor C 2 ground connection of parallel connection, the other end ground connection of capacitor C 3.
The utility model adopts above technical scheme; Compared with prior art, have the following advantages: the mode that digital program hard disk and encrypted circuit are cured and the mode of hardware encipher combine effectively, and the digital program hard disk can not be by random taking-up and reading of data; If take out by force; Hard disk will be destroyed, and causing can not the damage of reparation property, thereby the data of protection digital program disk the inside are not illegally stolen.If read the data of digital program disk the inside, must be through system verification; Just encryption chip U1 produces random number and sends to encryption chip U3; Encryption chip U1 was given in passback after encryption chip U3 carried out cryptographic calculation to it; Encryption chip U1 compares the data that the data that self obtain through AES and encryption chip U3 return, and during Data Matching, digital program disk just can proper communication.Protected the data of digital program disk the inside effectively, this method is safe, has good practical value.
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
Description of drawings
Accompanying drawing 2 is the circuit theory diagrams of encrypted circuit among the utility model embodiment;
Accompanying drawing 3 is the circuit theory diagrams of interface circuit among the utility model embodiment;
Among the figure,
1-digital program hard disk, the 2-encrypted circuit, the 3-interface circuit, 4-seals hard-disk cartridge, 5-decoding deck.
Specific embodiment
Embodiment, as shown in Figure 1, the digital program disk encryption system; It is characterized in that: said digital program disk encryption system comprises the digital program hard disk 1, encrypted circuit 2, interface circuit 3 of SATA interface, the sealing hard-disk cartridge 4 that can not disassemble, with the high strength fluid sealant with digital program hard disk 1 and encrypted circuit 2 cure package in sealing hard-disk cartridge 4, make to be integrated; Interface CN1 on the encrypted circuit 2 only leaks outside; The user can not hard disk is random taking-up, if take out by force, hard disk will be destroyed; Causing can not the damage of reparation property, thus the data of protection digital program disk the inside; Digital program hard disk 1 is connected through the SATA interface with encrypted circuit 2; Encrypted circuit 2 is connected through the SATA interface cable with interface circuit 3.
As shown in Figure 2, encrypted circuit 2 comprises interface CN1, interface CN2, encryption chip U1, FET Q1, resistance R 2, resistance R 3 and resistance R 4; The PIC10F202 that encryption chip U1 selects for use MicroChip company to produce, this chip is a kind of 8 single-chip microcomputers of CMOS process structure.Select for use this kind of chip that following reason is arranged: 1. its inside carries OTP type ROM, behind the secret fuse failure of interior program of establishing, exists the program among the inner ROM can not read by the external world.2. low-power consumption.3. there is the house dog of setting able to programme its inside, has increased reliability.4. chip volume is little, and the busy line board space seldom;
Interface CN1, model is SATA-Femail_22p, is used for being connected with external unit, be the sealing hard-disk cartridge 4 external interface, be used for interface circuit 3 on interface CN3 be connected; Interface CN2, model is SATA-Femail_22p, is encrypted circuit 2 and the interface that digital program hard disk 1 docks, and is used for connecting encrypted circuit 2 and digital program hard disk 1; 1 to 7 pin of 1 to 7 pin of interface CN1,13 pin and 17 to 22 pin and interface CN2,13 pin and 17 to 22 pin are corresponding to be connected 11, the 12 and 13 pin ground connection of interface CN2; ICSPDAT on the interface CN1 and ICSPCLK and encryption chip U1 1,3 pin is corresponding is connected; 1 pin of encryption chip U1 connects the 3.3V power supply through resistance R 3; 3 pin of encryption chip U1 connect the 3.3V power supply through resistance R 4; The 2 pin ground connection of encryption chip U1; 5 pin of encryption chip U1 connect the 3.3V power supply; 6 pin of encryption chip U1 connect the grid G of FET Q1, an end of resistance R 2; The other end of the source S connecting resistance R2 of FET Q1 and+5V power supply; The V5 of the drain D connection interface CN2 of FET Q1 end, on the interface CN1+on 5V and the encryption chip U1+5V is connected.
As shown in Figure 3, interface circuit 3 comprises interface CN3, encryption chip U3, communication interface JP1, capacitor C 4 and capacitor C 5; The model of interface CN3 is SATA-Femail_22p, and the model of encryption chip U3 is PIC10F202, and the model of communication interface JP1 is MHDR1X8, the corresponding connection of 1,2,3,5,6 pin of 1,2,3,5,6 pin of communication interface JP1 and interface CN3; The corresponding connection of 1,3 pin of 11,12 pin of interface CN3 and encryption chip U3; The 2 pin ground connection of encryption chip U3; 5 pin of encryption chip U3 connect the 3.3V power supply on the communication interface JP1; 14,15 of interface CN3 is connected with 16 pin on the communication interface JP1+5V and through capacitor C 4 ground connection; 20,21 of interface CN3 is connected with 22 pin on the communication interface JP1+12V and through capacitor C 5 ground connection; Interface CN3 adopts standard SATA joint cable to be connected with interface CN1; Communication interface JP1 is the port that communicates with decoding deck 5,1, the 4 and 7 pin ground connection of interface CN3, and all circuit parts are altogether.
As shown in Figure 4, encrypted circuit 2 also comprises the 3.3V power circuit, and the 3.3V power circuit comprises voltage stabilizing chip U2, resistance R 1, capacitor C 1, capacitor C 2 and capacitor C 3; 1 pin of voltage stabilizing chip U2 connect 3 pin, the resistance R 1 of voltage stabilizing chip U2 an end, capacitor C 3 an end and+the 5V power supply; 4 pin of another termination voltage stabilizing chip U2 of resistance R 1; The 2 pin ground connection of voltage stabilizing chip U2; 5 pin of voltage stabilizing chip U2 are the 3.3V output terminal, through capacitor C 1, capacitor C 2 ground connection of parallel connection, the other end ground connection of capacitor C 3.
Principle of work: use a clock line ICSPCLK and a data lines ICSPDAT to communicate between encryption chip U3 and the encryption chip U1, encryption chip U1 sends to encryption chip U3 after producing random number x; Encryption chip U1 uses AES y
m=f (x) carries out computing, obtains data encrypted y
1Meanwhile, encryption chip U3 uses same AES y
n=f (x) encrypts the x that receives, and obtains y
2And return data y
2Give encryption chip U1; Encryption chip U1 is with y
1With y
2Comparing, if unanimity can continue executive routine, will produce a low level signal, make FET Q1 conducting, is 1 power supply of digital program hard disk through interface CN2, starts hard disk.Otherwise program is carried out delay procedure, and recycle turns back to master routine, after continuing to produce random number x, sends to encryption chip U3; Get into next circulation.Encryption chip U1 produces random number, and random number is through the data that the AES on encryption chip U1 and the encryption chip U3 obtains, compare coupling after, hard disk could normal use, has protected hard disc data effectively.
Communication interface JP1 is the port that communicates with other equipment, is decoding deck 5 in this example, and decoding deck 5 is used for reading the data of hard disk the inside, carries out audio/video decoding and handles, the electric signal that converts the identification of the equipment that can be shown and audio frequency apparatus into and play; But be not limited to decoding deck, as long as can be connected application with communication interface JP1 with the equipment that the SATA hard disk is set up proper communication.
Claims (3)
1. digital program disk encryption system; It is characterized in that: said digital program disk encryption system comprises digital program hard disk (1), the encrypted circuit (2) of SATA interface and the sealing hard-disk cartridge (4) that can not disassemble, and digital program hard disk (1) and encrypted circuit (2) cure package are in sealing hard-disk cartridge (4);
Encrypted circuit (2) comprises interface CN1, interface CN2, encryption chip U1, FET Q1, resistance R 2, resistance R 3 and resistance R 4;
Interface CN1 is used for being connected with external unit; Interface CN2 is used for connecting encrypted circuit (2) and digital program hard disk (1); 1 to 7 pin of 1 to 7 pin of interface CN1,13 pin and 17 to 22 pin and interface CN2,13 pin and 17 to 22 pin are corresponding to be connected 11, the 12 and 13 pin ground connection of interface CN2; ICSPDAT on the interface CN1 and ICSPCLK and encryption chip U1 1,3 pin is corresponding is connected; 1 pin of encryption chip U1 connects the 3.3V power supply through resistance R 3; 3 pin of encryption chip U1 connect the 3.3V power supply through resistance R 4; The 2 pin ground connection of encryption chip U1; 5 pin of encryption chip U1 connect the 3.3V power supply; 6 pin of encryption chip U1 connect the grid G of FET Q1, an end of resistance R 2; The other end of the source S connecting resistance R2 of FET Q1 and+5V power supply; The V5 end of the drain D connection interface CN2 of FET Q1.
2. digital program disk encryption system as claimed in claim 1 is characterized in that: said digital program disk encryption system comprises:
Interface circuit (3) comprises interface CN3, encryption chip U3, communication interface JP1, capacitor C 4 and capacitor C 5; The corresponding connection of 1,2,3,5,6 pin of 1,2,3,5,6 pin of communication interface JP1 and interface CN3; The corresponding connection of 1,3 pin of 11,12 pin of interface CN3 and encryption chip U3; The 2 pin ground connection of encryption chip U3; 5 pin of encryption chip U3 connect the 3.3V power supply on the communication interface JP1; 14,15 of interface CN3 is connected with 16 pin on the communication interface JP1+5V and through capacitor C 4 ground connection; 20,21 of interface CN3 is connected with 22 pin on the communication interface JP1+12V and through capacitor C 5 ground connection; Interface CN3 adopts standard SATA joint cable to be connected with interface CN1.
3. according to claim 1 or claim 2 digital program disk encryption system, it is characterized in that: said encrypted circuit (2) comprising:
3.3V power circuit comprises voltage stabilizing chip U2, resistance R 1, capacitor C 1, capacitor C 2 and capacitor C 3; 1 pin of voltage stabilizing chip U2 connect 3 pin, the resistance R 1 of voltage stabilizing chip U2 an end, capacitor C 3 an end and+the 5V power supply; 4 pin of another termination voltage stabilizing chip U2 of resistance R 1; The 2 pin ground connection of voltage stabilizing chip U2; 5 pin of voltage stabilizing chip U2 are the 3.3V output terminal, through capacitor C 1, capacitor C 2 ground connection of parallel connection, the other end ground connection of capacitor C 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204410327U CN202331438U (en) | 2011-11-09 | 2011-11-09 | Digital program disk encryption system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204410327U CN202331438U (en) | 2011-11-09 | 2011-11-09 | Digital program disk encryption system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202331438U true CN202331438U (en) | 2012-07-11 |
Family
ID=46443410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204410327U Expired - Lifetime CN202331438U (en) | 2011-11-09 | 2011-11-09 | Digital program disk encryption system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202331438U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508794A (en) * | 2011-11-09 | 2012-06-20 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN106157998A (en) * | 2015-04-16 | 2016-11-23 | 联想（上海）信息技术有限公司 | Hard disk connector and electronic equipment |
-
2011
- 2011-11-09 CN CN2011204410327U patent/CN202331438U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508794A (en) * | 2011-11-09 | 2012-06-20 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN102508794B (en) * | 2011-11-09 | 2014-04-02 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN106157998A (en) * | 2015-04-16 | 2016-11-23 | 联想（上海）信息技术有限公司 | Hard disk connector and electronic equipment |
| CN106157998B (en) * | 2015-04-16 | 2018-10-12 | 联想（上海）信息技术有限公司 | Hard disk connector and electronic equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Li Lin Inventor after: Mou Dunxiao Inventor after: Wang Guoqiang Inventor after: Zhao Ming Inventor after: Wang Qidong Inventor before: Li Lin Inventor before: Mou Dunxiao Inventor before: Wang Guoqiang |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Encryption system for digital program hard disk Effective date of registration: 20171016 Granted publication date: 20120711 Pledgee: Shandong Gaomi rural commercial bank Limited by Share Ltd Pledgor: Shandong Huiying Science and Technology Media Co., Ltd. Registration number: 2017980000417 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210922 Granted publication date: 20120711 Pledgee: Shandong Gaomi rural commercial bank Limited by Share Ltd. Pledgor: SHANDONG HUIYING SCIENCE AND TECHNOLOGY MEDIA Co.,Ltd. Registration number: 2017980000417 |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120711 |