CN202309653U - Power-down delay memory circuit for electric appliance - Google Patents
Power-down delay memory circuit for electric appliance Download PDFInfo
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- CN202309653U CN202309653U CN2011203882212U CN201120388221U CN202309653U CN 202309653 U CN202309653 U CN 202309653U CN 2011203882212 U CN2011203882212 U CN 2011203882212U CN 201120388221 U CN201120388221 U CN 201120388221U CN 202309653 U CN202309653 U CN 202309653U
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- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
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Abstract
The utility model provides an electrical apparatus falls electric power time delay memory circuit, its is connected with the chip, includes the third resistance of being connected with the AD mouth of chip, the other end of third resistance is connected with the positive pole of first diode and the one end of second resistance respectively, the other end and the power of second resistance are connected, the negative pole of first diode is connected with the one end of first electric capacity, the other end ground connection of first electric capacity, it has a first resistance to connect in parallel on the first electric capacity. The utility model has the advantages that: the delay time is long after power failure, the delay time is controllable, and the cost is low.
Description
Technical field
The utility model relates to a kind of electrical equipment power down time-delay memory circuit.
Background technology
Along with the intelligentized development of small household appliances, there is multiple function to accomplish automatically.General fuzzy control function all be chip according to the time, temperature, conditions such as power are judged next step action.For example when automatic function was carried out, electrical network had the power failure of short time, when the Rest pin voltage of chip is lower than resetting voltage, and chip reset, all functions start anew or get into holding state, can't accomplish function corresponding.
Traditional power down protection is the capacity that on chip power VCC, strengthens electric capacity, jumbo capacitor, and when the electrical network short time had a power failure, the electric weight that stores in the capacitor kept the power supply to chip.Capacitor generally can be delayed time 10 seconds in, and than higher, condenser capacity increases to the requirement of circuit, and delay time increases, but cost also increases thereupon.
Also have in the traditional scheme when being checked through the electrical network no-voltage, a flag bit is set at chip internal.When powering on once more, whether chip detection has the power down flag bit, if having, the state when just following power down carries out next step action.Though this scheme does not increase cost, but can't judge the power down time, if the power down overlong time when start working in the centre, has not reached expected effect more.
Summary of the invention
The purpose of the utility model is to solve existing power down protection circuit and has the problem that cost is high, can't judge the power down time, and the electrical equipment power down time-delay that a kind of cost is low, delay time is controlled memory circuit is provided.
For the technical scheme that reaches the employing of goal of the invention the utility model is:
A kind of electrical equipment power down time-delay memory circuit; It is connected with chip, it is characterized in that: comprise the 3rd resistance that an end is connected with the AD mouth of chip, the other end of said the 3rd resistance connects the anode of first diode and an end of second resistance respectively; The other end of said second resistance is connected with power supply; The negative electrode of said first diode is connected with an end of first electric capacity, and the other end ground connection of said first electric capacity is parallel with one first resistance on said first electric capacity.
Further, the resistance of said first resistance is much larger than the resistance of the 3rd resistance.
The utility model be not through first electric capacity to chip power supply, but consume through the electric weight of first resistance to first electric capacity, detect potential change and then judgement time then and change, so the capacity of first electric capacity is not had too big requirement, so the cost minimizing; Secondly the technical scheme of the utility model can be judged the power down time, is judged whether to continue processing according to the power down time by chip then, and it is controlled to delay time, in use more convenient, practical.
Description of drawings
Fig. 1 is the circuit theory diagrams of the utility model.
Fig. 2 is that the utility model is applied to the routine processes flow chart in the electrical equipment.
Embodiment
Come the utility model is further specified below in conjunction with specific embodiment, but the utility model is not confined to these embodiments.One skilled in the art would recognize that the utility model contained in claims scope all alternatives, improvement project and the equivalents that possibly comprise.
Referring to Fig. 1, a kind of electrical equipment power down time-delay memory circuit, it is connected with chip; Comprise the 3rd resistance R 3 that is connected with the AD mouth of chip; The other end of said the 3rd resistance R 3 is connected with the anode of the first diode D1 and an end of second resistance R 2 respectively, and the other end of said second resistance R 2 is connected with power vd D, and the negative electrode of the said first diode D1 is connected with an end of first capacitor C 1; The other end ground connection of said first capacitor C 1 is parallel with one first resistance R 1 on said first capacitor C 1.
The resistance of said first resistance R 1 is much larger than the resistance of the 3rd resistance R 3.
During the utility model operate as normal, the AD mouth of chip is made as delivery outlet, and electric current gives first capacitor C 1 charging through the 3rd resistance R 3 and the first diode D1.The 3rd resistance R 3 choosings values is less, with first capacitor C 1 and first resistance R, 1 resistance that connects much larger than the 3rd resistance R 3, be in order to guarantee that first capacitor C 1 is filled in very short time.When power down took place, chip power was zero, and single-chip microcomputer quits work.First capacitor C 1 is through 1 discharge of first resistance R, because the existence of the first diode D1, the discharge loop of first capacitor C 1 is unique.When power-down conditions not taking place, the AD pin keeps high potential always, after the power down, and the discharge of first capacitor C 1, electric weight is consumed by first resistance R 1 gradually, and the current potential of AD pin can be than reducing before the outage, even become 0 during discharge off.Wherein discharge time, T was by the common decision of resistance value decision of the capacity of first capacitor C 1 and first resistance R 1, and it can promptly calculate the power down time according to potential change by the in addition record of circuit that clocks in the chip.
Referring to Fig. 2, when electrical network was switched on once more, chip was judged the current potential of AD pin earlier; Circuit is judged the power down time according to the height of current potential by clocking; If then chip was judged and not carried out data initialization within the scope of pre-programmed the power down time, machine will continue processing before.If the power down time, promptly the electric weight in first capacitor C 1 surpassed the regular hour through the discharge of first resistance R 1 above the time of pre-programmed, this moment, data initialization was carried out in the chip judgement, need not continue previous procedure.
It is not to chip power supply through first electric capacity that the utility model provides technical scheme; But consume through the electric weight of first resistance to first electric capacity; Detect potential change and then judgement time then and change, thus the capacity of first electric capacity there is not too big requirement, so cost reduces; The technical scheme that next the utility model provides can be judged the power down time, is judged whether to continue processing according to the power down time by chip then, and it is controlled to delay time, in use more convenient, practical.
Claims (2)
1. electrical equipment power down time-delay memory circuit; It is connected with chip, it is characterized in that: comprise the 3rd resistance that an end is connected with the AD mouth of chip, the other end of said the 3rd resistance connects the anode of first diode and an end of second resistance respectively; The other end of said second resistance is connected with power supply; The negative electrode of said first diode is connected with an end of first electric capacity, and the other end ground connection of said first electric capacity is parallel with one first resistance on said first electric capacity.
2. a kind of electrical equipment power down time-delay memory circuit according to claim 1, it is characterized in that: the resistance of said first resistance is much larger than the resistance of the 3rd resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203882212U CN202309653U (en) | 2011-10-13 | 2011-10-13 | Power-down delay memory circuit for electric appliance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203882212U CN202309653U (en) | 2011-10-13 | 2011-10-13 | Power-down delay memory circuit for electric appliance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202309653U true CN202309653U (en) | 2012-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN2011203882212U Expired - Lifetime CN202309653U (en) | 2011-10-13 | 2011-10-13 | Power-down delay memory circuit for electric appliance |
Country Status (1)
| Country | Link |
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| CN (1) | CN202309653U (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762966A (en) * | 2014-01-10 | 2014-04-30 | 美的集团股份有限公司 | Power failure memory circuit and power failure memory method |
| CN104850018A (en) * | 2014-02-19 | 2015-08-19 | 汤姆逊许可公司 | Electronic switch for simulating a mechanical rocker switch |
| CN105786638A (en) * | 2016-03-22 | 2016-07-20 | 江苏友奥电器有限公司 | Electric control board with power failure memory function |
| CN106292352A (en) * | 2015-05-28 | 2017-01-04 | 广东美的生活电器制造有限公司 | Power-fail memory function module, governor circuit, information-reading method, system and soy bean milk making machine |
| CN107037351A (en) * | 2016-12-15 | 2017-08-11 | 珠海格力电器股份有限公司 | Power failure delay circuit detection circuit and method, power failure delay device and electric appliance |
| CN107045302A (en) * | 2017-03-17 | 2017-08-15 | 浙江绍兴苏泊尔生活电器有限公司 | Food cooking method of food processor and circuit for detecting power-down time |
| CN107436575A (en) * | 2017-07-31 | 2017-12-05 | 浙江绍兴苏泊尔生活电器有限公司 | Power failure protection method and household appliance |
| CN107752763A (en) * | 2016-11-15 | 2018-03-06 | 浙江绍兴苏泊尔生活电器有限公司 | Soybean milk making method of soybean milk maker and circuit for detecting power failure time |
-
2011
- 2011-10-13 CN CN2011203882212U patent/CN202309653U/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762966A (en) * | 2014-01-10 | 2014-04-30 | 美的集团股份有限公司 | Power failure memory circuit and power failure memory method |
| CN104850018A (en) * | 2014-02-19 | 2015-08-19 | 汤姆逊许可公司 | Electronic switch for simulating a mechanical rocker switch |
| CN106292352A (en) * | 2015-05-28 | 2017-01-04 | 广东美的生活电器制造有限公司 | Power-fail memory function module, governor circuit, information-reading method, system and soy bean milk making machine |
| CN106292352B (en) * | 2015-05-28 | 2020-02-28 | 广东美的生活电器制造有限公司 | Power-off memory module, main control circuit, information reading method and system and soybean milk machine |
| CN105786638A (en) * | 2016-03-22 | 2016-07-20 | 江苏友奥电器有限公司 | Electric control board with power failure memory function |
| CN107752763A (en) * | 2016-11-15 | 2018-03-06 | 浙江绍兴苏泊尔生活电器有限公司 | Soybean milk making method of soybean milk maker and circuit for detecting power failure time |
| CN107037351A (en) * | 2016-12-15 | 2017-08-11 | 珠海格力电器股份有限公司 | Power failure delay circuit detection circuit and method, power failure delay device and electric appliance |
| CN107045302A (en) * | 2017-03-17 | 2017-08-15 | 浙江绍兴苏泊尔生活电器有限公司 | Food cooking method of food processor and circuit for detecting power-down time |
| CN107045302B (en) * | 2017-03-17 | 2020-09-08 | 浙江绍兴苏泊尔生活电器有限公司 | Food cooking method of food processor and circuit for detecting power-down time |
| CN107436575A (en) * | 2017-07-31 | 2017-12-05 | 浙江绍兴苏泊尔生活电器有限公司 | Power failure protection method and household appliance |
| CN107436575B (en) * | 2017-07-31 | 2020-11-10 | 浙江绍兴苏泊尔生活电器有限公司 | Power failure protection method and household appliance |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120704 |