CN202276332U - Isolation circuit for UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port - Google Patents
Isolation circuit for UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port Download PDFInfo
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- CN202276332U CN202276332U CN2011203945033U CN201120394503U CN202276332U CN 202276332 U CN202276332 U CN 202276332U CN 2011203945033 U CN2011203945033 U CN 2011203945033U CN 201120394503 U CN201120394503 U CN 201120394503U CN 202276332 U CN202276332 U CN 202276332U
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- uart
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- ncmos
- pipe
- isolation circuit
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Abstract
The utility model discloses an isolation circuit for a UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port, which is characterized in that a CMOS (Complementary Metal Oxide Semiconductor) phase inverter of which two stages have extremely-high input impedance is arranged between the transmitting end of an UART port of a main chip and the corresponding receiving end of a UART port of external hanging equipment; and a pull-up resistor is arranged at the transmitting end of the UART port of the main chip. The isolation circuit has the beneficial effects that an IO (Input/Output) port of the main chip does not need to be additionally occupied; software does not need to be used for control; and the isolation circuit is simple in structure and reliable in application.
Description
Technical field
The utility model relates to a kind of UART circuit, relates in particular to a kind of not extra buffer circuit that is used for UART communication multiplexing port that takies the main control chip port.
Background technology
In band communication function electronic circuit; The IO mouth that contains the master chip of UART communicating circuit; Existing UART communication function has the Download function again, and the UART function is meant that this port of master chip can do debugging with also can plug-in communication apparatus, and the Download function is meant when master chip powers on; If detect this port is low level, then is judged as to be in the pattern that downloads.When using UART plug-in device function, ban use of the Download function generally speaking.But through regular meeting occur as the UART communication function use, when start or UART plug-in device power supply break down; Let the IO mouth of master chip low level occur; Cause master chip to get into the Download pattern, the machine and the plug-in device cisco unity malfunction that make master chip control.Be head it off, increase a buffer circuit at the IO of master chip mouth usually, avoid getting into the Download pattern.
At present, realize that the common method of sort circuit has two kinds: first method is to increase a tri-state gate circuit (as shown in Figure 1) at this port, and by other this triple gate of director port control; Though this kind method is feasible, need take the limited port of controller (IO mouth) resource, especially when the port that controller is not had more than needed; Implement more inconvenient; But also need consideration to open the time point of triple gate, increase the software time sequence control, more complicated; Second method also is to increase a tri-state gate circuit at this port, and utilizes reset signal to control triple gate, is crucial responsive signal because of resetting, and is disturbed easily, and poor reliability does not generally make in this way.Therefore, be necessary to develop the buffer circuit that a kind of more simple and reliable buffer circuit replaces using the preceding method realization.
Summary of the invention
Bring variety of issue for the buffer circuit that solves UART communication multiplexing port uses tri-state gate circuit, the utility model provides simple in structure, reliable application replacement circuit, technical scheme is following:
A kind of buffer circuit that is used for UART communication multiplexing port; It is characterized in that: be provided with the inverter that two-stage has high input impedance between the corresponding receiving terminal of UART port of the transmitting terminal of the UART port of master chip and plug-in device, the transmitting terminal of the UART port of master chip is provided with a pull-up resistor (usually master chip built-in the pull-up resistor that is connected with positive source).
As the further improvement of the utility model, inverter adopts the CMOS inverter; Utilize the high input impedance of CMOS inverter; Make power on or the plug-in device power supply when breaking down the multiplexing port of master chip be in high impedance all the time; Can not have low level state through just drawing on the port like this; Make that master chip and plug-in device all can operate as normal, because inverter has inverter functionality, so adopt two-stage CMOS inverter that the sending and receiving end is consistent to the level of signal.
As shown in Figure 2, the utility model operation principle is following: TXA and RXA are the UART port of master chip, and RX and TX are the UART port corresponding port of plug-in device, when master chip detects TXA and is low level, get into the DOWNLOAD pattern.The CMOS inverter has high input impedance makes master chip under the effect of pull-up resistor, powers on or is in the high resistant high level state during plug-in device power failure in start, thereby can not make that master chip can get into the DOWNLOAD pattern.
The beneficial effect of the utility model is: adopts two-stage CMOS inverter, need not take the IO mouth of master chip in addition, also need not be through software control, and circuit structure is simple, and reliability is high.
Description of drawings
Below in conjunction with accompanying drawing and embodiment, the utility model and useful technique effect thereof are further elaborated, wherein:
Fig. 1 is the tri-state gate circuit symbol.
Fig. 2 is the circuit theory diagrams of the utility model.
Fig. 3 is a kind of practical implementation circuit diagram of the utility model.
Embodiment
Referring to Fig. 3; A kind of buffer circuit that is used for UART communication multiplexing port; The UART port transmitting terminal TXA that it is characterized in that master chip U2 is connected with the grid of NCMOS pipe Q1 respectively, and diode D1 is parallelly connected with resistance R 4, and the plus earth of diode D1, negative electrode are connected with the grid of NCMOS pipe Q1; The source electrode of NCMOS pipe Q1, Q2 links to each other and through resistance R 5 ground connection, the drain electrode of NCMOS pipe Q1 links to each other with the grid of NCMOS pipe Q2 and is connected with power positive end through resistance R 3; NCMOS pipe Q2 drain electrode links to each other with the receiving terminal RX of the UART port of the chip U1 of plug-in device through inductance L 1, and inductance L 1 two ends connect capacitor C 1, the C3 of two ground connection respectively; The UART port transmitting terminal RXA of master chip U2 is connected to ground capacity C2 and links to each other with the transmitting terminal TX of the chip U1 of the UART mouth of plug-in device through inductance L 2, and the transmitting terminal TX of chip U1 and receiving terminal RX are respectively through resistance R 1, the last power positive end that sockets of R2.
Circuit working principle shown in Figure 3 is following: TXA and RXA are the UART port of master chip U2, and RX and TX are the UART port corresponding port of the chip U1 of plug-in device, when master chip detects TXA and is low level, get into the DOWNLOAD pattern.NCMOS pipe Q1 and NCMOS pipe Q2 all use as inverter at this; Wherein the grid of NCMOS pipe Q1 is an input, and the drain electrode of NCMOS pipe Q2 is an output, and the NCMOS pipe has high input impedance; Make master chip (usually master chip is built-in pull-up resistor under the effect of pull-up resistor; So do not draw separately in the resistance view), power on or be in the high resistant high level state during plug-in device power failure in start, thereby can not make that master chip can get into the DOWNLOAD pattern.
The utility model is not constituted any restriction according to above-mentioned specification and specific embodiment; The embodiment that discloses and describe above the utility model is not limited to; To some modifications or the equivalent replacement commonly used of the utility model, also should fall in the protection range of claim of the utility model.
Claims (2)
1. buffer circuit that is used for UART communication multiplexing port; It is characterized in that: be provided with the inverter that two-stage has input impedance between the corresponding receiving terminal of UART port of the transmitting terminal of the UART port of master chip and plug-in device, the transmitting terminal of the UART port of master chip is provided with a pull-up resistor.
2. buffer circuit according to claim 1; It is characterized in that: the source electrode that the inverter that said two-stage has input impedance is managed (Q1), (Q2) by two NCMOS links to each other and through resistance (R5) ground connection; The drain electrode of NCMOS pipe (Q1) links to each other with the grid of NCMOS pipe (Q2) and is connected with power positive end through resistance (R3); Diode (D1) is parallelly connected with resistance (R4); The grid of the plus earth of diode (D1), negative electrode and NCMOS pipe (Q1) connects and composes, and wherein the grid of NCMOS pipe (Q1) is an input, and the drain electrode of NCMOS pipe (Q2) is an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203945033U CN202276332U (en) | 2011-10-17 | 2011-10-17 | Isolation circuit for UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203945033U CN202276332U (en) | 2011-10-17 | 2011-10-17 | Isolation circuit for UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202276332U true CN202276332U (en) | 2012-06-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203945033U Expired - Fee Related CN202276332U (en) | 2011-10-17 | 2011-10-17 | Isolation circuit for UART (Universal Asynchronous Receiver Transmitter) communication multiplexing port |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202276332U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113934673A (en) * | 2021-12-16 | 2022-01-14 | 知迪汽车技术(北京)有限公司 | Data transmission isolation circuit and data transmission equipment |
-
2011
- 2011-10-17 CN CN2011203945033U patent/CN202276332U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113934673A (en) * | 2021-12-16 | 2022-01-14 | 知迪汽车技术(北京)有限公司 | Data transmission isolation circuit and data transmission equipment |
| CN113934673B (en) * | 2021-12-16 | 2022-03-08 | 知迪汽车技术(北京)有限公司 | Data transmission isolation circuit and data transmission equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120613 Termination date: 20191017 |