CN202268155U - Display control circuit of learning machine - Google Patents
Display control circuit of learning machine Download PDFInfo
- Publication number
- CN202268155U CN202268155U CN2011203090745U CN201120309074U CN202268155U CN 202268155 U CN202268155 U CN 202268155U CN 2011203090745 U CN2011203090745 U CN 2011203090745U CN 201120309074 U CN201120309074 U CN 201120309074U CN 202268155 U CN202268155 U CN 202268155U
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- pin
- display control
- microprocessor
- control chip
- tftlcd
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Abstract
The utility model discloses a display control circuit of a learning machine. The display control circuit comprises a microprocessor of the learning machine, a thin film transistor (TFT) liquid crystal display (LCD) display control chip which is connected to the microprocessor, and a triode Q3 which is electrically connected with the TFTLCD display control chip, wherein the type of the microprocessor is LQFP144; and the type of the TFTLCD display control chip is QD028007A0-37. With the microprocessor of the learning machine, the processing capacity of the display control circuit of the learning machine is effectively improved, and the electrostatic interference resistance capacity of the display control circuit is improved.
Description
Technical field
The utility model relates to the learning machine circuit field, is specially a kind of learning machine display control circuit.
Background technology
Learning machine is a kind of electronic instruction series products, is widely used in the student group at home.Learning machine is generally by governor circuit and other peripheral circuit, like formations such as memory circuit, display control circuits.Prior art learning machine display control circuit processing power a little less than, and be subject to electrostatic interference.
The utility model content
The utility model purpose provides a kind of learning machine display control circuit, is subject to the problem of electrostatic interference with the display control circuit that solves the prior art learning machine.
In order to achieve the above object, the technical scheme that the utility model adopted is:
A kind of learning machine display control circuit; The microprocessor that comprises learning machine; And insert the TFTLCD display control chip of microprocessor, the triode Q3 that is electrically connected with the TFTLCD display control chip; Said microprocessor model is LQFP144; TFTLCD display control chip model is QD028007A0-37, it is characterized in that: the DB0-DB7 pin of said TFTLCD display control chip, GND pin be ground connection respectively, and the VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor; The RS pin inserts the MPU_A0 pin of microprocessor, and the WR pin inserts the MPU_WR pin of microprocessor, and the RD pin inserts the MPU_RD pin of microprocessor; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of said triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor respectively; Base stage is connected with the USB_BOOT pin of microprocessor through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter.
The utility model inserts in the microprocessor of learning machine; Display control circuit as learning machine; Through connecing the static impedance device in addition on the pin that inserts at the control signal incoming line, improved the antistatic ability of circuit effectively, the security that the electric capacity that each pin of TFTLCD display control chip inserts can improve circuit; Triode cooperates with the TFTLCD display control chip simultaneously, has improved the circuit signal antijamming capability.The utility model has improved the processing power of display control circuit effectively, has also improved the antistatic ability of display control circuit.
Description of drawings
Fig. 1 is the utility model microcontroller circuit schematic diagram.
Fig. 2 is the utility model TFTLCD display control chip circuit theory diagrams.
Embodiment
Like Fig. 1, shown in Figure 2.A kind of learning machine display control circuit; The microprocessor that comprises learning machine; And insert the TFTLCD display control chip of microprocessor, the triode Q3 that is electrically connected with the TFTLCD display control chip; The microprocessor model is LQFP144; TFTLCD display control chip model is QD028007A0-37, and the DB0-DB7 pin of TFTLCD display control chip, GND pin be ground connection respectively, and the VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor; The RS pin inserts the MPU_A0 pin of microprocessor, and the WR pin inserts the MPU_WR pin of microprocessor, and the RD pin inserts the MPU_RD pin of microprocessor; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor respectively; Base stage is connected with the USB_BOOT pin of microprocessor through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter.
Claims (1)
1. learning machine display control circuit; The microprocessor that comprises learning machine; And insert the TFTLCD display control chip of microprocessor, the triode Q3 that is electrically connected with the TFTLCD display control chip; Said microprocessor model is LQFP144; TFTLCD display control chip model is QD028007A0-37, it is characterized in that: the DB0-DB7 pin of said TFTLCD display control chip, GND pin be ground connection respectively, and the VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor; The RS pin inserts the MPU_A0 pin of microprocessor, and the WR pin inserts the MPU_WR pin of microprocessor, and the RD pin inserts the MPU_RD pin of microprocessor; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of said triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor respectively; Base stage is connected with the USB_BOOT pin of microprocessor through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203090745U CN202268155U (en) | 2011-08-24 | 2011-08-24 | Display control circuit of learning machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203090745U CN202268155U (en) | 2011-08-24 | 2011-08-24 | Display control circuit of learning machine |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202268155U true CN202268155U (en) | 2012-06-06 |
Family
ID=46158940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203090745U Expired - Fee Related CN202268155U (en) | 2011-08-24 | 2011-08-24 | Display control circuit of learning machine |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202268155U (en) |
-
2011
- 2011-08-24 CN CN2011203090745U patent/CN202268155U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120606 Termination date: 20120824 |