CN202221760U - Topological structure of TFT shift register layout - Google Patents

Abstract

The utility model provides a topological structure of a TFT shift register layout. According to the topological structure, the direction of induction holes is perpendicular to the channel direction of transistors; the topological structure comprises the plurality of transistors which are equal in both the channel width and the channel length; and the plurality of transistors are cascaded to be equivalent to a large-size transistor. The utility model also provides a TFT shift register having the above topological structure.

Description

A kind of topological structure of TFT shift register domain

Technical field

The utility model relates to a kind of TFT register circuit, especially based on the PMOS multi-crystal TFT register of metal induced lateral crystallization technology, more specifically, relates to a kind of topological structure of TFT shift register domain.

Background technology

In the past few years, TFT (thin-film transistor) circuit is because of adapting to era development and large-scale application by broad research.

Make the TFT circuit and can select polycrystalline SiTFT (poly-Si TFT), amorphous silicon film transistor (a-Si TFT), OTFT or monocrystalline silicon thin film transistor.As far as amorphous silicon film transistor and OTFT, cause low mobility and high threshold voltage because of there being some inherent shortcoming, thereby hindered the integrated realization of large-scale circuit.In recent years also relevant for the report of on glass substrate, attempting shifting monocrystalline silicon layer.In addition, some documents show that also monocrystalline silicon thin film transistor (SGSi-TFT) might become large scale digital and analog circuitry system through special fabrication processes recently.

To TFT circuit aspect of greatest concern is technique change and manufacturing cost.In order to make TFT electric component group synthesized high-performance circuit, low temperature polycrystalline silicon (LTPS) technology is still used the widest.Metal induced lateral crystallization (MILC) technology is in the technology that is considered to have application prospect aspect the realization p type polycrystalline SiTFT.Yet the crystal boundary intrinsic because of polysilicon can cause negative influence to device performance (like mobility and uniformity), simplifies technology with this and realizes that high performance circuit can run into many difficulties, and process is also very slow.

The TFT shift-register circuit is a circuit very crucial in the integration process of panel system (SOP).Main at present CMOS TFT circuit, the PMOS TFT circuit of adopting.In existing polysilicon process, P type polycrystalline silicon device has lower activation temperature than N type polysilicon, receive the influence of hot carrier's effect little, so device has better stability.And an operation that P type ion of needs injects is compared in the preparation of P type TFT circuit with the preparation of CMOS TFT circuit.Therefore, PMOS TFT circuit has bigger advantage.

Current PMOS technology is main with laser crystallization, relative laser crystallization, and MIC (crystallization inducing metal)/MILC technology cost reduces greatly, but device exists threshold voltage high, and the subthreshold value amplitude of oscillation is big, the low deficiency that waits of mobility.

Therefore often there is following shortcoming in MIC/MILC PMOS TFT shift-register circuit:

(1) for remedying the threshold voltage height, the deficiency that mobility is low, the pumping signal in test has been used bigger potential pulse, but because very big noise and delay appears in the influence of TFT parasitic capacitance, causes wave distortion.

(2) owing to the inhomogeneities of polycrystalline silicon device, the circuit signal distortion of cascade structure can be exaggerated, and finally causes circuit malfunction.

The utility model content

In order to solve the above-mentioned shortcoming of MIC/MILC PMOS TFT shift-register circuit; The utility model provides the topological structure of a kind of TFT shift-register circuit and a kind of TFT shift register domain; Can optimize circuit topological structure; Simplify transistorized quantity in the circuit, remedy and improve the uniformity of device.

The utility model provides a kind of TFT shift-register circuit, comprises 5 P transistor npn npns, is respectively transistor P2, P5, P6, P7, P8; Wherein P6, P7 are common source configuration, and the source electrode of P6, P7 all is connected to VDD, and the grid of P6 is connected to the drain electrode of P7; And join with the source electrode of P8, the grid of P7 is connected to the source electrode of P6 and joins with the source electrode of P5, and the grid of P5 is connected to the drain electrode of P2; The grid of P8 and the grid of P2 are connected to clock signal clk 1, and the drain electrode of P5 is connected with clock signal clk 2.

According to the TFT shift-register circuit that the utility model provides, it is as a unit of shift register.

According to the TFT shift-register circuit that the utility model provides, wherein the P transistor npn npn is the PMOS polycrystalline SiTFT, and this PMOS thin-film transistor is processed by crystallization inducing metal technology or metal induced lateral crystallization technology.

The utility model provides a kind of topological structure of TFT shift register domain, and in this topological structure, the direction of inducing the hole is perpendicular to transistorized channel direction; This topological structure comprises the transistor that a plurality of channel widths are identical and channel length is identical; A plurality of said transistor cascades are to be equivalent to a large-size crystals pipe.

Wherein said cascade comprises series connection and parallel connection.

In the TFT shift-register circuit that the utility model provides, the field-effect mobility of film transistor device is 65.21cm2/Vs, and threshold voltage is-3.5V that the subthreshold value amplitude of oscillation is 0.56V/dec.This paper has carried out special design to improve durability to circuit simultaneously.

Description of drawings

Followingly the utility model embodiment is described further with reference to accompanying drawing, wherein:

Fig. 1 is the schematic diagram of PMOS TFT scanning element;

Fig. 2 is the sequential chart of scanning element;

Fig. 3 is the parasitic capacitance of shift unit;

Fig. 4 is the electric capacity feedthrough effect of P5 pipe grid voltage;

Fig. 5 is the domain topological structure sketch map according to an embodiment of the utility model;

Fig. 6 is the input signal noise margin;

Fig. 7 is the structure chart of scanning circuit.

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is described in detail; Wherein, In the following description, with a plurality of different aspect of describing the utility model, yet; For the one of ordinary skilled in the art, can only utilize some or the entire infrastructure of the utility model or flow process to implement the utility model.For the definition of explaining, set forth specific number, configuration and order, but clearly, do not had also can to implement the utility model under the situation of these specific detail.In other cases, in order not obscure the utility model, will set forth no longer in detail for some well-known characteristics.

Embodiment 1

Present embodiment provides a kind of TFT shift-register circuit, and as one of them unit of shift register (stage), its circuit diagram is as shown in Figure 1; This TFT shift-register circuit comprises 5 P transistor npn npn P2, P5, P6, P7, P8, and wherein P6, P7 are common source configuration, and the source electrode of P6, P7 all is connected to VDD; The grid of P6 is connected to the drain electrode of P7; And join with the source electrode of P8, the grid of P7 is connected to the source electrode of P6 and joins with the source electrode of P5, and the grid of P5 is connected to the drain electrode of P2; The grid of P8 and the grid of P2 are connected to clock signal clk 1, and the drain electrode of P5 is connected with clock signal clk 2.

As shown in Figure 2, be the signal waveforms of this a certain period of TFT shift-register circuit.

P2 is a switching transistor, and P5 is a driving transistors, and the P2 transistor when open circuit signaling keeps big, just can actively effectively be controlled the transistorized grid of P5 by time opening.On the contrary, when open circuit signaling keeps hour, just can not effectively control the transistorized grid of this P5.In this case, the P5 transistor is just keeping the dynamically state of unlatching.Produce the output signal through the P5 driving transistors by CLK2 then.P6, P7, P8 transistor have the function that stores output voltage, are similar to the DRAM circuit of simplification.Each transistorized W/L ratio can be optimized with Smart spice eda tool.

Fig. 3 is an equivalent electric circuit of considering Fig. 1 of ghost effect.As can be seen from Figure 3, when driving function, P5 produces bootstrap effect when launching.Because coupling can appear in CLK2 junction point of traverses and P5 door grid node, therefore can be rebuild dynamic control by the coupling of other nodes.The many stranded Self Control phenomenons of trailing edge that suitable bootstrap effect helps aggravating output waveform also can produce fault, thereby unfavorable to the P5 gate oxide.As shown in Figure 4, be the waveform of pressure drop, can find out bootstrapping pressure drop optimization written treaty 0.7V.

According to the TFT shift-register circuit that present embodiment provides, wherein the PMOS thin-film transistor is a polycrystalline SiTFT, and this PMOS thin-film transistor can be processed by crystallization inducing metal technology or metal induced lateral crystallization technology.

Embodiment 2

Present embodiment provides a kind of topological structure of TFT shift register domain, satisfies following condition at this topological structure:

1) bar shaped induce the hole direction perpendicular to transistorized channel direction, so that transistorized raceway groove side is parallel, as shown in Figure 5 with the direction of growth (being the crystallization direction) of polysilicon grain;

2) the megacryst pipe is divided into the small transistor that a plurality of channel widths are identical and channel length is identical, and makes these small transistor cascades, the mode through cascade is equivalent to a large-sized transistor.

Wherein said cascade comprises series connection and parallel connection: series connection is meant that source/drain electrode joins, the raceway groove series connection, i.e. and the source electrode of the drain electrode of certain small transistor and other small transistor joins.Parallel connection is meant that then source/drain electrode joins, the raceway groove parallel connection, i.e. and certain small transistor drain electrode is joined with another small transistor drain electrode.Large-sized transistor after the cascade can be used as transistor P2, P5, P6, P7, P8 among Fig. 1.

Because transistorized channel direction is parallel with the polysilicon grain direction of growth, therefore can to greatest extent transistorized active area be controlled in the polysilicon grain district, on statistics, guarantee transistorized uniformity.Grid level and raceway groove separately form the fixedly small transistor of channel width and length, are equivalent to a large-sized transistor through the mode that makes the small transistor cascade, help improving whole uniformity like this.

The topological structure of the TFT shift register domain that present embodiment provides can improve the reliability and the accuracy of design object in the technical process.Simultaneously, there is the thickness of the door gate oxide of dynamic memory capacity also in the process of balance boot strap, to be optimized.

Noise margin problem to the TFT shift register of topological structure with TFT shift register domain that present embodiment provides has been carried out strict test.Low level noise tolerance limit when Fig. 6 is the pulse excitation IN that is in the little space scope between the high-low level.The result shows that noise margin can reach about 3V.Therefore, although preceding segment signal output noise less than 3V, pulse signal can not weaken in transmission course and whole shift-register circuit can steady operation.

Embodiment 3

Present embodiment provides a kind of TFT shift register, is made up of the knot (stages) that 180 embodiment 1 provide.

The TFT shift register that Fig. 7 provides for present embodiment is the circuit function module, can find out the general structure of shift register.SIN is an enabling signal, and OUT1 receives ON2, and OUT2 receives ON3......, and the output signal of a last unit is the input signal of next unit.At clock CLK1, accomplish the scan shift function under the driving of CLK2 successively.

Drive down with the 11V supply voltage, this TFT shift register shows good performance at 22Hz in the 220Hz scope.Signal output is less than that the depression of order time is less than 2 μ s under the 8 μ s raised bench time.The output signal can not weaken or distortion from first to a last knot (stage).Can realize high-performance drive circuit, can in panel system, find application based on MILCPMOS.

Certainly, as well known to a person skilled in the art that the quantity of knot (stages) is not limited to 180, can change the quantity of knot according to actual needs.

The TFT shift register that present embodiment provides has the topological structure of the TFT shift register domain that embodiment 2 provides.

Above embodiment only is used to describe the technical scheme of the utility model, rather than the present technique scheme is limited, and any modification, variation, application and embodiment of well known to a person skilled in the art is in the spirit and teachings of the utility model.

Claims (2)

1. the topological structure of a TFT shift register domain, in this topological structure, the direction of inducing the hole is perpendicular to transistorized channel direction; This topological structure comprises the transistor that a plurality of channel widths are identical and channel length is identical; A plurality of said transistor cascades are to be equivalent to a large-size crystals pipe.

2. topological structure according to claim 1, wherein said cascade comprise series connection and parallel connection.

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