CN202133712U - Peak detection circuit - Google Patents
Peak detection circuit Download PDFInfo
- Publication number
- CN202133712U CN202133712U CN201120239466U CN201120239466U CN202133712U CN 202133712 U CN202133712 U CN 202133712U CN 201120239466 U CN201120239466 U CN 201120239466U CN 201120239466 U CN201120239466 U CN 201120239466U CN 202133712 U CN202133712 U CN 202133712U
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- circuit
- adopted
- operational amplifier
- peak
- peak detection
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Abstract
The utility model relates to a peak detection circuit, belonging to the field of electronic circuits. 36-line dual in-line metal shell package is adopted. The peak detection circuit is characterized in that the technology of hybrid integrated circuit is adopted, a resistor is prepared by thick film technology, a paster form is adopted for a capacitor, and bare chips are adopted for an operational amplifier, a comparator, an analogue switch, a trigger and a monostable circuit. Because the thick film hybrid integrated technology is adopted, the circuit board is simplified, and the integration degree of the system is raised. The problems that because a plurality of components are adopted, so reliability of the integral circuit is weak, problem is difficult to search, and maintenance is difficult are solved. Provided is a peak detection circuit which is good in consistency, high in reliability, strong in anti-interference capability, convenient in debugging and easy in maintenance.
Description
Technical field
The utility model relates to electronic circuit field, particularly a kind of peak-detector circuit.
Background technology
Common in the market peak-detector circuit adopts discrete component to constitute more, comprises signal amplification circuit, peak holding circuit and AD sampling The strobe signal circuits.
The major defect of prior art is: the peak-detector circuit that this discrete component constitutes, because element is numerous, make that the circuit global reliability is poor, and going wrong is difficult to search, and repairs difficulty relatively.
The utility model content
To the defective that exists in the prior art, the purpose of the utility model provides the peak-detector circuit that a kind of circuit volume is little, reliability is high, easy to maintenance.
The utility model peak-detector circuit adopts following technical scheme:
A kind of peak-detector circuit adopts the encapsulation of 36 line dual-in-line Cans, and wherein operational amplifier N1 amplifies input signal; Operational amplifier N5, N6, diode VD1, VD2, VD3 and analog switch D2 and Resistor-Capacitor Unit are formed peak holding circuit; Comparer N7A, Sheffer stroke gate D1A, D1D and JK flip-flop D3B provide control signal for analog switch D2; Operational amplifier N3, comparer N4, N7B, Sheffer stroke gate D1B, D1C and JK flip-flop D3A, monostable circuit D4A, D4B and Resistor-Capacitor Unit are formed logical circuit, produce gating signal ST.Peak detector output signal SIG connects AD converter, the start and stop of ST signal controlling AD converter.
The utility model adopts HIC process, and resistance is that thick film technology is made, and electric capacity is that sheet pastes form, and operational amplifier, comparer, analog switch, trigger and monostable circuit are bare chip.
The utility model has the advantages that: owing to adopt the thick film hybrid integration technology to make, simplified circuit board, improved system integration degree.Solved because element is numerous, made that the circuit global reliability is poor, going wrong is difficult to search, and repairs relatively problems such as difficulty, and a kind of high conformity is provided, and reliability is high, and antijamming capability is strong, and debugging is convenient, easily the peak-detector circuit of maintenance.
Description of drawings
The utility model has following accompanying drawing:
Fig. 1 is a circuit module needle-like pin configuration synoptic diagram
Fig. 2 is the upward view of Fig. 1
Fig. 3 is the utility model peak-detector circuit schematic diagram
Embodiment
Embodiment 1: with a peak-detector circuit is example, and the utility model concrete structure is done explanation once more.
Consult Fig. 1 and Fig. 2, the utility model peak-detector circuit modular shape is a cuboid.Consult Fig. 1, the module of thick film circuit includes 36 needle-like pins, divides to be listed in the module both sides.Consult Fig. 3, operational amplifier N1 amplifies input signal; Operational amplifier N5, N6, diode VD1, VD2, VD3 and analog switch D2 and Resistor-Capacitor Unit are formed peak holding circuit; Comparer N7A, Sheffer stroke gate D1A, D1D and JK flip-flop D3B provide control signal for analog switch D2; Operational amplifier N3, comparer N4, N7B, Sheffer stroke gate D1B, D1C and JK flip-flop D3A, monostable circuit D4A, D4B and Resistor-Capacitor Unit are formed logical circuit, produce gating signal ST.Peak detector output signal SIG connects AD converter, the start and stop of ST signal controlling AD converter.
Claims (1)
1. peak-detector circuit; Adopt the encapsulation of 36 line dual-in-line Cans, it is characterized in that: adopt HIC process, resistance is that thick film technology is made; Electric capacity is that sheet pastes form, and operational amplifier, comparer, analog switch, trigger and monostable circuit are bare chip; Circuit comprises: operational amplifier N1 amplifies input signal; Operational amplifier N5, N6, diode VD1, VD2, VD3 and analog switch D2 and Resistor-Capacitor Unit are formed peak holding circuit; Comparer N7A, Sheffer stroke gate D1A, D1D and JK flip-flop D3B provide control signal for analog switch D2; Operational amplifier N3, comparer N4, N7B, Sheffer stroke gate D1B, D1C and JK flip-flop D3A, monostable circuit D4A, D4B and Resistor-Capacitor Unit are formed logical circuit, produce gating signal ST; Peak detector output signal SIG connects AD converter, the start and stop of ST signal controlling AD converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120239466U CN202133712U (en) | 2011-07-08 | 2011-07-08 | Peak detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120239466U CN202133712U (en) | 2011-07-08 | 2011-07-08 | Peak detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202133712U true CN202133712U (en) | 2012-02-01 |
Family
ID=45522477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201120239466U Expired - Fee Related CN202133712U (en) | 2011-07-08 | 2011-07-08 | Peak detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202133712U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267254A (en) * | 2014-08-13 | 2015-01-07 | 如皋市图腾电力科技有限公司 | Sine circuit reactive power detection method |
| CN106247915A (en) * | 2016-07-07 | 2016-12-21 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuit followed based on peak value and method thereof |
| CN110068724A (en) * | 2018-01-24 | 2019-07-30 | 株式会社索思未来 | Peak value valley value detection circuit, A/D converter and integrated circuit |
-
2011
- 2011-07-08 CN CN201120239466U patent/CN202133712U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267254A (en) * | 2014-08-13 | 2015-01-07 | 如皋市图腾电力科技有限公司 | Sine circuit reactive power detection method |
| CN104267254B (en) * | 2014-08-13 | 2017-03-01 | 如皋市图腾电力科技有限公司 | A kind of sinusoidal current reactive power detection method |
| CN106247915A (en) * | 2016-07-07 | 2016-12-21 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuit followed based on peak value and method thereof |
| CN106247915B (en) * | 2016-07-07 | 2018-11-09 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuits followed based on peak value and its method |
| CN110068724A (en) * | 2018-01-24 | 2019-07-30 | 株式会社索思未来 | Peak value valley value detection circuit, A/D converter and integrated circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120201 Termination date: 20150708 |
|
| EXPY | Termination of patent right or utility model |