CN202093782U - Shift register, liquid crystal display grid driving device and liquid crystal display - Google Patents
Shift register, liquid crystal display grid driving device and liquid crystal display Download PDFInfo
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- CN202093782U CN202093782U CN2011202303744U CN201120230374U CN202093782U CN 202093782 U CN202093782 U CN 202093782U CN 2011202303744 U CN2011202303744 U CN 2011202303744U CN 201120230374 U CN201120230374 U CN 201120230374U CN 202093782 U CN202093782 U CN 202093782U
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- film transistor
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Abstract
The utility model provides a shift register, a liquid crystal display grid driving device and a liquid crystal display. The shift register comprises a first film transistor, a control circuit, a discharging circuit and a voltage control circuit, wherein a source electrode of the first film transistor is connected with a dc high level signal input end for inputting dc high level signals, a drain electrode of the first film transistor is connected with a grid signal output end, the control circuit comprises a third film transistor used for controlling the first film transistor and enabling that the first film transistor charges the grid signal output end via dc high level signals, a drain electrode of the third film transistor is connected with a grid of the first film transistor, the discharging circuit is used for discharging the grip signal output end and is connected with grids and drain electrodes of the first film transistor and the third film transistor, and the voltage control circuit is used for controlling conduction voltage of the third film transistor and is connected with the grid of the first film transistor. The shift register reduces power consumption of the liquid crystal display grid driving device and the liquid crystal display.
Description
Technical field
The utility model relates to the LCD Technology field, is specifically related to a kind of shift register, LCD device grid drive device and LCD.
Background technology
Gate driving array (GOA:Gate Drive on Array), i.e. shift register, its key concept is that the gate driving of LCD (LCD Panel) (Gate driver) is integrated on the glass substrate, forms the turntable driving of counter plate.Compare traditional production technology, it not only provides cost savings, and display (Panel) can accomplish the design for aesthetic of both sides symmetry, realizes the design of the narrow frame of display, and utilizes display production capacity and yield to promote also more favourable.
But there is certain problem in the design of existing GOA unit, for example: because the problem that the circuit lifetime that amorphous silicon (a-Si) long-term work threshold voltage shift (Vth shift) is brought shortens etc.In addition, because the mobility of a-Si is lower, in order to satisfy the requirement of some thin film transistor (TFT)s in the circuit (TFT:Thin FilmTransistor) than macroion (Ion), can only satisfy by the channel width that increases TFT, can bring size on the space to increase like this and the increase of power consumption.And, because it is the charging of signal output terminal (OUTPUT) signal that traditional approach GOA unit needs very large TFT, and this TFT directly links to each other with clock signal input terminal, owing to have stray capacitance among the TFT, TFT AC power dissipation in the therefore existing GOA unit is very big, causes the power consumption of existing GOA unit very big.
In the GOA of actual product design, how to use minimum circuit elements device to realize the shift LD function, can guarantee low-power consumption and long-term stable operation again simultaneously, be the key issue of GOA design.
The utility model content
Technical problem to be solved in the utility model provides a kind of shift register, LCD device grid drive device and LCD, thereby reduces the power consumption of shift register, LCD device grid drive device and LCD.
For solving the problems of the technologies described above, the utility model provides scheme as follows:
A kind of shift register comprises:
One the first film transistor, source electrode is connected with the direct current high level signal input end of input direct current high level signal, and drain electrode is connected with described signal output terminal;
Control circuit, comprise that one is used to control described the first film transistor, making described the first film transistor utilize described direct current high level signal is the 3rd thin film transistor (TFT) of described signal output terminal charging, and the drain electrode of described the 3rd thin film transistor (TFT) connects the transistorized grid of described the first film;
One is used for the discharge circuit to described signal output terminal discharge, is connected with drain electrode with the grid of described the first film transistor and the 3rd thin film transistor (TFT);
Be used to control the voltage control circuit of the forward voltage of described the 3rd thin film transistor (TFT), be connected with the transistorized grid of described the first film.
Above-mentioned shift register, wherein, described control circuit also comprises: second thin film transistor (TFT) and electric capacity are formed, wherein:
The source electrode of second thin film transistor (TFT) all is connected with the signal input end with grid, and drain electrode is connected with first end and the described discharge circuit of the grid of the 3rd thin film transistor (TFT), described electric capacity respectively;
The source electrode of the 3rd thin film transistor (TFT) is connected with first clock signal input terminal, and drain electrode is connected with second end and the described discharge circuit of described electric capacity;
Described voltage control circuit is the 8th thin film transistor (TFT), and the source electrode of the 8th thin film transistor (TFT) is connected with described direct current high level signal input end, and grid is connected with the drain electrode of second thin film transistor (TFT) with drain electrode.
Above-mentioned shift register, wherein, described discharge circuit is made up of the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT), wherein:
The source electrode of the 4th thin film transistor (TFT) is connected with described control circuit, the grid of the 4th thin film transistor (TFT) is connected with the grid of reset signal input end, the 6th thin film transistor (TFT) respectively, and the drain electrode of the 4th thin film transistor (TFT) is connected with direct current low level signal input end respectively, the drain electrode of the drain electrode of the drain electrode of the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) connects;
The source electrode of the 5th thin film transistor (TFT) is connected with described control circuit, the transistorized grid of the first film respectively, and the grid of the 5th thin film transistor (TFT) is connected with the grid of second clock signal input part, the 7th thin film transistor (TFT) respectively;
The source electrode of the 6th thin film transistor (TFT) is connected with the source electrode of the first film transistor drain, signal output terminal, the 7th thin film transistor (TFT) respectively.
For solving the problems of the technologies described above, the utility model also provides a kind of LCD device grid drive device, comprises as above-mentioned each shift register.
For solving the problems of the technologies described above, the utility model also provides a kind of LCD, it is characterized in that, comprises above-mentioned LCD device grid drive device.
From the above as can be seen, the shift register that the utility model embodiment provides, LCD device grid drive device and LCD, by rational deployment with a spot of thin film transistor (TFT) and an electric capacity, the thin film transistor (TFT) of being responsible for the charging of control grid signal output part directly is not connected with clock signal input terminal, but with direct current high level signal input end, control circuit, discharge circuit connects, thereby can avoid this thin film transistor (TFT) to produce AC power dissipation, having reduced the gate driving array is the power consumption of shift register, and then can reduce the power consumption of LCD device grid drive device and LCD.
And simultaneously, control the voltage of the 3rd thin film transistor (TFT) by thin film transistor (TFT), and make the 3rd thin film transistor (TFT) to keep conducting state with less voltage, prolonged the serviceable life of system.
Description of drawings
The shift register structure synoptic diagram one that Fig. 1 provides for the utility model embodiment;
The shift register structure synoptic diagram two that Fig. 2 provides for the utility model embodiment;
The shift register input signal sequential simulated effect figure that Fig. 3 provides for the utility model embodiment.
Embodiment
The utility model embodiment provides a kind of shift register that can be applicable in the LCD device grid drive device, and as shown in Figure 1, this shift LD implement body can comprise:
One the first film transistor, source electrode is connected with the direct current high level signal input end of input direct current high level signal, and drain electrode is connected with the signal output terminal;
One is used for the discharge circuit 12 to described signal output terminal discharge, is connected with the 3rd thin film transistor (TFT) with described the first film transistor;
Be used to control the voltage control circuit 13 of the forward voltage of described the 3rd thin film transistor (TFT), be connected with the transistorized grid of described the first film.
A concrete structure synoptic diagram of the shift register that the utility model embodiment provides can be as shown in Figure 2, and wherein, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and a capacitor C 1 are formed control circuit 11; The 4th thin film transistor (TFT) T4, the 5th thin film transistor (TFT) T5, the 6th thin film transistor (TFT) T6 and the 7th thin film transistor (TFT) T7 form discharge circuit 12.And the 8th thin film transistor (TFT) T8 forms this voltage control circuit 13.
The concrete annexation of the shift register that the utility model embodiment provides can be as follows:
The source electrode of T1 is connected with VDD, and the grid of T1 can be connected with the source electrode of the drain electrode of T3, the end of C1 (can be made as second end), T5 respectively, and the drain electrode of T1 can be connected with the source electrode of OUTPUT, T6 and T7 respectively;
The source electrode of T2 all can be connected with signal input end (INPUT) with grid, and the drain electrode of T2 can be connected with the source electrode of the grid of T3, the other end of C1 (can be made as first end), T4 respectively;
The source electrode of T3 can be connected with first clock signal input terminal (CLK), and the grid of T3 can be connected with the drain electrode of T2, the source electrode of T4, first end of C1 respectively, and the drain electrode of T3 can be connected with second end of C1, the grid of T1, the source electrode of T5 respectively;
The source electrode of T4 can be connected with the drain electrode of T2, the grid of T3 and first end of C1 respectively, the grid of T4 can be connected with the grid of reset signal input end (RESET), T6 respectively, and the drain electrode of T4 can be connected with the drain electrode of direct current low level signal input end (VSS), T5, the drain electrode of T6, the drain electrode of T7 respectively;
The source electrode of T5 can be connected with the drain electrode of T3, first end of C1, the grid of T1 respectively, the grid of T5 can be connected with the grid of second clock signal input part (CLKB), T7 respectively, and the drain electrode of T5 can be connected with the drain electrode of VSS, T4, the drain electrode of T6, the drain electrode of T7 respectively;
The source electrode of T6 can be connected with the drain electrode of T1, the source electrode of OUTPUT, T7 respectively, and the grid of T6 can be connected with grid, the RESET of T4 respectively, and the drain electrode of T6 can be connected with the drain electrode of VSS, T4, the drain electrode of T5, the drain electrode of T7 respectively;
The source electrode of T7 can be connected with the drain electrode of T1, the source electrode of OUTPUT, T6 respectively, and the grid of T7 can be connected with the grid of CLKB, T5 respectively, and the drain electrode of T7 can be connected with the drain electrode of VSS, T4, the drain electrode of T5, the drain electrode of T6 respectively.
The source electrode of T8 is connected with VDD, and grid and drain electrode are connected in the circuit that the grid of the drain electrode of T2 and T3 is connected simultaneously, and just the while is connected with the drain electrode of T2 and the grid of T3.
Need to prove that the source electrode of the thin film transistor (TFT) TFT that the utility model embodiment is related is interchangeable with drain electrode, and the two ends of electric capacity can be exchanged.
Based on above-mentioned concrete annexation, control circuit 11 in the shift register that the utility model embodiment provides, can be according to the sequential relationship of input signal (sequential relationship simulated effect figure can as shown in Figure 3), control T1 and discharge circuit 12 carry out the charge and discharge operation for OUTPUT.
Concrete principle of work can be as follows:
At first, when lastrow GOA unit is the signal of shift register output when being imported by INPUT, the CLK input low level, the CLKB input high level, at this moment, T2 is in conducting state, and the signal of input is the C1 charging, simultaneously, because T5 and T7 are in conducting state at this moment, and the drain electrode of T5 and T7 is connected with VSS, therefore, T1 is at this moment and keeps closed condition, OUTPUT is low level;
Then, when the signal end of input, the CLK input high level, the CLKB input low level, at this moment, T3 is in conducting state, supposing does not have T8, in this case, considers the capacitive coupling effect of CLK signal to T3, when follow-up operation, the grid voltage of T3 can be drawn high about 2 times of VDD, and the too high life-span that can shorten T3 of grid voltage, therefore, in specific embodiment of the utility model, add T8, during the T8 conducting, make the grid voltage of T3 become VDD+Vth (threshold voltage of T8), therefore can make that also the grid of T3 is a high voltage, but its grid voltage can remain on VDD+Vth, and can not be elevated to about 2 times of VDD, and having avoided is not having T8 to make the problem of the too high reduction in serviceable life that brings of grid voltage of time spent T3.
At last, when CLK input low level, CLKB once more during input high level once more, the reset signal of RESET input high level (being the output signal of next line GOA unit), at this moment, TFT4～7 are in conducting state, and then RESET is the OUTPUT discharge, simultaneously, CLKB is the C1 discharge.
Because it is the OUTPUT charging that existing GOA unit needs very large TFT, and TFT is that CLK directly links to each other with clock signal input terminal, owing to have stray capacitance among the TFT, the TFT AC power dissipation among the therefore existing GOA is very big, causes the power consumption of existing GOA unit very big.
And the description of the shift register that provides by above-mentioned the utility model embodiment as can be seen, among the utility model embodiment, being responsible for control grid signal output part is that the thin film transistor (TFT) that OUTPUT charges is T1, be not that CLK or CLKB are connected directly with clock signal input terminal, but with direct current high level signal input end be VDD, and control circuit 11 is connected with discharge circuit 12, thereby can avoid T1 to produce AC power dissipation, having reduced the gate driving array is the power consumption of shift register, and then can reduce the power consumption of LCD device grid drive device and LCD, the demonstration product that power consumption is had relatively high expectations will have highly beneficial.
And simultaneously, by adding T8, the grid voltage of control T3 remains on VDD+Vth, and can not continue to raise, and has avoided not having T8 to make the problem of the too high reduction in serviceable life that brings of grid voltage of time spent T3.
Because the shift register that the utility model embodiment provides can be applicable in the LCD device grid drive device, therefore, the utility model embodiment also provides a kind of LCD device grid drive device, the shift register that has comprised plurality of cascaded in this device, this shift register comprises a plurality of levels of mutual cascade, the signal output terminal of each grade is the signal input end of next stage, described each level can be by control circuit 11, discharge circuit 12 and one is responsible for the thin film transistor (TFT) T1 composition that control grid signal output part discharges and recharges, specifically can be shown in accompanying drawing 1 or 2.The number of set shift register can be corresponding with set grid line number in this device in this device.
The shift register and the LCD device grid drive device that provide based on the utility model embodiment, the utility model embodiment also can provide a LCD, one LCD device grid drive device is set in this display, and this LCD device grid drive device can be provided with the shift register shown in accompanying drawing 1 or 2.
From the above as can be seen, the shift register that the utility model embodiment provides, LCD device grid drive device and LCD, by rational deployment with a spot of thin film transistor (TFT) and an electric capacity, the thin film transistor (TFT) of being responsible for the charging of control grid signal output part directly is not connected with clock signal input terminal, but with direct current high level signal input end, control circuit, discharge circuit connects, thereby can avoid this thin film transistor (TFT) to produce AC power dissipation, having reduced the gate driving array is the power consumption of shift register, and then can reduce the power consumption of LCD device grid drive device and LCD.
The above only is an embodiment of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (5)
1. a shift register is characterized in that, comprising:
One the first film transistor, source electrode is connected with the direct current high level signal input end of input direct current high level signal, and drain electrode is connected with the signal output terminal;
Control circuit, comprise that one is used to control described the first film transistor, making described the first film transistor utilize described direct current high level signal is the 3rd thin film transistor (TFT) of described signal output terminal charging, and the drain electrode of described the 3rd thin film transistor (TFT) connects the transistorized grid of described the first film;
One is used for the discharge circuit to described signal output terminal discharge, is connected with drain electrode with the grid of described the first film transistor and the 3rd thin film transistor (TFT);
Be used to control the voltage control circuit of the forward voltage of described the 3rd thin film transistor (TFT), be connected with the transistorized grid of described the first film.
2. shift register according to claim 1 is characterized in that, described control circuit also comprises: second thin film transistor (TFT) and electric capacity are formed, wherein:
The source electrode of second thin film transistor (TFT) all is connected with the signal input end with grid, and drain electrode is connected with first end and the described discharge circuit of the grid of the 3rd thin film transistor (TFT), described electric capacity respectively;
The source electrode of the 3rd thin film transistor (TFT) is connected with first clock signal input terminal, and drain electrode is connected with second end and the described discharge circuit of described electric capacity;
Described voltage control circuit is the 8th thin film transistor (TFT), and the source electrode of the 8th thin film transistor (TFT) is connected with described direct current high level signal input end, and grid is connected with the drain electrode of second thin film transistor (TFT) with drain electrode.
3. shift register according to claim 2 is characterized in that, described discharge circuit is made up of the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT), wherein:
The source electrode of the 4th thin film transistor (TFT) is connected with described control circuit, the grid of the 4th thin film transistor (TFT) is connected with the grid of reset signal input end, the 6th thin film transistor (TFT) respectively, and the drain electrode of the 4th thin film transistor (TFT) is connected with direct current low level signal input end respectively, the drain electrode of the drain electrode of the drain electrode of the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) connects;
The source electrode of the 5th thin film transistor (TFT) is connected with described control circuit, the transistorized grid of the first film respectively, and the grid of the 5th thin film transistor (TFT) is connected with the grid of second clock signal input part, the 7th thin film transistor (TFT) respectively;
The source electrode of the 6th thin film transistor (TFT) is connected with the source electrode of the first film transistor drain, signal output terminal, the 7th thin film transistor (TFT) respectively.
4. a LCD device grid drive device is characterized in that, comprises as each described shift register of claim 1 to 3.
5. a LCD is characterized in that, comprises LCD device grid drive device as claimed in claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202303744U CN202093782U (en) | 2011-06-30 | 2011-06-30 | Shift register, liquid crystal display grid driving device and liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202303744U CN202093782U (en) | 2011-06-30 | 2011-06-30 | Shift register, liquid crystal display grid driving device and liquid crystal display |
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| Publication Number | Publication Date |
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| CN202093782U true CN202093782U (en) | 2011-12-28 |
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| CN2011202303744U Expired - Lifetime CN202093782U (en) | 2011-06-30 | 2011-06-30 | Shift register, liquid crystal display grid driving device and liquid crystal display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
| CN104008717A (en) * | 2014-05-19 | 2014-08-27 | 华南理工大学 | Grid drive circuit of flat-panel display and low-power-consumption output module thereof |
-
2011
- 2011-06-30 CN CN2011202303744U patent/CN202093782U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
| WO2014169536A1 (en) * | 2013-04-16 | 2014-10-23 | 北京京东方光电科技有限公司 | Shift register unit and driving method therefor, gate driving circuit, and display apparatus |
| CN103236273B (en) * | 2013-04-16 | 2016-06-22 | 北京京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit and display device |
| US9530370B2 (en) | 2013-04-16 | 2016-12-27 | Beijing Boe Optoelectronics Technology Co., Ltd. | Shift register unit and driving method thereof, gate driving circuit and display device |
| CN104008717A (en) * | 2014-05-19 | 2014-08-27 | 华南理工大学 | Grid drive circuit of flat-panel display and low-power-consumption output module thereof |
| CN104008717B (en) * | 2014-05-19 | 2016-05-04 | 华南理工大学 | The gate driver circuit of flat-panel monitor and low-power consumption output module thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111228 |