CN202050399U - Serial port tie line management instruction-check-type 8K-channel sensor 128-group home appliance wire holder - Google Patents
Serial port tie line management instruction-check-type 8K-channel sensor 128-group home appliance wire holder Download PDFInfo
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- CN202050399U CN202050399U CN2010206962888U CN201020696288U CN202050399U CN 202050399 U CN202050399 U CN 202050399U CN 2010206962888 U CN2010206962888 U CN 2010206962888U CN 201020696288 U CN201020696288 U CN 201020696288U CN 202050399 U CN202050399 U CN 202050399U
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Abstract
串行口联络线管理核对指令式8K路传感器128组家电接线座是一种计算机与家电的接口装置,通过串行口的TXD配合两根联络线管理128组电子电器,用一根输入联络线检测8K(K=1,2,3,......)路传感器;包括:RS232C接口、USB接口、
电平转换电路、8bit串入并出移位寄存器、256个8bit数据比较器电路、128个RS触发器电路、128组电子开关电路、8bit×K并入串出移位寄存器以及8K(K=1,2,3,......)对传感器接线端。其中,RTS作为上述两种移位寄存器的时钟信号,DTR分别作为8bit串入并出移位寄存器的串行输入信号以及8bit×K并入串出移位寄存器的数据移位/装载控制信号,TXD作为所述比较器电路的输出允许控制信号,该比较器电路的输出控制128个RS触发器电路及其电子开关电路;CTS接收8bit×K并入串出移位寄存器的串行输出信号。用于现有电器网络化管理。Serial port connection line management check instruction type 8K channel sensor 128 sets of home appliance terminal block is a computer and home appliance interface device, through the TXD of the serial port and two connection lines to manage 128 groups of electronic appliances, with one input connection line Detect 8K (K=1, 2, 3,...) sensors; including: RS232C interface, USB interface,
Level conversion circuit, 8bit serial input and output shift register, 256 8bit data comparator circuits, 128 RS flip-flop circuits, 128 sets of electronic switch circuits, 8bit×K parallel input and serial output shift register and 8K (K= 1, 2, 3, ...) to the sensor terminals. Among them, RTS is used as the clock signal of the above two shift registers, and DTR is used as the serial input signal of the 8bit serial input and output shift register and the data shift/load control signal of the 8bit×K parallel input and serial output shift register respectively. TXD is used as the output permission control signal of the comparator circuit, and the output of the comparator circuit controls 128 RS flip-flop circuits and their electronic switch circuits; CTS receives the serial output signal of the 8bit×K parallel input and serial output shift register. It is used for network management of existing electrical appliances.Description
Technical field
The utility model belongs to the application electric technology field, particularly relates to a kind of computer of household electrical appliance automation and interface arrangement of domestic electronic and electrical equipment realized.
Background technology
Submit to recently the utility model patent " the serial port junctor management management core is to 128 groups of home appliance wire holders of instruction type No. 8 sensors " of Patent Office of State Intellectual Property Office examination so that computer can detect the output state of 8 Sensor of Switch-Output Type, and by means of two of computer serial port output interconnections and send data wire TXD and send out the binary data instruction by 8 SI PO shift registers exactly, through comparing with the instruction code that presets, manage 128 groups of domestic electronics and electrical equipment.
Summary of the invention
The purpose of this utility model is to provide a kind of serial port interconnection management core to 128 groups of household electrical appliances junction blocks of instruction type 8K road transducer, it is main frame with the computer, rely on an input interconnection of serial port to detect 8K (K=1,2,3, ...) road digital quantity output type transducer, two output interconnections by serial port are sent out the binary data instruction, and send the output of data wire TXD control data instruction with it, this director data and the command code that presets are compared, manage 128 groups of domestic electronics and electrical equipment; Comprise: RS232C interface, USB interface, USB change the serial port circuit,
Level shifting circuit, 8bit SI PO shift register, 256 8bit data comparator circuit, 128 rest-set flip-flop circuit, 128 groups of electronic switching circuits, 8bit * K incorporate into and go here and there out shift register, 8K (K=1,2,3 ...) to sensor terminals, voltage-stabilized power supply circuit, anti-lightning strike and surge circuit and power line and plug thereof.
The technical scheme that its technical problem that solves the utility model adopts is:
USB interface is connected to the corresponding signal input part that USB turns to the serial port circuit, the corresponding port line parallel of the latter's signal output part and RS232C interface; The 5th pin GND of RS232C interface is connected to power cathode, and its 4th pin DTR, the 7th pin RTS, the 3rd pin TXD are connected respectively to
A RS232C level signal input of level shifting circuit; The TTL/CMOS level signal output of the corresponding RTS of this level shifting circuit is connected respectively to 8bit SI PO shift register and 8bit * K to be incorporated into and goes here and there out the clock signal input terminal of shift register; The TTL/CMOS level signal output of the corresponding DTR of this level shifting circuit is connected respectively to serial signal input of 8bit SI PO shift register and 8bit * K to be incorporated into and goes here and there out the parallel input data of the shift register control end that is shifted/loads; The comparative result A=B signal output that the TTL/CMOS level signal output of the corresponding TXD of this level shifting circuit is connected to 256 8bit data comparator circuit allows control end
Also connect a pull-up resistor to positive source; The 8th pin CTS of serial port is connected to
A RS232C level signal output of level shifting circuit, the TTL/CMOS level signal input of corresponding this level shifting circuit is connected to 8bit * K and incorporates into and go here and there out the serial signal output of shift register therewith; 8 signal output part Q of 8bit SI PO shift register
7Q
6Q
5Q
4Q
3Q
2Q
1Q
0One group of comparison signal input A with 256 8bit data comparator circuit
7A
6A
5A
4A
3A
2A
1A
0In regular turn in parallel, 256 comparative result A=B signal output parts of 256 8bit data comparator circuit connect respectively a pull down resistor to power cathode, also are connected in regular turn respectively 128 opposed 1 end S and reset terminal R of 128 rest-set flip-flop circuit; 128 output Q of 128 rest-set flip-flop circuit are connected respectively to the control signal input of one group of electronic switching circuit; The ac input end of voltage-stabilized power supply circuit is received civil power with anti-lightning strike in parallel with surge circuit by power line and plug thereof.
The 8bit SI PO shift register is made up of a 74HC164.
256 8bit data comparator circuit are made up of 256 8bit data comparators, and it is A that each 8bit data comparator has two groups of comparison signal inputs
7A
6A
5A
4A
3A
2A
1A
0And B
7B
6B
5B
4B
3B
2B
1B
0One group of comparison signal input A of each 8bit data comparator
7A
6A
5A
4A
3A
2A
1A
0Difference is in regular turn in parallel, consists of one group of comparison signal input A of 256 8bit data comparator circuit
7A
6A
5A
4A
3A
2A
1A
0Another group comparison signal input B of each 8bit data comparator
7B
6B
5B
4B
3B
2B
1B
0Be connected respectively to the common port of a single-pole double-throw switch (SPDT), so have 8 * 256 single-pole double-throw switch (SPDT)s, the in addition two ends of these single-pole double-throw switch (SPDT)s are connected respectively to positive source and power cathode; Each 8bit data comparator also has the signal output part of a comparative result A=B and a comparative result A=B signal output to allow control end
The former high level is effective, consists of altogether 256 comparative result A=B signal output parts of 256 8bit data comparator circuit, latter's Low level effective, and the comparative result A=B signal output that consists of 256 8bit data comparator circuit in parallel allows control end
8bit * K incorporates into and goes here and there out shift register and be made up of K piece 74HC165 cascade, their sheet choosing end is all received power cathode, its clock signal input terminal all links together, constitute the clock signal input terminal of described shift register, the 1st cascade carry signal input DS receives the positive pole of power supply, its serial signal output Q
HBe connected to the 2nd serial signal input B, the 2nd serial signal output Q
HBe connected to the 3rd cascade carry signal input DS, and the like, the serial signal output Q of K-1 piece
HBe connected to the cascade carry signal input DS of K piece, the serial signal output Q of K piece
HSerial signal output as described shift register; The 8K of described shift register parallel signal input connects a pull-up resistor respectively to positive source, also respectively with power cathode constitute 8K (K=1,2,3 ...) and to sensor terminals.
Voltage-stabilized power supply circuit is made up of power transformer, diode bridge rectifier circuit, capacitor filter and circuit of three-terminal voltage-stabilizing integrated 7806, and two outputs of 7806 have constituted the positive source and the power cathode of this device respectively.
Anti-lightning strike and surge circuit is made up of a fuse and a piezo-resistance polyphone.
Level shifting circuit is made up of in conjunction with four electrochemical capacitors two MAX232.
128 groups of electronic switching circuits comprise 128 groups of electronic switching circuits, and each structure of organizing electronic switching circuit is identical, comprises separately: No. 1 alternating current electronic switching circuit and 1 road direct current electronic switching circuit.
The alternating current electronic switching circuit comprises: 1 NPN triode, 1 PNP triode, 1 base resistance, 1 base biasing resistor, 1 collector resistance, 1 current limliting collector resistance, a light-emitting diode and a solid-state relay; Wherein, the base stage of one termination NPN triode of base resistance, the other end is as the signal input end of this group electronic switching circuit, base biasing resistor is connected in parallel on the emitter junction of PNP triode, the emitter of this PNP triode connects positive source, its base stage and collector resistance, the collector electrode series connection of light-emitting diode and NPN triode, the emitter of NPN triode is connected to power cathode, current limliting of the collector electrode of PNP triode series connection is connected to the positive pole in the signal input end of solid-state relay with collector resistance, the negative pole in the signal input end of solid-state relay is connected to power cathode; Two outputs of solid-state relay constitute the output of this alternating current electronic switching circuit.
The electronic DC switch circuit comprises: triode and base resistance, a diode and a direct current relay; Wherein, the base stage of one termination triode of base resistance, the other end is as the signal input end of this group electronic switching circuit, the emitter of triode is connected to power cathode, its collector electrode is connected respectively to an end of the coil of the positive pole of diode and direct current relay, and the other end of the negative pole of diode and the coil of direct current relay all is connected to positive source; Six terminals of two pairs of single-pole double-throw switch (SPDT)s of direct current relay have constituted the output of this electronic DC switch circuit.
The utility model has constituted the interface between computer and domestic electronic and the electrical equipment, its advantage is, both can cooperate to incorporate into and go here and there out shift register and detect 8K (K=1 by an input interconnection, 2,3 ...) output state of road digital quantity output type transducer, can cooperate by two output interconnections again to send the correct binary data instruction of data wires output, through data relatively, manage 128 groups of domestic electronics or electrical equipment.
Description of drawings
Below in conjunction with accompanying drawing, further specify the utility model.
Fig. 1 is the circuit of the sensor interface part of circuit theory diagrams of the present utility model, wherein, and K=2, S
16..., S
01Representative sensor.
Fig. 2 is the schematic diagram of one group of electronic switching circuit.
Fig. 3 is circuit (square frame) figure of the transfer instruction data division of circuit theory diagrams of the present utility model.
Fig. 4 is made of the circuit theory diagrams of a 8bit binary data comparator 4bit binary data comparator.
Among the figure, 001.-128. electronic switching circuit, 11.-12.
Level shifting circuit, 13.8bit SI PO shift register, 15.128 rest-set flip-flop circuit, 16., 17.8bit incorporates into and goes here and there out shift register, 31. the single-pole double throw direct current electromagnetic relay, 32. solid-state relay SSR, 5. voltage-stabilized power supply circuits, 51. anti-lightning strike and surge circuit, 6.USB interface, 7.USB changes serial port circuit, 8.RS232C interface, 9.256 individual 8bit data comparator circuit, 91.-93.4bit binary data comparator.
Embodiment
As shown in Figure 1,8bit incorporates into and goes here and there out shift register (16), (17) cascade and form 8bit * K and incorporate into and go here and there out shift register (K=2).When DTR is the parallel input data displacement/loading control end SHIFT/LOAD of 74HC165 (16), (17) when being low level, the data of 16 parallel inputs of 74HC165 (16), (17) are loaded.When RTS is the pulse of a positive transition of the every input of clock signal input terminal of 74HC165 (16), (17), the data of 16 parallel inputs that are loaded take place once to be shifted successively, for example: A → B → ... → G → H → Q
HTherefore, event attribute according to serial communication control MSComm32.OCX: MSComm32.CTSholding/.DSRholding/.DCDholding, from the 8th pin CTS (also can use CD, DSR instead) of RS232C interface just can interrupt response mode or the mode of inquiry analyze 8 road digital quantity output type transducer S
16..., S
01State.16 the pull-up resistor Rs relevant with the parallel input of 74HC165 (16), (17)
16..., R
01Make and do not insert transducer S
16..., S
01The time its input end in stable level state.
As shown in Figure 3,8bit SI PO shift register (13) is made up of a 74HC164, its key points for operation are: be before the rising edge arrival of RTS at clock pulse signal, need be ready to the one digit number of transmission according to the serial signal input B of Di to 74HC164 (13) by DTR; The rising edge of clock pulse signal arrives, and displacement action: Q0=Di will take place the parallel output terminal of 74HC164 (13), Q0 → Q1 → Q2 → ... → Q6 → Q7; Output earlier is no less than 808 parallel-by-bit dateouts of coming zero clearing 74HC164 (13) before sending out data command at every turn, also can not go zero clearing, only exports needed data.
As shown in Figure 4, a 8bit binary data comparator is formed with (93) in 3 tetrad data comparator integrated circuits (91), (92), therefore, uses 256 8bit data comparators can form 256 8bit data comparator circuit (9).As seen from Figure 4, one group of data input pin A of comparator (92) and (91)
3A
2A
1A
0, A
3A
2A
1A
0Consisted of successively one group of comparison signal input A of this 8bit data comparator
7A
6A
5A
4A
3A
2A
1A
0Another group data input pin B of comparator (92) and (91)
3B
2B
1B
0, B
3B
2B
1B
0Consisted of successively another group comparison signal input B of this comparator
7B
6B
5B
4B
3B
2B
1B
0, they come the prepositioned instruction code by eight single-pole double-throw switch (SPDT)s.Utilize one group of data input pin B of comparator (93)
3B
2B
1B
0Highest order B
3The comparative result A=B signal output that consists of this 8bit data comparator allows control end
If that is:
The output signal A=B end of comparator (93) is always low level.Therefore, the pull down resistor R000 among Fig. 3 ..., R255 is also nonessential.
After " sealing in 8 the binary command data that walk abreast out ", Output attribute according to control MSComm32.OCX, character string is at random write in the serial port output register, then " its front of character of every transmission is superimposed with a low level beginning flag position ", this will cause 256 8bit data comparator circuit (9) output comparative result, guarantee that the correct director data of in good time transmission gives the 128 couples of R and the S control end of 128 rest-set flip-flop circuit (15).
8bit SI PO shift register (13) and 8bit * K incorporate into and go here and there out shift register (16), (17) (K=2) shared RTS is as clock signal input terminal, and shared DTR is as separately serial signal input B and data shift/loading control end SHIFT/LOAD.Therefore, can influence the operating state of the latter (16), (17) when operating the former (13), at this moment, the event attribute of not going to be concerned about serial communication control MSComm32.OCX gets final product; Also can influence the operating state of the former (13) when the operation latter (16), (17), at this moment, not send any data from TXD, just can be so that the output of the comparative result A=B signal of 256 8bit data comparator circuit (9) allows control end
Be in the high level disarmed state, thereby 256 comparative result A=B signal output parts of 256 8bit data comparator circuit (9) all are in low level, do not influence the 128 couples of R and the S control end of 128 rest-set flip-flop circuit (15), that is do not influence the operating state of electronic switching circuit (001)-(128).
Claims (9)
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CN111314636A (en) * | 2020-01-20 | 2020-06-19 | 思特威(上海)电子科技有限公司 | CMOS image sensor with improved column data shift reading |
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CN111314636A (en) * | 2020-01-20 | 2020-06-19 | 思特威(上海)电子科技有限公司 | CMOS image sensor with improved column data shift reading |
CN111314636B (en) * | 2020-01-20 | 2022-02-08 | 思特威(上海)电子科技股份有限公司 | CMOS image sensor with improved column data shift reading |
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Granted publication date: 20111123 Termination date: 20111229 |