CN202034956U - Level displacement circuit - Google Patents
Level displacement circuit Download PDFInfo
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- CN202034956U CN202034956U CN2011200284293U CN201120028429U CN202034956U CN 202034956 U CN202034956 U CN 202034956U CN 2011200284293 U CN2011200284293 U CN 2011200284293U CN 201120028429 U CN201120028429 U CN 201120028429U CN 202034956 U CN202034956 U CN 202034956U
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Abstract
The utility model discloses a level displacement circuit. In allusion to the defects of the conventional level displacement circuit that the area of a smaller circuit layout and the effective level displacements of different duty ratio input voltages can not be realized at the same time, the utility model provides a level displacement circuit, comprising a double-pulse generating and shaping circuit, a high/low level displacement converting circuit, a high-voltage pulse filtering shaping circuit and an RS trigger. The level displacement circuit is characterized in that the high/low level displacement converting circuit comprises an LDMOS tube, a NMOS tube, a first resistor, a second resistor, a third resistor, a first diode and a second diode. Compared to the conventional level displacement circuit of using two LDMOS tubes, the level displacement circuit of the utility model just uses one LDMOS tube, so that the layout area is reduced, and the effective level displacements of different duty ratio input voltages are realized by the rising edge and the falling edge of a high/low level characterization input control signal of a single channel pulse.
Description
Technical field
The utility model belongs to the chip design art field, relates to high-voltage power mos gate drive integrated circult, is specifically related to a kind of level displacement circuit.
Background technology
MOS grid drive integrated circult is one of typical circuit of HVIC (high voltage integrated circuit), is widely used in aspects such as household electrical appliance and industrial equipment, Aeronautics and Astronautics, armament systems.Its concrete importance using is to be used for realizing high-low pressure level shift, up to the present, general MOS grid drive integrated circult mostly adopts the identical LDMOS of two-way to realize level displacement circuit, i.e. the level displacement circuit of dipulse trigger-type.The mode of two-way level shift makes the complicated and chip area increase of circuit structure.Studies show that level displacement circuit occupies more than 80% of whole system power consumption.
A kind of relatively more classical high voltage level shift circuit as shown in Figure 1, comprise that two burst pulses produce circuit A and B, two pulse bandwidth filtering circuit A and B and signal recovery circuitry, because the high voltage bearing characteristic of LDMOS, this circuit carries out level shift by high-voltage LDMOS pipe M1 and M2 and load resistance R1 thereof and R2, can remedy the not high voltage bearing shortcoming of common level displacement circuit, and have advantage low in energy consumption, especially can effectively realize level shift at different duty ratio input voltages.But because this circuit characterizes the rising edge and the trailing edge of input control signal by using two burst pulses, use two-way LDMOS level displacement circuit respectively in level conversion, the high tension apparatus utilance is low, has increased the area of circuit layout.
Be the bigger problem of area that overcomes circuit layout, at document " Wu Zhenyu; Fang Jian; Qiao Ming; Li Zhaoji; high voltage level shift circuit and application thereof that single channel LDMOS realizes; microelectronics, Vol 37 (2), 2007,250-254 "; another kind of high voltage level shift circuit has been proposed; comprise pulse-generating circuit; pulse shaper; filter circuit; signal recovery circuitry, this level displacement circuit has used a LDMOS pipe and load resistance thereof to carry out level shift, this circuit has been realized single channel LDMOS level displacement circuit, and the high tension apparatus utilance improves, and the circuit layout area has reduced, but can bring the another one problem is rising edge and the trailing edge that the single channel burst pulse can't characterize input control signal, can't make different duty ratio input voltages can effectively realize level shift.
The utility model content
The purpose of this utility model is in order to solve the defective that existing level displacement circuit exists, to have proposed a kind of level displacement circuit.
To achieve these goals, the technical solution of the utility model, a kind of level displacement circuit, comprise that dipulse produces and shaping circuit, high-low level displacement conversion circuit, high-voltage pulse filtering shaping circuit and rest-set flip-flop, input voltage is connected to dipulse and produces and the shaping circuit input, it is characterized in that, high-low level displacement conversion circuit comprises the LDMOS pipe, the NMOS pipe, first resistance, second resistance, the 3rd resistance, first diode and second diode, input voltage is connected to the grid of NMOS pipe, the drain electrode of NMOS pipe links to each other with the source electrode of LDMOS pipe, the source electrode of NMOS pipe links to each other with first resistance, the other end of first resistance is connected to utterly, second resistance links to each other with the drain electrode of LDMOS pipe, the other end of second resistance is connected to utterly, the drain electrode of the 3rd resistance one termination LDMOS pipe, the other end links to each other with the high voltage source of outside, the positive pole of first diode links to each other with the drain electrode of LDMOS pipe, the negative pole of first diode links to each other with the positive pole of second diode, the negative pole of second diode links to each other with the high voltage source of outside, dipulse produces and links to each other with the grid of LDMOS pipe with the output of shaping circuit, the drain electrode of LDMOS pipe links to each other with the input of high-voltage pulse filtering shaping circuit, and two outputs of high-voltage pulse filtering shaping circuit link to each other with the S end with the R end of rest-set flip-flop respectively, and wherein the rising edge pulse output end links to each other with the R end of rest-set flip-flop, the trailing edge pulse output end links to each other with the S end of rest-set flip-flop, and the Q end of rest-set flip-flop is the level displacement circuit output voltage.
Above-mentioned high-voltage pulse filtering shaping circuit comprises: first comparator, second comparator and NOR gate, wherein, the negative input end of first comparator is connected as the input of high-voltage pulse filtering shaping circuit with the positive input terminal of second comparator, the positive input terminal of first comparator links to each other with first reference voltage of outside, the negative input end of second comparator links to each other with second reference voltage of outside, the power end of first comparator and second comparator links to each other with the high voltage source of outside, the ground end of first comparator and second comparator links to each other with the floating ground of outside, the output of second comparator is the trailing edge pulse output end of high-voltage pulse filtering shaping circuit, first comparator links to each other with two inputs of the output difference AND of second comparator, and the output of NOR gate is the rising edge pulse output end of high-voltage pulse filtering shaping circuit.
The beneficial effects of the utility model: compare existing high voltage level shift circuit and use two LDMOS pipes, level displacement circuit of the present utility model has only used a LDMOS pipe, other devices are the mesolow commonplace components, thereby reduced chip area, simplify circuit structure design, reduced the difficulty that technology realizes; Compare the single channel LDMOS circuit in the document, level displacement circuit of the present utility model can characterize the rising edge and the trailing edge of input control signal by the high-low level of single channel pulse, realizes the significant level displacement of different duty ratio input voltages.
Description of drawings
Fig. 1 is existing a kind of level displacement circuit structural representation.
Fig. 2 is a level displacement circuit structural representation of the present utility model.
Fig. 3 is the high-low level displacement conversion electrical block diagram of the utility model embodiment.
Fig. 4 is the high-voltage pulse filtering shaping circuit structural representation of the utility model embodiment.
Fig. 5 is the simulation result schematic diagram of the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the utility model is further elaborated.
As shown in Figure 2, a kind of level displacement circuit comprises that dipulse produces and shaping circuit 1, high-low level displacement conversion circuit 2, high-voltage pulse filtering shaping circuit 3 and rest-set flip-flop 4, and input voltage VIN is connected to dipulse and produces and shaping circuit 4 inputs.The dipulse here produces with shaping circuit 1 and belongs to prior art, no longer is described in detail at this.
For the ease of writing conveniently, make following regulation below: dipulse produces and the output signal of shaping circuit is designated as: Vo1; The signal of high-low level displacement conversion unit output is designated as: Vo2; The signal of the rising edge pulse output end output of high-voltage pulse filtering shaping circuit is designated as: Vo3; The signal of the trailing edge pulse output end output of high-voltage pulse filtering shaping circuit is designated as: Vo4; Input voltage is designated as: Vin; Outside floating ground is designated as: VSD; The floating empty power supply of high pressure is designated as: VCD; The level displacement circuit output voltage is designated as: Vout.
As shown in Figure 3, high-low level displacement conversion circuit 2 comprises LDMOS pipe M21, NMOS manages M22, first resistance R 23, second resistance R 24, the 3rd resistance R 25, the first diode D26 and the second diode D27, input voltage vin is connected to the grid of M22, the drain electrode of M22 links to each other with the source electrode of LDMOS pipe M21, the source electrode of M22 links to each other with first resistance R 23, the other end of first resistance R 23 is connected to common ground GND, second resistance R 24 links to each other with the drain electrode of LDMOS pipe M21, the other end of second resistance R 24 is connected to common ground GND, the drain electrode of the 3rd resistance R 25 1 termination LDMOS pipe M21, the other end links to each other with the high voltage source VCD of outside, the positive pole of the first diode D26 links to each other with the drain electrode of LDMOS pipe, the negative pole of the first diode D26 links to each other with the positive pole of the second diode D27, the negative pole of the second diode D27 links to each other with the high voltage source VCD of outside, dipulse produces with the output of shaping circuit 1 and links to each other with the grid of LDMOS pipe M21, the drain electrode of LDMOS pipe M21 links to each other with the input of high-voltage pulse filtering shaping circuit 3, the rising edge pulse output end of high-voltage pulse filtering shaping circuit 3 links to each other with the R of rest-set flip-flop end, the trailing edge pulse output end of high-voltage pulse filtering shaping circuit 3 links to each other with the S of rest-set flip-flop end, and the Q end of rest-set flip-flop is the output of level displacement circuit.
As shown in Figure 4, high-voltage pulse filtering shaping circuit 3 comprises: the first comparator A, the second comparator B, NOR gate M31, wherein the negative input end of the first comparator A is connected as the input of high-voltage pulse filtering shaping circuit 3 with the positive input terminal of the second comparator B, the positive input terminal of the first comparator A links to each other with the first reference voltage V REF1 of outside, the negative input end of the second comparator B links to each other with the second reference voltage V REF2 of outside, the power end of the first comparator A and the second comparator B links to each other with the high voltage source VCD of outside, the ground end of the first comparator A and the second comparator B links to each other with the floating ground VSD of outside, the output of the second comparator B is the trailing edge pulse output end of high-voltage pulse filtering shaping circuit 3, the first comparator A links to each other with two inputs of the output difference AND M31 of the second comparator B, and the output of NOR gate M31 is the rising edge pulse output end of high-voltage pulse filtering shaping circuit 3.
With the present embodiment is the operation principle of example explanation the utility model integrated circuit:
In the present embodiment, the ground VSD of the high-pressure section of high-voltage pulse filtering shaping circuit 3 and rest-set flip-flop 4 is the floating vacant lot of high pressure, the high level of the output voltage of level displacement circuit is VCD, and low level is VSD, and the function of level displacement circuit is that the output with low-pressure section is sent to high-pressure section.
Among Fig. 3, dipulse produces and the output signal Vo1 of shaping circuit 1 is controlling opening and shutting off of LDMOS pipe M21, the signal Vo2 of the output of high-low level displacement conversion element circuit (drain electrode of LDMOS) output can change along with the inverse change of Vo1, when LDMOS pipe M21 turn-offs, Vo2=VCD, when biasing NMOS pipe M21 opened, Vo2 was by resistance R 23 and R24 decision.
When circuit input signal Vin input dipulse produces with shaping unit, press in also being connected on the grid of NMOS pipe M22, when Vin is high level, NMOS pipe M22 conducting, resistance R 23 source electrode that is switched to LDMOS pipe M21 in parallel with R24, at this moment, the of short duration unlatching of pulse control LDMOS tube grid that rising edge produced, the drain voltage of LDMOS pipe can generate Vo2, and the low level current potential of Vo2 is designated as: VL; When input signal Vin was low level, M22 closed, and R24 is switched to the source electrode of LDMOS pipe separately, the of short duration unlatching of pulse control LDMOS tube grid that trailing edge produced, and the drain voltage of LDMOS can produce Vo2, and the low level current potential of Vo2 is designated as: VH.Because the LDMOS pipe is easy to generate bigger displacement current in shutoff and opening process, on resistance R 25, R23 and R24, have bigger voltage fluctuation, so between floating empty power supply VCD of high pressure and Vo2, increase by two reverse withstand voltage be the Zener diode D3 of 6.5～7V, D4 constitutes peripheral boostrap circuit, maximum pressure drop on the R25 is limited in 13～14V, avoids the gate oxide breakdown of subordinate's phase inverter.
Among Fig. 4, the input of high-voltage pulse filter shape unit 3 can intersect continuously imports rising edge pulse signal S2 and trailing edge pulse signal S3, because rising edge pulse signal S2 is different with the drop-down level of pulse of trailing edge pulse signal S3, in high-voltage pulse filter shape unit 3, have two comparator circuits that reference voltage is different, wherein the Wai Bu first reference voltage V REF1 connects the anode of comparator A, the second outside reference voltage V REF2 connects the anode of comparator B, the voltage swing that input requires VREF1 is between VH and VCD, and the voltage swing of VREF2 is between VL and VH.
When rising edge pulse signal S2 arrives comparator, because the drop-down level VL of pulse of signal S2 is less than reference voltage V REF1, VREF2, comparator A output logic 0, comparator B output logic 1; When Vo2=VCD, because VCD is greater than reference voltage V REF1, VREF2, comparator A output logic 1, comparator B output logic 0; Because the drop-down level VH of pulse of signal S3 is lower than reference voltage V REF1, is higher than reference voltage V REF2, so comparator A output logic 0, comparator B output logic 0.Comparator is in the height of judging output level, good filter function is also arranged, can eliminate the false triggering that d (VCD)/dt produces, the output of comparator B is the signal Vo4 of the trailing edge pulse output end output of high-voltage pulse filtering shaping circuit, comparator A links to each other with two inputs of the output difference AND M31 of comparator B, and the output of NOR gate M31 is the signal Vo3 of the rising edge pulse output end output of high-voltage pulse filtering shaping circuit.
The Vo3 signal can be input to the R end of rest-set flip-flop 4, can trigger the rising edge that generates the displacement level; The Vo4 signal can be connected to the S end of rest-set flip-flop 4, correspondingly also can generate the trailing edge of displacement level.High voltage level after the displacement that the Q of rest-set flip-flop 4 end can be exported.
Fig. 5 has provided the simulation result figure of embodiment, observes the high pressure Vo3 along the pulse that rises, high pressure trailing edge pulse Vo4, the relation between the high voltage level output Vout waveform.The pulse-triggered of Vo3 signal can the displacement high-voltage square-wave rising edge of output; Equally, the Vo4 signal can make high voltage level step-down among the Vout by trigger, realizes the displacement control of trailing edge.
The signal Vo2 of high-low level displacement conversion circuit 2 outputs is under the situation of the of short duration opening and closing of LDMOS tube grid, produce two level VH and VL respectively, when different the saying of duty ratio of input signal can be caused false triggering, in the present embodiment by the height of comparator at judgement output level VH and VL, eliminate the false triggering of generation, under different duty ratio input voltages, realize effective level shift thereby reach.
The simulated conditions of present embodiment is: the floating empty power supply VCD of high pressure is 80V; The floating vacant lot VSD of high pressure is 70V; Low-tension supply VCC is 5.8V; Circuit input voltage vin scope: 0V～5.8V.Simulation result is as shown in the figure: the scope of level displacement circuit output voltage V out: 70V～80V, and frequency is identical with input, and promptly to hang down logical relation relatively identical for the relative high potential logical relation of output and input, reached the purpose of high-low level displacement.
As can be seen from the above analysis, high voltage level shift circuit of the present utility model has solved the effective level shift of input voltage under different duty when reducing the circuit layout area.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present utility model, should to be understood that the protection range of utility model is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection range of claim of the present utility model.
Claims (2)
1. level displacement circuit, comprise that dipulse produces and shaping circuit, high-low level displacement conversion circuit, high-voltage pulse filtering shaping circuit and rest-set flip-flop, input voltage is connected to dipulse and produces and the shaping circuit input, it is characterized in that, high-low level displacement conversion circuit comprises the LDMOS pipe, the NMOS pipe, first resistance, second resistance, the 3rd resistance, first diode and second diode, input voltage is connected to the grid of NMOS pipe, the drain electrode of NMOS pipe links to each other with the source electrode of LDMOS pipe, the source electrode of NMOS pipe links to each other with first resistance, the other end of first resistance is connected to utterly, second resistance links to each other with the drain electrode of LDMOS pipe, the other end of second resistance is connected to utterly, the drain electrode of the 3rd resistance one termination LDMOS pipe, the other end links to each other with the high voltage source of outside, the positive pole of first diode links to each other with the drain electrode of LDMOS pipe, the negative pole of first diode links to each other with the positive pole of second diode, the negative pole of second diode links to each other with the high voltage source of outside, dipulse produces and links to each other with the grid of LDMOS pipe with the output of shaping circuit, the drain electrode of LDMOS pipe links to each other with the input of high-voltage pulse filtering shaping circuit, the rising edge pulse of the output of high-voltage pulse filtering shaping circuit links to each other with the R of rest-set flip-flop end, the trailing edge pulse of the output of high-voltage pulse filtering shaping circuit links to each other with the S of rest-set flip-flop end, and the Q end of rest-set flip-flop is the level displacement circuit output voltage.
2. level displacement circuit according to claim 1, it is characterized in that, described high-voltage pulse filtering shaping circuit comprises first comparator, second comparator and NOR gate, the negative input end of first comparator is connected as the input of high-voltage pulse filtering shaping circuit with the positive input terminal of second comparator, the positive input terminal of first comparator links to each other with first reference voltage of outside, the negative input end of second comparator links to each other with second reference voltage of outside, the power end of first comparator and second comparator links to each other with the high voltage source of outside, the ground end of first comparator and second comparator links to each other with the floating ground of outside, the output of second comparator is the trailing edge pulse output end of high-voltage pulse filtering shaping circuit, first comparator links to each other with two inputs of the output difference AND of second comparator, and the output of NOR gate is the rising edge pulse output end of high-voltage pulse filtering shaping circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200284293U CN202034956U (en) | 2011-01-27 | 2011-01-27 | Level displacement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200284293U CN202034956U (en) | 2011-01-27 | 2011-01-27 | Level displacement circuit |
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| CN202034956U true CN202034956U (en) | 2011-11-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011200284293U Expired - Fee Related CN202034956U (en) | 2011-01-27 | 2011-01-27 | Level displacement circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185592A (en) * | 2011-01-27 | 2011-09-14 | 电子科技大学 | Level shift circuit |
| CN107612528A (en) * | 2017-09-29 | 2018-01-19 | 科域科技有限公司 | A kind of pulse bandwidth filtering circuit arrangement |
| CN110632397A (en) * | 2019-08-30 | 2019-12-31 | 深圳市华奥通通信技术有限公司 | Signal analysis method and computer readable storage medium |
-
2011
- 2011-01-27 CN CN2011200284293U patent/CN202034956U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185592A (en) * | 2011-01-27 | 2011-09-14 | 电子科技大学 | Level shift circuit |
| CN102185592B (en) * | 2011-01-27 | 2013-07-17 | 电子科技大学 | Level shift circuit |
| CN107612528A (en) * | 2017-09-29 | 2018-01-19 | 科域科技有限公司 | A kind of pulse bandwidth filtering circuit arrangement |
| CN110632397A (en) * | 2019-08-30 | 2019-12-31 | 深圳市华奥通通信技术有限公司 | Signal analysis method and computer readable storage medium |
| CN110632397B (en) * | 2019-08-30 | 2021-11-19 | 深圳市华奥通通信技术有限公司 | Signal analysis method and computer readable storage medium |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111109 Termination date: 20140127 |