CN201869206U

CN201869206U - Streaming media server

Info

Publication number: CN201869206U
Application number: CN2010201571500U
Authority: CN
Inventors: 丁宇; 姚志平
Original assignee: SUZHOU DATONG TAIKE INFORMATION TECHNOLOGY Co Ltd
Current assignee: SUZHOU DATONG TAIKE INFORMATION TECHNOLOGY Co Ltd
Priority date: 2010-04-13
Filing date: 2010-04-13
Publication date: 2011-06-15
Anticipated expiration: 2020-04-13

Abstract

The utility model relates to a streaming media server with a network repeat function, which comprises a host CPU and a bridge chip of the host machine, a multi-chip flash memory system, a device supporting the repeat function, a media repeat memory and a gigabit Ethernet network interface; and the streaming media server is characterized in that the device comprises a packet processing engine, a solid-state storage engine, a solid-state storage network interface module, a network interface module and a PCIe interface module, wherein the solid-state storage network interface module defines a data conversion structure from the media storage format to the network playing format, thereby realizing the network repeat function. By adopting the device in the utility model, the streaming media playing performance of the streaming media server is 10 times or more than 10 times than that of the traditional streaming media server, the running power consumption of the server can be greatly reduced, the operation efficiency of the operator and the number of clients are greatly improved and the operation cost of the operator is reduced.

Description

Streaming media server

Technical field

The utility model relates to a kind of streaming media server, particularly relates to a kind of streaming media server with network repeat function.

Background technology

Along with the continuous propelling that China's broadband internet is built, the network integration of unification of three nets constantly advances, and increasing user brings into use IP-based wideband service, and the wideband epoch of converged communication arrive.This makes many IP-based multimedia services become possibility, wideband cinema for example, Network TV Station, video conference, long-distance education, tele-medicine, Network Video Surveillance, online live broadcast system etc.

As the core technology of wideband service, stream media technology obtains great development in recent years, and Streaming Media refers to transmit in network with stream mode the media format of audio frequency, video and multimedia file.In the streaming media service system, the common especially PC of client master, or the set-top box of support IP function; At the operation local side, streaming media server is arranged, media content managing system, customer account management and Verification System, and the media transcoding system that adapts to various video platforms.

Wherein streaming media server is exactly the core system of streaming media service, is operator provides crucial platform from Video service to the user.Its major function be to media content gather, buffer memory, format conversion, scheduling and transmission are play; Serve the especially requirement of telecom operators in order to adapt to operation simultaneously, the new function at value-added telecom services becomes necessary, for example encrypts distribution, content auditing and issue, authentication broadcast, operation charging or the like based on incorporate broadband streaming media business function.

Current main streaming media server adopts traditional X86 architecture, along with the network flow-medium flow sharply increases, traditional architectures runs into following performance bottleneck: storage system is still based on mechanical hard disk, though the standard machinery hard disk is advanced by leaps and bounds on memory capacity, but because its structure weakness, read or write speed is subject to the physics rotary speed of video disc and the read or write speed of magnetic head, there is the problem that reads difficulty at random simultaneously, these cause its lasting read or write speed still progressive very slow, have greatly lagged behind capacity increase speed; Network interface and storage system are independent subsystem in the X86 architecture, and both directly do not put passage, make the broadcast of a large amount of Streaming Medias still pass through system's main memory, cause the very big consume system resources of streaming media playing, influence host performance.

Summary of the invention

The purpose of this utility model provide a kind of can server the operation power consumption, adopt the parallel high-speed flash-memory storage system, the high speed that can realize stream medium data continues to read, realize that files in stream media play-overs, greatly improves the streaming media server with network repeat function of the speed that stream media network plays from the high speed that storage reads network interface.

For solving the problems of the technologies described above, the utility model is taked following technical scheme: a kind of streaming media server with network repeat function comprises host CPU and bridge sheet thereof, many flash-memory storage systems, supports device, the medium of repeat function directly to put internal memory and gigabit ethernet network interface; It is characterized in that:

Described device comprises packet processing engine, solid-state storage engine, solid-state storage Network Interface Module, Network Interface Module and PCIe interface module;

Described packet processing engine is accepted the data sending request from described Network Interface Module, solid-state storage Network Interface Module, and according to the link parameter of host definition, the distribution queue space is with temporary various packets in the outside DDR internal memory of described device; Described packet processing engine is also from described DDR internal memory read data packet and send it to described Network Interface Module;

Described solid-state storage engine is connected with the solid-state storage Network Interface Module with the PCIe interface module, and links to each other with many flash-memory storage systems;

Described solid-state storage Network Interface Module is used to realize the direct interface between described solid-state storage engine and the packet processing engine, and it has defined the translation data structure from the media store form to the netcast form, thereby realizes network repeat function;

Described Network Interface Module is the adaptation module between the multiple network interface of described packet processing engine and described device outside;

Described PCIe interface module is used to provide the data-interface between main frame and the described device.

Because described device of the present utility model, promptly chip or FPGA have adopted high speed flash memory solid state storage technologies to realize that the high speed of stream medium data continues to read, thereby solve the continuous access speed issue and the randow addressing problem of traditional mechanical hard disk; In addition, described solid-state storage Network Interface Module has defined the translation data structure from the media store form to the netcast form, thereby can realize that files in stream media play-overs from the high speed that storage reads network interface, effectively solve the bottleneck problem of traditional X-ray 86 structure large-scale datas, can realize the HD video broadcast of the clear or hundreds of roads of thousands of road signs to netcast; At last, described device, promptly chip or FPGA also provide abundant network interface, can realize that the unified of heterogeneous networks interface inserts by different adaptation module.In sum, described device in the utility model, be chip or FPGA, make its streaming media playing performance reach 10 times of the conventional flow media server and even more, significantly reduce the operation power consumption of server simultaneously, greatly improve efficiency of operation and client's quantity of operator, reduce operating cost of operator.

Description of drawings

Fig. 1 is based on the structure chart of the streaming media server of network repeat function.

Fig. 2 is the structural representation that adopts the streaming media server of microTCA or ATCA standard architecture.

Fig. 3 is the structure chart of many flash memories network repeat AMC module.

Fig. 4 is the multi-flash memory parallel storage device with network repeat function, i.e. chip or FPGA, the hardware configuration schematic diagram.

Embodiment

Below in conjunction with accompanying drawing the technical solution of the utility model is elaborated.

In order to solve big volume flow media play problem, be to improve the long-term reading speed problem of storage system outside its key, and improve the netcast speed of Streaming Media simultaneously.

The streaming media server of repeat function Network Based comprises host CPU, storage system, network interface, and optional coding/decoding module.Flash-memory storage system with network repeat function provides the high-speed channel of storage system to network interface, greatly improves the cost performance of streaming media server.

Fig. 1 shows the structure chart of the streaming media server of repeat function Network Based.As shown in Figure 1, described streaming media server comprises host CPU and bridge sheet thereof, and the multi-bank flash-memory storage system, supports the device of repeat function, i.e. chip or FPGA, and medium are directly put internal memory DIMM, and corresponding gigabit ethernet network interface.This streaming media server can 1U or the 2U form server realize, at the middle-size and small-size streaming media market about 2G.Wherein, host CPU and attached bridge sheet thereof can adopt intel XEON series CPU and bridge sheet thereof, also can adopt Freescale P4080 series CPU, can support multichannel PCIe interface; Support the device of repeat function, promptly chip or FPGA are the cores of this streaming media server, and it will elaborate in following part.Described device, i.e. chip or FPGA, the core design of design can be cut out supporting the different bandwidth of directly putting, and utilizes the FPGA of different costs to realize.Its storage system can support 8 to 128 nand flash memories parallel, read bandwidth and reach as high as 20Gbps, network interface can be supported two common 10/100/1000BASE-T gigabit ethernet interfaces simultaneously, described device, be chip or FPGA, support that gmii interface and outside gigabit Ethernet PHY (for example BCM5482) are interconnected; The PCIe interface provides main frame to the multi-bank flash-memory storage system with directly put the interface of mixed-media network modules mixed-media, can support single channel or multichannel PCIe, and the nearly above bandwidth of 10Gbps is provided.

Preferably, in order to support more jumbo streaming media service, can adopt based on microTCA (Micro Telecommunications Computing Architecture) or ATCA (Advanced Telecommunications Computing Architecture) standard architecture.Fig. 2 shows the structural representation of the streaming media server that adopts microTCA or ATCA standard architecture.Described streaming media server has the AMC module of a plurality of AMC of meeting standards to be formed, and mainly contains CPU master control AMC module, many flash memories network repeat AMC (Advanced Mezzanine Cards) module and optional encoding and decoding piece AMC module and MCH Switching Module.

Wherein, the MCH Switching Module is the Switching Module in the microTCA architecture, mainly bears communication task between each AMC module; CPU master control AMC module mainly is responsible for stream media protocol, and network protocol analysis is handled, and it communicates by gigabit Ethernet network and each AMC module of MCH; Adopting fast simultaneously, the PCIe interface communicates control and streaming media playing processing to many flash memories network repeat AMC module; The PCIe interface is the main control channel of CPU host module to many flash memories network repeat AMC module; CPU master control AMC module can link to each other with the encoding and decoding accelerating module that mainly contains the DSP formation by sRIO (serial RapidIO) simultaneously.

Especially, many flash memories network repeat AMC module is the core of described media server, and its core technology is described device, i.e. chip or FPGA, and its structure chart is by shown in Figure 3.

In detail to previously described device, promptly chip or FPGA are described in detail below.

Fig. 4 shows many flash memories high-speed parallel storage device that the network enabled in the utility model is directly put, i.e. chip or FPGA, the hardware configuration schematic diagram.Described device, be chip or FPGA, can adopt programmable gate array or special-purpose gate array to realize, as shown in Figure 4, its main nucleus module comprises packet processing engine 1 (pkt_engine), solid-state storage engine 2 (SSD_engine), solid-state storage Network Interface Module 3 (SSD_IWF), Network Interface Module 4 (pkt_if) and PCIe interface module 5 (PCIe_if).

Below to constituting described device, i.e. chip or FPGA, each module be described in detail.

Described packet processing engine 1 is used for being responsible for the processing of procotol, for example queue management, and traffic engineering is handled, network protocol analysis and distribution etc.The core of described packet processing engine 1 is that open network exchange is handled, it provides general packet interface, thereby can insert different data modules by different adaptation module, for example can realize linking to each other, also can link to each other with host network interface with the external perimysium reference gigabit Ethernet by the interface between the described Network Interface Module 4; In addition, can also realize the play-overing of network interface, thereby greatly improve the playing efficiency of Streaming Media by described solid-state storage Network Interface Module.

Preferably, described packet processing engine 1 mainly comprises formation writing module 11 (queue_writer) and formation read through model 12 (queue_reader) composition.

Described formation writing module 11 is accepted from the next data sending request of inner various data source modules such as described Network Interface Module 4, solid-state storage Network Interface Module 3, according to the link parameter of host definition, externally in the DDR internal memory 6 the distribution queue space with temporary various packets.When carrying out distribution queue, carry out traffic management, protocal analysis and packet classification, this function realizes by the CAM (Content Addressable Memory) of inner three cascades that mainly CAM113 (forwarding CAM) is confirmed in i.e. ethernet source address CAM111 (source address CAM), identification of data packets CAM112 (exception CAM) and link.Described ethernet source address CAM111 realizes the source address of Ethernet is classified, and only sets in advance the described identification of data packets CAM112 that the source address of admitting just is sent to next step and handles; Described identification of data packets CAM112 discerns many packets that need the upper strata main frame to carry out further protocol processes, and sends it to host CPU and handle, STP protocol package for example, OAM, Routing Protocol etc.; Described link confirms that CAM113 confirms link and is provided with to pass on label, so that next step is sent to corresponding module, the packet by the link affirmation will initiatively not abandoned.The design of described three CAM adopts flexibly that binary tree structure designs, and its capacity can carry out concrete cutting according to the capacity of system.After the described CAM affirmation of packet by three-stage cascade, traffic policing module 114 (policer) will be carried out the traffic engineering classification to packet according to the degree of crowding of formation, and the bag of giving that promptly is commonly called as is beaten color.The congestion manager 115 of traffic engineering (congestion manager) is according to the color of packet, with and queue condition of living in carry out congested processing, carry out Weighted random earlier detection (WRED, Weighted Random Earlier Detection) queuing operation.The client of described formation writing module 11 by internal unity writes interface 116 (client write interface) and described device, i.e. chip or FPGA, and other inner modules link to each other; Preferably, it is 32, the bus of 125Mhz that described client writes interface, can support the bandwidth of writing of 4Gbps, simultaneously can support to link to each other with a plurality of device client interfaces, for example described a plurality of device client interface can be the reorganization client module (SSD reassembly client) of writing client's module (MAC write client), solid-state storage module with following too network interface, the described client that described these client's modules all support unified client to write interface and packet processing engine 1 writes interface and links to each other, but then supports different functions at the other end.

Described formation read through model is carried out the work from the internal memory read data packet, and sends it to corresponding external network interface.Described formation read through model mainly relies on destination CAM121 (destination CAM) to obtain the destination information that packet will send, for example destination-mac address, connect parameter etc., and configuration in advance is added in the packet of corresponding link according to system with described information; Important transmission information such as the traffic engineering parameter of simultaneously described formation read through model dependence transmitting control scheduling module 122 (poller/shaper/scheduler) decision output stream, bag transmitting time, obtaining destination address, transmitting time is stabbed mark, after the relevant informations such as port numbers, described formation read through model is according to predetermined requirement read data packet from internal memory, send it to external module, described external module for example can be a network interface etc.The client of described formation read through model by internal unity reads interface 123 (client readinterface) and described device, i.e. chip or FPGA, and other inner modules link to each other; Preferably, it is 32, the bus of 125Mhz that described client reads interface, can support that the tape reading of 4Gbps is wide, simultaneously can support to link to each other with a plurality of device client interfaces, for example the assembling client module (SSDassembly client) of reading client's module (MAC read client), solid-state storage module of big network interface, the segmentation client module (SSD segmentclient) of solid-state storage module, these client's modules are all supported unified client to read interface to read interface with the described client of packet processing engine 1 and link to each other.

Described solid-state storage engine 2 is responsible for and many flash-memory storage systems 7 (F1ash Array) interface, and it supports many flash array storages, and design can support the parallel storage of 128 flash memories, the stable bandwidth that continues of data read can reach 16Gbps at most.Described solid-state storage engine is also supported to be connected with PCIe interface module 5 simultaneously, and the solid-state storage Network Interface Module 3 that is connected with Packet engine interface module 1 is connected, thereby the realization storage networking is play-overed.The core of described solid-state storage engine modules is flash memory control module 21 (SSD_Control), this module can be supported maximum 128 nand flash memories simultaneously, adopt parallel combination method, make readwrite bandwidth improve greatly, support flash memory anti-aging algorithm simultaneously, make prolong greatly the useful life of flash memory.Described solid-state storage engine 2 comprises that also the flash data bag sends primary module 22 (SSD pkttx master) and the flash data bag receives primary module 23 (SSD pkt rx master), and it is designed to send cache module 34 with following solid-state storage respectively and is connected with solid-state storage reception cache module 38.

Described solid-state storage Network Interface Module 3 is used to realize the direct interface between described solid-state storage engine 2 and the packet processing engine 1.Described solid-state storage Network Interface Module 3 has defined the translation data structure from the media store form to the netcast form, and adopt the multiple strand chain list structure to realize that Streaming Media is linked to the mapping of storage file, make when stream media network is play, can realize repeat function automatically, thereby improve the stream media network broadcast performance greatly.Preferably, initial designs is supported the link of 1024 Streaming Medias, and about altogether 2Gbps continues the netcast bandwidth.

Described solid-state storage Network Interface Module 3 comprises 6 little modules altogether by the read-write two large divisions.Described read through model is read client's module 31 (ssd read client), solid-state storage bag buffer module 32 (ssd packet buffer) and three submodules of solid-state storage assembling client module 33 (ssd assembly client) by solid-state storage and is constituted; Solid-state storage read that client's module 31 is responsible for and the described clients of described packet processing engine 1 to read interface interconnected, to write described solid-state storage bag buffer module 32 from the packet that described packet processing engine 1 reads, described solid-state storage bag buffer module 32 is carried out the data pack buffer effect, also carry out simultaneously the conversion of data rate clock, to realize the adaptive of different data rate; Solid-state storage assembling client module 33 is utilized connection identifier (FID, Flow ID) to solid-state storage connection identifier (SSDID, Solidstate disk ID) information in the look-up table is ressembled the packet that reads from described solid-state storage bag buffer module 32, form new solid-state data memory format, send cache module 34 (ssd tx buffer) by writing solid-state storage again, wait for that solid-state storage engine 2 goes to handle.

The described writing module of solid-state storage Network Interface Module 3 is write client's module 35 (ssd write client), solid-state storage bag buffer module 36 (ssd packet buffer) and solid-state storage section client module 37 (ssd segment client) by solid-state storage and is constituted; Solid-state storage write that client's module 35 is responsible for and the described clients of described packet processing engine 1 to write interface interconnected, to write described packet processing engine 1 from the packet that solid-state storage bag buffer module 36 reads, solid-state storage bag buffer module 36 is carried out the data pack buffer effect, also carry out simultaneously the conversion of data rate clock, to realize the adaptive of different data rate; Solid-state storage section client module 37 is utilized solid-state storage connection identifier (SSDID, Solid state disk ID) to connection identifier (FID, Flow ID) information in the look-up table is cut apart again to receiving the packet that reads the cache module 38 (ssd rxbuffer) from solid-state storage, form new Ethernet bearing form, by writing solid-state storage bag buffer module 36, the wait solid-state storage is write client's module 35 and is gone to handle again.

Described Network Interface Module 4 is described packet processing engine 1 and described device, be chip or FPGA, adaptation module between the outside multiple network interface, keeping under the constant situation of described packet processing engine 1, by different adaptation module, can insert gigabit Ethernet, main frame detection Control Network interface, HDLC interface, RS232 serial ports, ATM cell and multiple network adaptation unit.

Described Network Interface Module 4 is wherein most important adaptation module, and by the read-write two large divisions, 6 little modules constitute altogether.Described Ethernet read through model is by reading client's module 41 (macread client), bag cache module 42 (mac packet buffer), gigabit Ethernet data link layer transport module 43 (gig ethernet pcs/mac tx) formation; Read that client's module 41 is responsible for and the clients of described packet processing engine 1 to read interface interconnected, to write bag cache module 42 from the packet that described packet processing engine 1 reads, described bag cache module 42 is carried out the data pack buffer effect, also carry out simultaneously the conversion of data rate clock, to realize the adaptive of different data rate; Described gigabit Ethernet data link layer transport module 43 is used to realize the data link layer protocol function of gigabit Ethernet, can with described device, be chip or FPGA, outside gigabit Ethernet physical layer PHY (ethernet physical layer equipment) is interconnected with GMII (GigabitMedia Independent Interface) or RMII (Reduced pincount GigabitMedia Independent Interface), perhaps interconnected with the SFP of SGMII (Serial GigabitMedia Independent Interface) interface and optical Ethernet.Described gigabit Ethernet data link layer transport module 43 also passes to described device by GMII (Serial Gigabit Media Independent Interface) or SGMII (Serial Gigabit Media Independent Interface) interface from the packet that bag cache module 42 reads, be chip or FPGA, on the outside Ethernet.

Described Ethernet writing module wraps cache module 45 (mac packet buffer) by writing client's module 44 (mac write client), and the gigabit Ethernet data link layer is accepted module 46 (gig Ethernet pcs/mac rx) and constituted.It is interconnected that the described client's of writing module 44 clients responsible and described packet processing engine 1 write interface, to write described packet processing engine 1 from the packet that bag cache module 45 reads, described bag cache module 45 is carried out the data pack buffer effect, also carry out simultaneously the conversion of data rate clock, to realize the adaptive of different data rate; The gigabit Ethernet data link layer is accepted the data link layer protocol function that module 46 realizes gigabit Ethernet, can with described device, be chip or FPGA, outside gigabit Ethernet physical layer PHY (ethernet physical layer equipment) is interconnected, perhaps interconnected with the SFP of SGMII interface and optical Ethernet with GMII (Gigabit Media IndependentInterface) or RMII (Reduced pincount Gigabit Media IndependentInterface).The gigabit Ethernet data link layer is accepted module 46 receives the external network input by GMII (Gigabit MediaIndependent Interface) or SGMII (Serial Gigabit MediaIndependent Interface) interface packet, it is write bag cache module 45, and send packets and be ready to signal to writing client's module 44, wait client's module 44 to be written to read the bag data from described bag cache module 45.

Cpu data packet interface module 8 provides the packet interface with CPU, mainly supplies host test and protocol processes, and its structure and described Network Interface Module 4 are similar, but provides the register interface for the CPU visit.

Described PCIe (PCI express) interface module 5 is supported multichannel PCIe interface, makes main frame can directly link to each other with the Streaming Media repeater system.The PCIe interface module mainly is made up of PCIe system control module 51 (PCIe System Control), sdram interface module 52 (PCIesdram i/f), PCIe holotype writing module 53 (PCIe write master) and PCIe holotype read through model 54 (PCIe read master).Physical layer and the link layer interface 9 (PCIe PHY and Link layer) of PCIe system control module one side and PCIe, provide the system works interface to dedicated system inside on the other hand, described built-in system working interface mainly is made up of described SDRAM (Synchronous dynamic Random Access Memory) interface module, PCIe holotype writing module and PCIe holotype read through model.Wherein, described sdram interface module is the sdram memory interface, is used for providing direct sdram memory access path to host CPU; PCIe holotype writing module is the write direct interface of host CPU to the described multi-chip flash memory module in the utility model, and it mainly handles the data write operation that sends from PCIe; PCIe holotype read through model is the direct fetch interface of host CPU to multi-chip flash memory module described in the utility model, the main data reading operation that sends from PCIe of handling.

Described chip described in the utility model, promptly described multi-chip flash memory module adopt Xilinxvirtex-5FPGA to realize, estimate design capacity about 1,000,000 about.On the basis of core special chip, under the consideration of integrated cost and performance, can consider to utilize same nucleus module to realize high-end and two series of low and middle-end, low and middle-end series is supported the streaming media playing bandwidth of about 2Gbps, can support SD video or 200 road above HD videos more than 400 tunnel simultaneously approximately, be primarily aimed at the community of intermediate size, private network users such as enterprise; The streaming media playing bandwidth of the about 20G of high-end system support can be supported SD video or 2000 road above HD videos more than 4000 tunnel approximately simultaneously, is primarily aimed at extensive operation business.

Claims

1. the streaming media server with network repeat function comprises host CPU and bridge sheet thereof, many flash-memory storage systems, supports device, the medium of described repeat function directly to put internal memory and gigabit ethernet network interface; It is characterized in that:

2. streaming media server as claimed in claim 1 is characterized in that: described streaming media server adopts based on microTCA or ATCA standard architecture.

3. streaming media server as claimed in claim 1 or 2 is characterized in that: described packet processing engine is carried out traffic management, protocal analysis and packet classification in the distribution queue space.

4. streaming media server as claimed in claim 1 or 2 is characterized in that: described distribution queue space realizes that by the CAM of three cascades CAM is confirmed in i.e. ethernet source address CAM, identification of data packets CAM and link.

5. streaming media server as claimed in claim 1 or 2 is characterized in that: described translation data structure adopts the multiple strand chain list structure to realize that Streaming Media is linked to the mapping of storage file.

6. streaming media server as claimed in claim 1 or 2 is characterized in that: described PCIe interface module is supported multichannel PCIe interface.

7. streaming media server as claimed in claim 1 or 2 is characterized in that: described device also comprises cpu data packet interface module, and it is used to provide the packet interface with CPU; Described cpu data packet interface module mainly supplies host test and protocol processes.