CN201859336U

CN201859336U - Programmable controller with multipath high-speed pulse output function

Info

Publication number: CN201859336U
Application number: CN2010205877619U
Authority: CN
Inventors: 张伟; 应成; 琚长江; 侯金华; 陆晔
Original assignee: Shanghai Electrical Apparatus Research Institute Group Co Ltd
Current assignee: Shanghai Electrical Apparatus Research Institute Group Co Ltd
Priority date: 2010-11-02
Filing date: 2010-11-02
Publication date: 2011-06-08
Anticipated expiration: 2020-11-02

Abstract

The utility model discloses a programmable controller with multipath high-speed pulse output function, which comprises a main chip and a PLC (programmable logic controller) output terminal, wherein the main chip is connected with a high-speed pulse output chip through a parallel interface; each path of output of the high-speed pulse output chip is input to a diode current-limiting resistor R1 through optical couplers in sequence; an optical coupler U1, a phase inverter U2 and a field-effect tube Q1 are connected with the PLC output terminal. The programmable controller with the multipath high-speed pulse output function provided by the utility model has multipath independent high-speed pulse output and improves the frequency and the stability of the high-speed pulse output.

Description

Programmable Logic Controller with multipath high-speed pulse output function

Technical field

The utility model relates to a kind of Programmable Logic Controller, relates in particular to a kind of Programmable Logic Controller with multipath high-speed pulse output function.

Background technology

Programmable Logic Controller (PLC) is owing to complete function, functional reliability and cost performance height, and is easy to use, and can be applicable in the various abominable engineering-environments, so be widely used in the industrial automation control system.The motion control type PLC that possesses multipath high-speed pulse output then is a demand and most widely used a kind of, though current a lot of small PLC has the function of high-speed pulse output, but has only a two-way mostly, and travelling speed is not high yet, can not satisfy the project situation of the limited needs again of a lot of budgets multichannel motion control, necessitate so develop a kind of high performance mini PLC that possesses the multipath high-speed pulse output function.Be that the reliable high-speed pulse output of current realization all need adopt high speed photo coupling to isolate the mode that adds the output of high speed transistor on hardware circuit, thereby the cost of small PLC can be risen to some extent.

In addition, the high-speed pulse output function of at present a lot of small PLCs is integrated in the host CPU, perhaps adopt special-purpose motion chip, can take the more resource of host CPU like this and influence scan period of whole PLC, thereby its pulse output frequency is very limited, all has a lot of problems aspect track running precision and the multichannel output coordinating.So in this small PLC circuit, adopted microprocessor ARM to add the circuit design of programmable logic controller (PLC) FPGA, realize data operations processing and real-time control management such as motion planning, servocontrol filtering by ARM, fpga logic Programmable Logic Controller and other related devices are formed servocontrol and position feedback hardware interface, make aspect such as multipath high-speed pulse output running precision be greatly improved.Be the complexity that this scheme has also increased circuit, improved cost.

China Patent No. is that ZL200920077605.5 discloses a kind of high-speed pulse output, dependent instruction PWM and PTO have been introduced, but these functions all realize by software in host CPU, be in operation and take the resource of master chip always, and be subjected to the restriction of timer internal number and software, make and can not realize nearly 6 the road or more independent high-speed pulse output, operation stability also relative mistake is a little.

Summary of the invention

Technical problem to be solved in the utility model provides a kind of Programmable Logic Controller with multipath high-speed pulse output function, has independently high-speed pulse output of multichannel, improves the frequency and the stability of high-speed pulse output.

The utility model is to solve the problems of the technologies described above the technical scheme that adopts to provide a kind of Programmable Logic Controller with multipath high-speed pulse output function, comprise master chip and PLC lead-out terminal, wherein, described master chip links to each other with the high-speed pulse pio chip by parallel interface, optocoupler input diode current-limiting resistance R1 is passed through in each road output of described high-speed pulse pio chip successively, optocoupler U1, phase inverter U2, field effect transistor Q1 links to each other with the PLC lead-out terminal; The 3 end ground connection of described optocoupler U1, output inversion signal after optocoupler U1 isolates connects phase inverter U2 again after capacitor C 1 decoupling, connect triode TR1 before the field effect transistor Q1, be connected with resistance R 3 before the triode TR1 and resistance R 4 plays the dividing potential drop effect, thus the switch of control triode.

The above-mentioned Programmable Logic Controller with multipath high-speed pulse output function, wherein, described high-speed pulse pio chip is programmable logic device (PLD) FPGA, has 6 tunnel output signals.

The above-mentioned Programmable Logic Controller with multipath high-speed pulse output function, wherein, described field effect transistor Q1 is the P-channel enhancement type field effect transistor.

The utility model contrast prior art has following beneficial effect: the Programmable Logic Controller with multipath high-speed pulse output function that the utility model provides, the high-speed pulse number goes out part to be adopted and the host CPU separate design, only take the interrupt resources of host CPU, do not influence the scan period of whole PLC, improved output frequency and precision, the high-speed pulse output frequency reaches as high as 100KHz; Multipath high-speed pulse output can accomplish that each road is independent fully unaffected, can be used as common output port when not needing as high speed output.

Description of drawings

Fig. 1 is the Programmable Logic Controller structural representation that the utlity model has the multipath high-speed pulse output function;

Fig. 2 is the utility model high-speed pulse output circuit schematic diagram;

Fig. 3 searches for each situation synoptic diagram for the utility model DOG.

Among Fig. 1:

1 master chip, 2 high-speed pulse pio chips, 3 PLC lead-out terminals

Embodiment

The utility model will be further described below in conjunction with drawings and Examples.

Fig. 1 is the Programmable Logic Controller structural representation that the utlity model has the multipath high-speed pulse output function.

See also Fig. 1, the Programmable Logic Controller with multipath high-speed pulse output function that the utility model provides comprises master chip 1 and PLC lead-out terminal 3, wherein, described master chip 1 links to each other with high-speed pulse pio chip 2 by parallel interface, each road output of described high-speed pulse pio chip 2 is through optocoupler input diode current-limiting resistance R1, optocoupler U1, phase inverter U2, field effect transistor Q1 links to each other with the PLC lead-out terminal;

The 3 end ground connection of described optocoupler U1, output inversion signal after optocoupler U1 isolates connects phase inverter U2 again after capacitor C 1 decoupling, connect triode TR1 before the field effect transistor Q1, be connected with resistance R 3 before the triode TR1 and resistance R 4 plays the dividing potential drop effect, thus the switch of control triode.

Described master chip 1 links to each other with high-speed pulse pio chip 2 by parallel interface, and parallel interface comprises data line DATA, address wire ADDR, control line CS, RD, WR, DIR, INT.Described high-speed pulse pio chip is programmable logic device (PLD) FPGA, has 6 tunnel output signal DRV0～DRV5.

Fig. 2 is the utility model high-speed pulse output circuit schematic diagram.

See also Fig. 1, optocoupler U1 adopts high speed photo coupling TLP114A; Phase inverter U2 adopts NL17SZ04; P-channel enhancement type field effect transistor Q1 model is IRFU9024N.Resistance R 1 is an optocoupler input diode current-limiting resistance, the 3 end ground connection of U1, and what export after light-coupled isolation is inversion signal, so connecting the U2 phase inverter behind capacitor decoupling.During the circuit operate as normal, the high-speed pulse signal of master chip output enters the high-speed pulse output circuit by A point, and when A level point when being high, the B point is low, exports high level through phase inverter C point.In order to trigger field effect transistor work, increased triode TR1, R3 and R4 play the effect of dividing potential drop, thereby realize the on-off action of triode, be the C point when high, the triode conducting, 2,3 ends are equal to connection, D point conducting field effect transistor after R5 and R6 dividing potential drop then, E point are equal to be connected with the COM0+ end exports high level.Because the design feature of circuit makes that circuit can the very high pulse signal of transmission frequency.In a word, the A high-speed pulse waveform of ordering can be reflected to the E point faithfully.

Fig. 3 searches for each situation synoptic diagram for the utility model DOG.

See also Fig. 3, for by the output of hard-wired high precision 16 road high-speed pulse, mechanical origin recurrence (DSZR-band DOG search, ZRN-no DOG search), single speed location relevant operating instructions such as (DRVI-relative address position, DRVA-specific address positions) have mainly been designed according to the current application demand.

DOG searches for introduction: design has just changes spacing, reverse when spacing, the original point return of DOG function of search has been used in execution, this moment is because of the starting position difference of original point return, original point return action also have nothing in common with each other (will return direction among Fig. 3 and be made as the minimizing direction, ruuning situation is opposite when being set to increase direction)

Concrete DOG search situation is as follows:

1) starting position before by DOG in: after bringing into operation, earlier accelerate to top speed from substrate velocity, after block reaches the DOG signal transducer (it then is top speed with current that the top speed that does not accelerate to setting is just run into) creep speed reduces speed now, (near point signal) continues to creep after block goes out the DOG signal transducer, up to receiving that first zero signal of motor stops, this point is initial point

2) starting position is in DOG

3) starting position is near point signal OFF (behind DOG)

When 4) limit switch of original point return direction (just changeing spacing or reversing spacing) is for ON

Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little modification and perfect, therefore protection domain of the present utility model is worked as with being as the criterion that claims were defined.

Claims

1. Programmable Logic Controller with multipath high-speed pulse output function, comprise master chip (1) and PLC lead-out terminal (3), it is characterized in that, described master chip (1) links to each other with high-speed pulse pio chip (2) by parallel interface, optocoupler input diode current-limiting resistance R1 is passed through in each road output of described high-speed pulse pio chip (2) successively, optocoupler U1, phase inverter U2, field effect transistor Q1 links to each other with the PLC lead-out terminal;

2. the Programmable Logic Controller with multipath high-speed pulse output function as claimed in claim 1 is characterized in that, described high-speed pulse pio chip (2) is programmable logic device (PLD) FPGA, has 6 tunnel output signals.

3. the Programmable Logic Controller with multipath high-speed pulse output function as claimed in claim 1 is characterized in that, described field effect transistor Q1 is the P-channel enhancement type field effect transistor.