CN201853706U

CN201853706U - Radioresistance EEPROM (electrically erasable programmable read-only memory) storage array structure

Info

Publication number: CN201853706U
Application number: CN2010205459853U
Authority: CN
Inventors: 王晓玲; 封晴; 田海燕; 赵桂林; 李珂; 肖培磊
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2010-09-29
Filing date: 2010-09-29
Publication date: 2011-06-01
Anticipated expiration: 2020-09-29

Abstract

The utility model discloses a radioresistance EEPROM (electrically erasable programmable read-only memory) storage array structure which is characterized in that an EEPROM storage unit is enclosed in the middle by utilizing polycrystalline silicon, an isolation structure of an HVNMOS tube is formed by the polycrystalline silicon and the active region of each storage unit adjacent to the polycrystalline silicon so as to separate each storage unit in the storage array from four storage units above and below the storage unit as well as on the left and right of the storage unit, and the separating tube grid end of the HVMOS for separating is connected with voltage of minus 1 volt to minus 3 volt. Under the condition of guaranteeing the performance of the components, a separation structure is used between units so as to prevent leakage of electricity between units; and the impact of the total dose effect (TID) generated by radiation on field leakage between adjacent storage units in the EEPROM storage array is solved, and radioresistance performance of the storage unit array of the EEPROM component is improved.

Description

The radioresistant EEPROM memory array structure

Technical field

The utility model relates to a kind of method for designing of radioresistant EEPROM storage array.Belong to technical field of integrated circuits.

Background technology

EEPROM is used for the aeronautics and space field in a large number as non-volatile memory device.But because the complexity of space applied environment, storage array usually can be subjected to the influence of radiation and critical data is lost or component failure.How satisfying the needs that use in the space, improve the radiation resistance of EEPROM, is the focus of studying for many years.

Do not increase extra isolation structure between the memory cell that forms by the NMOS pipe in the prior art, isolate by the field oxygen in the technical process between unit and the unit.As shown in Figure 1,2 is active area, and 3 is gate oxide, and 4 is grid, 1 be about oxygen district, field between two NMOS pipes.In conventional environment, there is not conducting channel in the oxygen, there is not leakage current.In radiation environment, it is right that oxygen on the scene district 1 can produce ionization electron-hole; Because the effect of capturing of trap is at Si/SiO ₂The SiO of system ₂One side is piled up positive charge, forms interfacial state, might form the electric leakage raceway groove of transoid under the oxygen.Field oxygen electric leakage raceway groove can extend to contiguous transistorized source/drain region 2, and this will produce leakage current Id between adjacent NMOS pipe.So standard EEPROM memory cell array structure does not possess the value of using in radiation environment.

Summary of the invention

The utility model purpose is to address the above problem, and on the existing processes basis, has studied the influence of radiation to the EEPROM storage array, has proposed a kind of new radioresistant EEPROM memory array structure, makes the EEPROM storage array have capability of resistance to radiation.

The technical scheme that provides according to the utility model, the radioresistant EEPROM memory array structure, it is middle to utilize polysilicon that the EEPROM memory cell is enclosed in, the active area of described polysilicon and adjacent each memory cell forms the isolation structure of HVNMOS pipe, make each memory cell in the storage array and its up and down four memory cell separate; The HVNMOS isolated tube grid termination-1V that is used to isolate is to the voltage of-3V.The bit line of storage array adopts the vertical cabling of two aluminium, and word line adopts the horizontal cabling of three aluminium.The HVNMOS isolated tube grid of each byte are connected on the aluminium by contact hole in the storage array, form the grid wiring.

The utility model has the advantages that: guarantee between unit and unit, to use isolation structure, in case the electric leakage between the stop element under the condition of device performance.This invention has solved the total dose effect (TID) that produced by radiation to the influence of place electric leakage between the consecutive storage unit in the EEPROM storage array, improved the capability of resistance to radiation of EEPROM device stores cell array, the storage array resistant to total dose ability that adopts the above radioresistance memory cell of 300KRad (Si) to form can reach more than the 300KRad (Si).

Description of drawings

Fig. 1 is the schematic diagram that leaks electricity between the unit in the EEPROM storage array in the prior art

Fig. 2 is the utility model isolation structure floor map

Fig. 3 is the utility model separation principle profile

Fig. 4 is the utility model memory array structure floor map

Embodiment

Be elaborated below in conjunction with the technical scheme of drawings and Examples to invention:

Electric leakage principle according to field oxygen is isolated has adopted structure as shown in Figure 2, adds the polycrystalline ring in each memory cell periphery, and the N type active area of this polycrystalline ring and adjacent cells forms the HVNMOS isolated tube.

Structure shown in Figure 2 promptly forms the isolation structure of a HVNMOS pipe between unit and unit.The course of work of this structure and operation principle profile as shown in Figure 3,2 is two adjacent memory unit N type active areas separately, 3 is gate oxide, 4 for polysilicon gate (being the grid of HVNMOS isolated tube).Compared to Figure 1, do not have an oxygen zone between unit and the unit, the active area between unit and the unit has formed the active area of the HVNMOS isolated tube that is used to isolate.The grid termination-1 of this HVNMOS isolated tube～-3V voltage (present embodiment adopts-2V), make and below grid, pile up a lot of positive charges that pipe is in off state.When producing the electron leak electric current owing to the interfacial state existence, can be compound by the positive charge institute that pile up the grid below, can between memory cell and memory cell, not produce leakage current.

Fig. 4 is the array schematic diagram that adopts HVNMOS pipe isolation structure.In this array structure, bit line BL1～4 are by two aluminium, 5 vertical cablings, and the word line of memory cell selects grid SG1～4 and control gate CG1～4 by three aluminium, 6 horizontal cablings; Each EEPROM memory cell all by the HVNMOS isolated tube with in the middle of it is enclosed in, itself and four memory cell are up and down separated by the HVNMOS pipe fully.The HVNMOS isolated tube grid 4 of each byte link to each other by contact hole 7 and the current potential aluminium for-2V, the wiring of formation grid, even the NMOS threshold voltage is offset to some extent in radiation environment, this isolated tube can not opened yet, thereby can not produce leakage current between adjacent cells.

Claims

1. radioresistant EEPROM memory array structure, it is characterized in that: it is middle to utilize polysilicon that the EEPROM memory cell is enclosed in, the active area of described polysilicon and adjacent each memory cell forms the isolation structure of HVNMOS pipe, make each memory cell in the storage array and its up and down four memory cell separate; The HVNMOS isolated tube grid termination-1V that is used to isolate is to the voltage of-3V.

2. radioresistant EEPROM memory array structure according to claim 1 is characterized in that the bit line of storage array adopts the vertical cabling of two aluminium, and word line adopts the horizontal cabling of three aluminium.

3. radioresistant EEPROM memory array structure according to claim 1 is characterized in that the HVNMOS isolated tube grid of each byte in the storage array are connected on the aluminium by contact hole, forms the grid wiring.