CN201821335U - Phase locking system with zero steady-state phase locking error - Google Patents

Phase locking system with zero steady-state phase locking error Download PDF

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CN201821335U
CN201821335U CN2010205741375U CN201020574137U CN201821335U CN 201821335 U CN201821335 U CN 201821335U CN 2010205741375 U CN2010205741375 U CN 2010205741375U CN 201020574137 U CN201020574137 U CN 201020574137U CN 201821335 U CN201821335 U CN 201821335U
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phase
signal
frequency
locked
filter
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史田元
胡蛇庆
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JIANGSU JINFENG ELECTRONICS CO Ltd
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Abstract

The utility model provides a phase locking system with zero steady-state phase locking error, which determines the natural law of center frequency distribution of individual sub-band filters by use of a sampling frequency (fs) and a sampling point number (N) in a fast Fourier transform (FFT), and adjusts the sampling frequency to change the bandwidth and the position of center frequency of the sub-band filters. When the sampling frequency (fs) is an integral multiple of a locked signal frequency (fx) and the sampling point number is N, the locked signal must fall in the position of center frequency of the No. N/m sub-band filter. When the sampling frequency (fs) is defined by the locked signal frequency (fx), the center of the No. N/m sub-band filter is just the position of the locked signal frequency. The filter is a dedicated matching filter for input signals, and the frequency and the phase position of the output signal of the filter are just the frequency and the phase position of the locked signal, so that the steady-state error is eliminated.

Description

The phase-locked error of a kind of stable state is zero phase-locked system
Technical field
The utility model is the Phase Lock Technique of extensive use in the electronic information field, it relates to a kind of new phase-locked theory, it is to have adopted signal after the frequency locking output signal frequency multiplication to be the sample frequency of CAD, to use the system of specific output subfilter in the fast Fourier transform (specific output point output signal is exactly a lockin signal) then, claim that the selectivity fast fourier transform is CFFT (Choose Fast Fourier Transform), the phase-locked error of specifically a kind of stable state is zero phase-locked system.
Background technology
The history in existing 80 years of Phase Lock Technique has become the subject of an extensive use at present, from analog to digital, from the transistor to the large scale integrated circuit, develop very soon, mainly is to study implementation method.Their basic circuit such as Fig. 1 form: phase discriminator (PD), loop filter (LPF) and voltage controlled oscillator (VCO).Phase discriminator is a phase comparator, is that input signal carries out producing error voltage than mutually with voltage-controlled output signal; Loop filter is a low-pass filtering, high fdrequency component and noise in its filtering error voltage, the stability of increase loop; Voltage controlled oscillator (VCO) is to change frequency and phase place under the effect of error voltage, reaches the purpose of following the tracks of with locking.
Phase-locked is a dynamic process, and the response time is arranged, capture characteristic, stable state phase difference etc.The numeral phase-locked a kind of be Digital Logical Circuits, another kind of is Digital Signal Processing.No matter be that the sort of its basic principle is the same, all be a closed loop, the result of generation is basic identical.Complicated digital phase-locked loop, steady state phase error can be approximately zero in theory, is actually very difficult.Needing stable state to differ in many cases is zero.
Be defined as about the phase-locked loop steady-state error: after transient response disappears, the deviation between control variables and the set point.It is relevant with " integrator " number in the control system for theoretical proof, shows locking when the loop frequency difference is zero, and it differs:
Θ ∝=arc sin Δ ω/k+2n π (n is an integer) (1)
Δ ω is that loop bandwidth K is the loop gain coefficient, that is to say any phase-locked above error that always exists.Can become very complicated in order to reach the higher circuit that requires, realize that difficulty is bigger, because can not surmount theoretical formula (1).
The utility model is exactly under this background that needs, the system that easily realizes on the another kind of new phase-locked theory of proposition and the engineering.A kind of new phase-locked theory and technical application in the Phase Lock Technique subject, have been increased again.
Summary of the invention
The purpose of this utility model is in the phase-locked loop, when the loop frequency difference is zero its stable state differ be difficult to eliminate between topic, the phase-locked error of a kind of stable state proposed be zero phase-locked system.
The technical solution of the utility model is:
The phase-locked error of a kind of stable state is zero phase-locked system, and it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer;
An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs;
A Hilbert transformer H is used for the digital signal conversion signal that pluralizes after the sampling;
A selectivity fast Fourier transformer CFFT, be used for N/m way band filter is selected to obtain the output signal of this sub-filter, promptly complex signal is carried out fast Fourier transform, calculate and select the value F (N/m) of N/m output point of fast Fourier transform;
With an inverse Fourier transform device IFFT, be used for output valve F (N/m) to the N/m road and carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
The phase-locked error of a kind of stable state is zero phase-locked system, and it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer;
An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs;
A Hilbert transformer H is used for the digital signal conversion signal that pluralizes after the sampling;
A Fourier transformer FFT is used for complex signal is carried out fast Fourier transform, obtains the output valve of multichannel sub-filter;
A result selects module, and the output signal that is used to take out N/m sub-filter is the value F (N/m) of N/m output point of fast Fourier transform;
With an inverse Fourier transform device IFFT, be used for output valve F (N/m) to the N/m road and carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
The utility model also comprises an existing phase-locked loop circuit, comprises phase discriminator, loop filter and voltage controlled oscillator, and input signal is promptly carried out reaching the frequency lock state from motion tracking to lock signal.
In the m frequency multiplier of the present utility model: m=2,4,8 ... 2 P, P is a positive integer.
The beneficial effects of the utility model:
The utility model utilizes middle sample frequency fs of fast Fourier transform (FFT) and sampling number N to determine the natural law of each sub-filter central frequency distribution, adjust the position that sample frequency will change the bandwidth and the centre frequency of sub-filter, when sample frequency fs is the integral multiple of locked signal frequency f x, sampling number is N, then locked signal necessarily drops on N/m sub-filter centre frequency place, when sample frequency fs has locked signal frequency f x again and determines, N/m sub-filter center is exactly the position of locked signal frequency, this filter is exactly the special-purpose matched filter of input signal, its output signal frequency, phase place is exactly the frequency of locked signal, there is not steady-state error in phase place.
When sample frequency fs was m times of locked signal frequency f x, as long as calculate N/m filter output vector, then the first phase of vector was exactly the first phase of locked signal, constantly slided and just calculated the constantly phase place of output locked signal, and it is phase-locked that its function 100% is equal to what.
The utility model is the phase-locked theory that does not have the phase-locked error of stable state, be to utilize the instrument of Signal Matching filter as signal analysis and recovery, by the what signal by after the filter that mates fully with it, output signal does not produce phase lag or leading, so the phase place of its output signal is exactly a phase of input signals, signal obtains restoring after the inverse transformation.Thisly phase-lockedly used the CFFT technology, so be called selectivity fast fourier transform (Choose Fast FourieTransform).As long as just can obtain phase of input signals to N/m this matched filter calculating with plural addition and subtraction.The m frequency multiplication is a most critical with choosing N/m the output valve in the filter in the overall technology.
Description of drawings
Fig. 1 is the fundamental block diagram of existing phase-locked loop circuit.
Fig. 2 is one of theory diagram of the present utility model.
Fig. 3 is two of a theory diagram of the present utility model.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
As shown in Figure 2, the phase-locked error of a kind of stable state is zero phase-locked system, and it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer; An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs; A Hilbert transformer H is used for the signal (also can directly calculate the CFFT/FFT of real number, can obtain phase place equally but signal to noise ratio descends) that pluralizes of the digital signal conversion after the sampling; A selectivity fast Fourier transformer CFFT, be used for N/m way band filter is selected to obtain the output signal of this sub-filter, promptly complex signal is carried out fast Fourier transform, calculate and select the value F (N/m) of N/m output point of fast Fourier transform; With an inverse Fourier transform device IFFT, be used for output valve F (N/m) to the N/m road and carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
As shown in Figure 3, the phase-locked error of a kind of stable state is zero phase-locked system, and it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer; An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs; A Hilbert transformer H is used for the signal (also can directly calculate the CFFT/FFT of real number, can obtain phase place equally but signal to noise ratio descends) that pluralizes of the digital signal conversion after the sampling; A Fourier transformer FFT is used for complex signal is carried out fast Fourier transform, obtains the output valve of multichannel sub-filter; A result selects module, and the output signal that is used to take out N/m sub-filter is the value F (N/m) of N/m output point of fast Fourier transform; With an inverse Fourier transform device IFFT, be used for output valve F (N/m) to the N/m road and carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
The utility model also comprises an existing phase-locked loop circuit, comprises phase discriminator, loop filter and voltage controlled oscillator, and input signal is promptly carried out reaching the frequency lock state from motion tracking to lock signal.
In the m frequency multiplier of the present utility model: m=2,4,8 ... 2 P, P is a positive integer.
During concrete enforcement:
1, utilizes the frequency f x that existing phase-locked loop will locked signal to pin, its output frequency is carried out frequency multiplication m time, make sample frequency with fs=mfx, sampling period Ts=1/fs, m=fs/fx;
2, the digital signal after the CAD sampling is carried out " H " conversion (Hilbert transform) and become complex signal;
3, utilize complex digital signal, only the fast fourier that the individual output point of F (N/m) is carried out calculates, and promptly uses selectivity FFT (CFFT), just obtains the output signal of this filter, and it is equal to frequency, phase place and the amplitude maximum of what input signal; ,
4, inverse transformation is carried out in F (N/m) road output and can obtain signal with input signal homophase (getting I (nTs)) or quadrature (getting Q (nTs)).
The utility model utilize N point of FFT output the special relationship between each filter center frequency distribution of correspondence and the sample frequency, this relation is:
The 4db bandwidth of FFT output each point respective filter:
Δf＝1/NTs＝fs/N (2)
And fx/ Δ f=N/m (3)
Be that fx drops in i=N/m the filter, N/m be integer then fx form " mating naturally " just in time in the centre frequency position, do not have dynamic tracking.This is the root that does not produce phase error.I=N/m path filter output signal computing formula:
F ( N / m ) = ΣX n = 0 N - 1 ( nTs ) e - j 2 πn / m - - - ( 4 )
Wherein: X (nTs) is that input signal X (t) is in nTs sampled value constantly
n＝0、1、2、3......(N-1)
M=2,4,8...2 P, P is a positive integer.
N is sampling number or participates in counting (also claiming time span) of computing.This phase-locked theory of algorithm that does not have the phase-locked error of stable state, be to utilize the instrument of Signal Matching filter as signal analysis and recovery, by the what signal by after the filter that mates fully with it, output signal does not produce phase lag or leading, so the phase place of its output signal is exactly a phase of input signals, signal obtains restoring after the inverse transformation.Thisly phase-lockedly used the CFFT technology, so be called selectivity fast fourier transform (Choose FastFourieTransform).As long as just can obtain phase of input signals to N/m this matched filter calculating with plural addition and subtraction.Can save complex multiplication, reduce many workloads.
Conclusion: when sample frequency fs is m times of locked signal frequency f x, as long as calculate N/m filter output vector, then the first phase of vector is exactly the first phase of locked signal, constantly slides and just calculates the constantly phase place of output locked signal, and it is phase-locked that its function 100% is equal to what.The m frequency multiplication is a most critical with choosing N/m the output valve in the filter in the overall technology.
Embodiment one:
1, the frequency of setting input signal X (t) is fx=250kHz, and amplitude is a, and first phase is M=4, N=8, input signal divides two-way, and one the road to phase-locked loop, and another road is to the A/D conversion.The first via enters 4 frequency multipliers with its output after phase-locked, get 4fx=fs, as sampled signal;
2, A/D is output as the digital signal of 1MHz sampling, carries out " H " (Hilbert) and is for conversion into complex signal;
3, utilize formula (3) to obtain N/m=2, promptly No. 2 filters are output as:
F ( N / m ) = F ( 8 / 4 ) = F ( 2 ) = Σ n = 0 7 X ( nTs ) e - j 2 πn / 4 - - - ( 5 )
Figure BDA0000029198080000063
Figure BDA0000029198080000064
Figure BDA0000029198080000065
Figure BDA0000029198080000066
Figure BDA0000029198080000067
Figure BDA0000029198080000069
Figure BDA00000291980800000610
Figure BDA00000291980800000611
The subband frequency range is Δ f=fs/N=1MHz/8=125kHz
No. 2 filter center frequency is N/m Δ f=2*125khz=250kHz
So output signal keeps the information (frequency and first phase) of input signal fully:
Figure BDA0000029198080000071
Figure BDA0000029198080000072
Get Then be homophase output; Get
Figure BDA0000029198080000076
Then be quadrature output; Get
Figure BDA0000029198080000078
Be complex signal output.Ts is known, just obtains the function of time of input signal when n changes, and comprises frequency f x=250kHz, and first phase is Because No. 2 the filter center frequency is frequency input signal fx decision, when signal frequency fx changed, No. 2 the filter center frequency and then became, and the effect of " following the tracks of naturally " is arranged, the function of " coupling automatically ".So output phase does not lag or in advance, claim that it is a Phase Lock Technique for no steady state phase error.
The utility model does not relate to the part prior art that maybe can adopt all same as the prior art to be realized.

Claims (6)

1. the phase-locked error of stable state is zero phase-locked system, it is characterized in that it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer;
An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs;
A Hilbert transformer H is used for the digital signal conversion signal that pluralizes after the sampling;
A selectivity fast Fourier transformer CFFT, be used for N/m way band filter is selected to obtain the output signal of this sub-filter, promptly complex signal is carried out fast Fourier transform, calculate and select the value F(N/m of N/m output point of fast Fourier transform);
With an inverse Fourier transform device IFFT, be used for output valve F(N/m to the N/m road) carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
2. the phase-locked error of stable state according to claim 1 is zero phase-locked system, it is characterized in that it also comprises an existing phase-locked loop circuit, comprise phase discriminator, loop filter and voltage controlled oscillator, input signal is promptly treated lock signal carry out reaching the frequency lock state from motion tracking.
3. the phase-locked error of stable state according to claim 1 is zero phase-locked system, it is characterized in that in the described m frequency multiplier: m=2,4,8 ... 2 P, P is a positive integer.
4. the phase-locked error of stable state is zero phase-locked system, it is characterized in that it comprises:
A m frequency multiplier is used for the locking frequency fx signal of existing phase-locked loop circuit output is carried out the m frequency multiplication, obtains sample frequency fs=mfx, 2≤m≤N wherein, and N is a positive integer;
An A/D converter is sampled to the input signal of existing phase-locked loop circuit, and sample frequency is fs;
A Hilbert transformer H is used for the digital signal conversion signal that pluralizes after the sampling;
A Fourier transformer FFT is used for complex signal is carried out fast Fourier transform, obtains the output valve of multichannel sub-filter;
A result selects module, and the output signal that is used to take out N/m sub-filter is the value F(N/m of N/m output point of fast Fourier transform);
With an inverse Fourier transform device IFFT, be used for output valve F(N/m to the N/m road) carry out inverse transformation and obtain and have now the output signal that the phase-locked loop circuit input signal is promptly treated lock signal same-phase or quadrature.
5. the phase-locked error of stable state according to claim 4 is zero phase-locked system, it is characterized in that it also comprises an existing phase-locked loop circuit, comprise phase discriminator, loop filter and voltage controlled oscillator, input signal is promptly treated lock signal carry out reaching the frequency lock state from motion tracking.
6. the phase-locked error of stable state according to claim 4 is zero phase-locked system, it is characterized in that in the described m frequency multiplier: m=2,4,8 ... 2 P, P is a positive integer.
CN2010205741375U 2010-10-22 2010-10-22 Phase locking system with zero steady-state phase locking error Expired - Fee Related CN201821335U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101986568A (en) * 2010-10-22 2011-03-16 江苏锦丰电子有限公司 Steady state phase-locking error-free phase locking system and phase locking method
CN105577601A (en) * 2014-10-30 2016-05-11 联发科技股份有限公司 Circuit and communication unit for VCO frequency adjustment and frequency generation method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101986568A (en) * 2010-10-22 2011-03-16 江苏锦丰电子有限公司 Steady state phase-locking error-free phase locking system and phase locking method
CN101986568B (en) * 2010-10-22 2012-11-14 江苏锦丰电子有限公司 Steady state phase-locking error-free phase locking system and phase locking method
CN105577601A (en) * 2014-10-30 2016-05-11 联发科技股份有限公司 Circuit and communication unit for VCO frequency adjustment and frequency generation method
CN105577601B (en) * 2014-10-30 2018-12-21 联发科技股份有限公司 Circuit, wireless communication unit and frequency generating method for VCO frequency adjustment

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