CN201813397U - Wireless data communication module - Google Patents
Wireless data communication module Download PDFInfo
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- CN201813397U CN201813397U CN2010202852855U CN201020285285U CN201813397U CN 201813397 U CN201813397 U CN 201813397U CN 2010202852855 U CN2010202852855 U CN 2010202852855U CN 201020285285 U CN201020285285 U CN 201020285285U CN 201813397 U CN201813397 U CN 201813397U
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- baseband processor
- transceiver
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Abstract
The utility model provides a wireless data communication module which comprises a baseband processor and a transceiver. The transceiver comprises an amplifying circuit used for receiving an external signal and performing low-noise amplification to the external signal, a first frequency converting circuit used for performing down-frequency conversion to the amplified signal, a filter circuit used for performing channel filtration to the signal after down-frequency conversion, a switching circuit used for converting the filtered signal into a digital signal and outputting the digital signal to the baseband processor, a first control circuit used for performing gain control to the amplifying circuit according to the filtered signal, a modulation circuit used for receiving and modulating a signal from the baseband processor, and a second frequency converting circuit used for performing up-frequency conversion to the modulated signal. The baseband processor comprises a peripheral interface, a memory interface, a DSP (Data Signal Processor) and an MCU (Microprogrammed Control Unit) which are connected through a bus, and further comprises a radio-frequency interface connected with the switching circuit, the DSP and the MCU. The wireless data communication module has high integration level and high reliability, and is advantageous in performance/cost ratio.
Description
Technical field
The utility model relates to the communications field, relates in particular to a kind of RFDC module.
Background technology
At present, GSM (Global System for Mobile Communications, global system for mobile communications)/GPRS (General Packet Radio Service, the general packet radio service technology) range of application of RFDC module is very extensive, be suitable for developing some GSM/GPRS wireless application products: as mobile phone, wireless POS (point of sale, point of sales terminal) machine, radio meter register, wireless public telephone, the wireless business phone, remote monitoring, remote measurement, location positioning, products such as tracking mainly provide the voice transfer and the transfer of data of radio communication.
Existing GSM/GPRS RFDC module generally adopts Siemens, TI (Texas Instruments, Texas Instrument), MTK (MediaTek Inc., MediaTek Inc) solution, general frame is along with ASIC (Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)) progress of chip technology, and user is to the continuous increase of RFDC demand or the like factor and constantly evolution.
At present use the most general GSM/GPRS RFDC module as shown in Figure 1, can find out and mainly comprise three parts from scheming to go up: Analog Baseband partly, digital baseband part and radio-frequency module; Also comprise peripheral interface in addition, in order to connect external equipment, as clock, power management module, speech ciphering equipment, SIM card, memory, data equipment or the like.
Radio-frequency module RF mainly is responsible for functions such as the filtering, amplification, modulation of radiofrequency signal, links to each other with antenna, comprises power amplification and radio-frequency (RF) receiving and transmission module.
Analog Baseband part is mainly finished such as simulated voice digitlization, digital voice simulated, and changes digital controlled signal into analog control signal work such as (the control voltage as power amplifier form).
Digital baseband part comprises digital signal processor DSP, microcontroller MCU, memory MEM and hardware logic device Logic etc.Wherein MCU generally adopts arm processor, be responsible for finishing the processing of application layer (as man-machine interface MMI), network layer and data link layer, the peripheral circuit (keyboard, display screen etc.) of control portable terminal connects, and the realization of whole communication protocol stack, tends to system's control; The DSP data operation is powerful, is mainly used in the processing of finishing physical layer, data link layer, is responsible for the processing (coding/decoding) of voice signal, tends to the processing of digital baseband signal; MEM comprises flash memory FLASH and SRAM (Static Random Access Memory, static random access memory), can be according to the have ready conditions size of flexible configuration memory of user's application demand.
The extensive covering of GSM network and universal makes the core design scheme of its Related product, in case successfully release, can bring high technological value and commercial value, the chip design of its core simultaneously, protocol stack and corresponding hardware platform solution technology barriers height, monopoly is strong.
The utility model content
The technical problems to be solved in the utility model provides a kind of RFDC module, can reach high integration, high reliability, and possesses ratio of performance to price advantage.
In order to address the above problem, the utility model provides a kind of RFDC module, comprising: baseband processor and transceiver;
Described transceiver comprises and is used to receive outer signals and carries out the amplifying circuit that low noise amplifies, be used for the signal after amplifying is carried out first frequency changer circuit of down-conversion, be used for the signal after the down-conversion is carried out the filter circuit of channel filtering, be used for filtered signal is converted into the change-over circuit that digital signal is exported to described baseband processor, be used for described amplifying circuit being carried out the first control circuit of gain controlling according to filtered signal, be used for from the signal of described baseband processor reception and the modulation circuit of modulating, be used for the signal after the modulation is carried out second frequency changer circuit exported after the up-conversion;
Described baseband processor comprises peripheral interface, memory interface, the radio frequency interface that links to each other with described change-over circuit, digital signal processor DSP and microcontroller MCU; Described DSP, MCU, peripheral interface and memory interface link to each other with bus; Described DSP links to each other with described radio frequency interface with MCU.
Further, described RFDC module also comprises:
That link to each other, that be integrated with receiving key power amplifier, memory with extraneous antenna, the clock that links to each other with described transceiver and be used for power management module to described baseband processor, transceiver, power amplifier and memory power supply;
Described transceiver links to each other with described power amplifier; Described amplifying circuit is from the integrated receiving key received signal of described power amplifier; The signal of described second frequency changer circuit after with up-conversion exported to described power amplifier;
Described memory links to each other with the memory interface of described baseband processor.
Further, described transceiver also comprises and is used to send the second control circuit of the power waveform control signal of climbing form to described power amplifier, and is used to send three control circuit of automatic frequency control signal to described clock.
Further, the described DSP in the described baseband processor adopts ZSP400, and described MCU adopts ARM946E, and bus structures adopt Advanced Microcontroller Bus Architecture AMBA.
Further, described baseband processor adopts DTT6C01B; Described transceiver adopts PMB6277.
Further, the radio frequency interface of described DTT6C01B links to each other with the DigRF V1.12 digital interface of described PMB6277.
Further, described DigRF V1.12 digital interface comprises:
The STROBE interface is used for from the gating signal of described baseband processor reception DigRF digital interface;
The RXTXEN interface is used to receive the enable signal of the DigRF interface of being initiated by described baseband processor, and launches data and give described baseband processor; And receive data from described baseband processor according to the enable signal that receiver is initiated;
The RXTXDATA interface is used for the bursty data before described baseband processor emission IQ modulation, from described baseband processor received RF chip digital bit stream;
The CTRLEN interface is used for receiving DigRF interface 26MHz clock output enable signal from described baseband processor;
The CTRLCLK interface is used for from the clock signal of described baseband processor reception DigRF interface;
The CTRLDATA interface is used for from the data controlling signal of described baseband processor reception DigRF interface, is used with CTRLEN, CTRLCLK to constitute 3 line interfaces;
The SYSCLK interface is used for sending DigRF interface clock signal to described baseband processor.
Further, described PMB6277 comprises that also system clock enables the SYSCLKEN interface; Described DTT6C01B also comprises the OSCEN interface, links to each other with described SYSCLKEN interface, sends enable signal to described SYSCLKEN interface.
Further, described OSCEN interface enables to link to each other by first resistance between the SYSCLKEN interface with described system clock; The tie point that described first resistance and described system clock enable between the SYSCLKEN interface also passes through first capacity earth.
Further, described RXTXEN interface is also by second grounding through resistance; Described RXTXDATA interface is also by the 3rd grounding through resistance.
The technical solution of the utility model adopts DTT6C01B baseband processor and Infineon PMB6277Transceiver to constitute GSM/GPRS RFDC module, overcome with general baseband processor and realized the high power consumption that high resource requirement, the highly redundant of GSM/GPRS RFDC module cause, expensive technical disadvantages, has high technology content, high integration, high reliability, and good ratio of performance to price advantage, the every index of overall plan is good, have commercial competitiveness; The Interface design of its prioritization scheme adopts DigRF V1.12 digital interface, and the framework that DTT6C01B is cooperated with PMB6277 is reasonable, resource complementation, stable performance.
Description of drawings
Fig. 1 is the hardware configuration schematic diagram of GSM/GPRS wireless communication module in the prior art;
Fig. 2 is the hardware configuration schematic diagram of the RFDC module of embodiment one;
Fig. 3 is the connection diagram of DTT6C01B and PMB6277 among the embodiment one.
Embodiment
Below in conjunction with drawings and Examples the technical solution of the utility model is described in detail.
Need to prove that if do not conflict, each feature among the utility model embodiment and the embodiment can mutually combine, all within protection range of the present utility model.
Embodiment one, a kind of RFDC module as shown in Figure 2, comprising:
Baseband processor (Communication Oriented Multi-type Information Processor) and transceiver Transceive;
Described transceiver comprises and is used to receive outer signals and carries out the amplifying circuit that low noise amplifies, be used for the signal after amplifying is carried out first frequency changer circuit of down-conversion, be used for the signal after the down-conversion is carried out the filter circuit of channel filtering, be used for filtered signal is converted into the change-over circuit that digital signal is exported to described baseband processor, be used for described amplifying circuit being carried out the first control circuit of gain controlling according to filtered signal, be used for the signal that receives from described baseband processor and modulate the modulation circuit of (can but be not limited to Gaussian-filtered minimum shift keying GMSK modulation), be used for the signal after the modulation is carried out second frequency changer circuit exported after the up-conversion;
Described baseband processor comprises peripheral interface, memory interface, be used for the radio frequency interface, DSP and the MCU that link to each other with described change-over circuit; Described DSP, MCU, peripheral interface and memory interface link to each other with bus; Described DSP links to each other with described radio frequency interface with MCU.
In the present embodiment, described RFDC module can also comprise: that link to each other, that be integrated with receiving key power amplifier, memory with extraneous antenna, the clock that links to each other with described transceiver, the peripheral interface connector that links to each other with described peripheral interface, can connect outside keyboard, demonstration, interactive audio, data etc.; And be used for power management module to described baseband processor, transceiver, power amplifier and memory power supply;
Described transceiver links to each other with described power amplifier, and described amplifying circuit is from the integrated receiving key received signal of described power amplifier; The signal of described second frequency changer circuit after with up-conversion exported to described power amplifier;
Described memory links to each other with the memory interface of described baseband processor.
In the present embodiment, described transceiver can also comprise and is used to send Ramp (control of the climbing form) signal that the is used for power control second control circuit to described power amplifier, and be used to send the AFC that is used for FREQUENCY CONTROL (automatic frequency control, automatic frequency control) signal and give the 3rd control circuit of described clock.
In the present embodiment, the described DSP in the described baseband processor can but be not limited to adopt ZSP400, realize Layer 1 and audio coding/decoding; Described MCU can but be not limited to adopt ARM946E, realize Layer 1 control, Layer 2 and Layers 3 protocol stacks; Bus structures can but be not limited to adopt AMBA (Advanced Microcontroller Bus Architecture, Advanced Microcontroller Bus Architecture), bus speed reaches as high as 98.304MHz.
In the present embodiment, described baseband processor can but be not limited to adopt the DTT6C01B of company of Datang Microelectronics; Described transceiver can but be not limited to adopt the PMB6277 of Infineon company.
In the present embodiment, the connected mode of described DTT6C01B and described PMB6277 as shown in Figure 3:
Different with the most common traditional analog IQ interface, in the present embodiment, the radio frequency interface of described DTT6C01B links to each other with the DigRF V1.12 digital interface of described PMB6277; The automatic gain control of radio frequency, automatic frequency control, automated power control are realized by PMB6277, have simplified the interface between DTT6C01B and the PMB6277.
Described DigRF V1.12 digital interface comprises:
The STROBE interface is used for being initial modulation from the gating signal of described baseband processor reception DigRF digital interface that incidents such as power control provide accurate timing.
The RXTXEN interface is used to receive the enable signal of the DigRF interface of being initiated by described baseband processor, and launches data and give described baseband processor; And receive data from described baseband processor according to the enable signal that receiver is initiated.
The RXTXDATA interface is used to receive and dispatch the data-signal of DigRF interface, is exactly specifically: burst (burst) data before described baseband processor emission IQ modulation, and from described baseband processor received RF chip digital bit stream.
The CTRLEN interface is used for receiving DigRF interface 26MHz clock output enable signal from described baseband processor.
The CTRLCLK interface is used for from the clock signal of described baseband processor reception DigRF interface.
The CTRLDATA interface is used for from the data controlling signal of described baseband processor reception DigRF interface, is used with CTRLEN, CTRLCLK to constitute the 3-line interface, and the register of configuration radio frequency can also be read the data in the radio frequency register;
SYSCLK interface: be used for sending DigRF interface clock signal, to provide the 26MHz clock to described baseband processor to described baseband processor.
Described PMB6277 comprises that also system clock enables the SYSCLKEN interface; Described DTT6C01B also comprises the OSCEN interface, links to each other with described SYSCLKEN interface, sends enable signal to described SYSCLKEN interface; Described OSCEN interface also is used to control the shutoff and the opening signal of external crystal-controlled oscillation.
In the present embodiment, described OSCEN interface enables to link to each other by first resistance between the SYSCLKEN interface with described system clock, the resistance of described first resistance can but be not limited to 1K Ω; Described first resistance and described system clock enable tie point between the SYSCLKEN interface also by first capacity earth, described first electric capacity can but be not limited to 470nF.
In the present embodiment, described RXTXEN interface is also by second grounding through resistance; Described RXTXDATA interface is also by the 3rd grounding through resistance; Described second, third resistance all can but be not limited to 1K Ω.
In the present embodiment, DTT6C01B cooperates with PMB6277, realized the core of GSM/GPRS RFDC module hardware platform, satisfy the resource requirement of GSM/GPRS protocol stack Physical Layer 1, RLC-MAC Layers 2, RR/CM/MM Layers 3, satisfy the resource requirement of the operation of operating system, application program, man-machine interface program; Increase power amplification on this basis, core, power management has promptly been realized complete GSM/GPRS module hardware platform.
Certainly; the utility model also can have other various embodiments; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection range of claim of the present utility model.
Claims (10)
1. a RFDC module is characterized in that, comprising: baseband processor and transceiver;
Described transceiver comprises and is used to receive outer signals and carries out the amplifying circuit that low noise amplifies, be used for the signal after amplifying is carried out first frequency changer circuit of down-conversion, be used for the signal after the down-conversion is carried out the filter circuit of channel filtering, be used for filtered signal is converted into the change-over circuit that digital signal is exported to described baseband processor, be used for described amplifying circuit being carried out the first control circuit of gain controlling according to filtered signal, be used for from the signal of described baseband processor reception and the modulation circuit of modulating, be used for the signal after the modulation is carried out second frequency changer circuit exported after the up-conversion;
Described baseband processor comprises peripheral interface, memory interface, the radio frequency interface that links to each other with described change-over circuit, digital signal processor DSP and microcontroller MCU; Described DSP, MCU, peripheral interface and memory interface link to each other with bus; Described DSP links to each other with described radio frequency interface with MCU.
2. RFDC module as claimed in claim 1 is characterized in that, also comprises:
That link to each other, that be integrated with receiving key power amplifier, memory with extraneous antenna, the clock that links to each other with described transceiver and be used for power management module to described baseband processor, transceiver, power amplifier and memory power supply;
Described transceiver links to each other with described power amplifier; Described amplifying circuit is from the integrated receiving key received signal of described power amplifier; The signal of described second frequency changer circuit after with up-conversion exported to described power amplifier;
Described memory links to each other with the memory interface of described baseband processor.
3. RFDC module as claimed in claim 2 is characterized in that:
Described transceiver also comprises and is used to send the second control circuit of the power waveform control signal of climbing form to described power amplifier, and is used to send three control circuit of automatic frequency control signal to described clock.
4. RFDC module as claimed in claim 1 is characterized in that:
Described DSP in the described baseband processor adopts ZSP400, and described MCU adopts ARM946E, and bus structures adopt Advanced Microcontroller Bus Architecture AMBA.
5. RFDC module according to any one of claims 1 to 4 is characterized in that:
Described baseband processor adopts DTT6C01B; Described transceiver adopts PMB6277.
6. RFDC module as claimed in claim 5 is characterized in that:
The radio frequency interface of described DTT6C01B links to each other with the DigRF V1.12 digital interface of described PMB6277.
7. RFDC module as claimed in claim 6 is characterized in that, described DigRFV1.12 digital interface comprises:
The STROBE interface is used for from the gating signal of described baseband processor reception DigRF digital interface;
The RXTXEN interface is used to receive the enable signal of the DigRF interface of being initiated by described baseband processor, and launches data and give described baseband processor; And receive data from described baseband processor according to the enable signal that receiver is initiated;
The RXTXDATA interface is used for the bursty data before described baseband processor emission IQ modulation, from described baseband processor received RF chip digital bit stream;
The CTRLEN interface is used for receiving DigRF interface 26MHz clock output enable signal from described baseband processor;
The CTRLCLK interface is used for from the clock signal of described baseband processor reception DigRF interface;
The CTRLDATA interface is used for from the data controlling signal of described baseband processor reception DigRF interface, is used with CTRLEN, CTRLCLK to constitute 3 line interfaces;
The SYSCLK interface is used for sending DigRF interface clock signal to described baseband processor.
8. RFDC module as claimed in claim 7 is characterized in that:
Described PMB6277 comprises that also system clock enables the SYSCLKEN interface; Described DTT6C01B also comprises the OSCEN interface, links to each other with described SYSCLKEN interface, sends enable signal to described SYSCLKEN interface.
9. RFDC module as claimed in claim 8 is characterized in that:
Described OSCEN interface enables to link to each other by first resistance between the SYSCLKEN interface with described system clock; The tie point that described first resistance and described system clock enable between the SYSCLKEN interface also passes through first capacity earth.
10. RFDC module as claimed in claim 7 is characterized in that:
Described RXTXEN interface is also by second grounding through resistance; Described RXTXDATA interface is also by the 3rd grounding through resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202852855U CN201813397U (en) | 2010-08-06 | 2010-08-06 | Wireless data communication module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202852855U CN201813397U (en) | 2010-08-06 | 2010-08-06 | Wireless data communication module |
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| CN201813397U true CN201813397U (en) | 2011-04-27 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929816A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Radio frequency communication transceiver device utilizing memory controller to load programs and relative method |
| CN103346816A (en) * | 2013-06-28 | 2013-10-09 | 长沙威胜信息技术有限公司 | Wireless communication system and remote updating method thereof |
| CN105553754A (en) * | 2015-12-08 | 2016-05-04 | 重庆金美通信有限责任公司 | Wireless communication device testability design method |
-
2010
- 2010-08-06 CN CN2010202852855U patent/CN201813397U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929816A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Radio frequency communication transceiver device utilizing memory controller to load programs and relative method |
| CN103346816A (en) * | 2013-06-28 | 2013-10-09 | 长沙威胜信息技术有限公司 | Wireless communication system and remote updating method thereof |
| CN105553754A (en) * | 2015-12-08 | 2016-05-04 | 重庆金美通信有限责任公司 | Wireless communication device testability design method |
| CN105553754B (en) * | 2015-12-08 | 2019-04-16 | 重庆金美通信有限责任公司 | A kind of wireless telecom equipment design method of testability |
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Granted publication date: 20110427 |
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