CN201773278U - Processing box chip - Google Patents
Processing box chip Download PDFInfo
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- CN201773278U CN201773278U CN2010205278133U CN201020527813U CN201773278U CN 201773278 U CN201773278 U CN 201773278U CN 2010205278133 U CN2010205278133 U CN 2010205278133U CN 201020527813 U CN201020527813 U CN 201020527813U CN 201773278 U CN201773278 U CN 201773278U
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Abstract
The utility provides a processing box chip, which comprises a LC circuit, a parasitic power supply circuit, a synchronized clock circuit , a subcarrier modulation circuit and a MCU.A MCU first internal timer is connected with the MCU pin IO1 of the synchronized clock circuit and the output terminal of the LC circuit by frequency division signals.A MCU second internal timer is arranged for accounting the quantity of frequency division signals.A MCU built-in oscillator is connected with the MCU second internal timer for providing a clock reference.The MCU first internal timer outputs the frequency division signals to start the reading of the timing of the MCU second internal timer.Resistor R4 of the subcarrier modulation circuit is connected with the MCU pin IO2, so that subcarrier modulation signals are provided directly through IO2 by MCU.Synchronized clock signals of the LC circuit are connected with the MCU pin IO1 by the synchronized clock circuit after being coupled by capacitor C3.The processing box chip of the present utility model has a high reliability and a good stability.
Description
Technical field
The utility model relates to a kind of chip, specifically, relates to and a kind ofly being exclusively used on the handle box and printer transmits information processing box chip being installed in.
Background technology
An existing class handle box, the chip that can carry out radio signal transmission with printer and information storage function is arranged is installed, thereby make printer can read the information that is stored in the process box chip, for example, printer can read the type information corresponding to handle box from process box chip, compare and discern, can also write the relevant information of holding the real-time surplus of toner in the reflection handle box in the process box chip.Therefore, if when being installed to a dissimilar handle box in the printer mistakenly, printer can detect this handle box and be installed mistakenly, and provides the prompting of setup error.In addition, the quantity that printer can have been printed according to this handle box, the use history of handle box is written in the process box chip, make the fabricator can from the process box chip that the user returns, read the relevant historical information of using, thus, can carry out inspection, unit replacement work in the Regeneration Treatment exactly, increase work efficiency.
Publication number is that the Chinese invention patent application that CN101089750, name are called " method of process box chip and demodulating information thereof " then provides a kind of process box chip, referring to Fig. 1, this process box chip 1 ' comprises lc circuit 2 ', parasite power circuit 3 ', MCU4 ', sub-carrier modulation circuit 5 ', synchronous clock 6 ', frequency divider 7 ' and clock reference 8 ', owing to adopted frequency divider 7 ' in the chip, therefore power consumption increases, the chip less stable; Adopt the external active crystal oscillator in its clock reference 8 ', not only making the circuit structure complexity has also increased power consumption greatly; Simultaneously, adopt two triode Q1 and Q2 and biasing resistor in the sub-carrier modulation circuit 5 ', caused that the loss of power consumption strengthens, directly influenced the stability of chip; Reduced the functional reliability of this process box chip.
Summary of the invention
Fundamental purpose of the present utility model provides the process box chip of a kind of reliability height, working stability, to solve above-mentioned the deficiencies in the prior art part.
For achieving the above object, the process box chip that provides of the utility model comprises:
Be used to receive and dispatch the LC circuit of electromagnetic wave signal;
Be connected the LC circuit output end, be used for electromagnetic wave signal is converted to the parasite power circuit of chip operation supply voltage;
Be connected the synchronous clock circuit of LC circuit output end;
Be connected the LC circuit output end, the chip internal information modulated and outwards sent by the LC circuit sub-carrier modulation circuit of electromagnetic wave signal;
The MCU that is connected with synchronous clock circuit and sub-carrier modulation circuit input end respectively;
MCU first timer internal, this MCU first timer internal is connected with synchronous clock circuit by MCU pin IO1, and is connected to the output terminal of lc circuit, is used for the signal of lc circuit output is carried out frequency division;
MCU second timer internal is used to measure the MCU clock reference quantity in the first timer internal frequency division output signal cycle; And
The built-in oscillator of MCU that is connected with MCU second timer internal is used for providing clock reference to MCU second timer internal;
The MCU first timer internal frequency division output signal reads the value of MCU second timer internal with startup.
By above scheme as seen, the process box chip that the utility model provides utilizes the timer of MCU inside by count mode the external clock of IO1 to be counted, and utilizes the characteristic of counting to carry out frequency division, thereby has saved frequency divider; Utilize the system clock of the clock of MCU internal oscillator generation, thereby saved the clock reference in the existing chip circuit as MCU work; And the MCU internal oscillator less with power consumption replaces the bigger active crystal oscillator of power consumption; Therefore, simplify circuit greatly, reduced power consumption, thereby improved the job stability of chip.
Its further technical scheme is, the sub-carrier modulation circuit comprises triode Q1, resistance R 3, R4, diode D3 and D4, resistance R 4 is connected between the base stage of the pin IO2 of MCU and triode Q1, resistance R 3 is connected on the collector of triode Q1 and the negative electrode of diode D3, diode D4, and the anode of diode D3 and diode D4 is connected on the two ends of lc circuit respectively.Scheme as seen thus, MCU directly provides modulated subcarrier signal by pin IO2, avoided obtaining one road signal carries out sub-carrier modulation again with the IO15 modulation signal of MCU mode by frequency dividing circuit in the prior art, directly provide the mode of modulated subcarrier signal to make that circuit is simple, power consumption reduces, chip operation stability is higher.
Further technical scheme is again, synchronous clock circuit comprises capacitor C 3 and resistance R 2, one end of capacitor C 3 links to each other with the anode of an end of lc circuit and diode D1, diode D3, the other end of capacitor C 3 and an end of resistance R 2 are connected and are connected to the pin IO1 of MCU, the other end ground connection of resistance R 2.
In the above-mentioned further again scheme, being coupled the synchronizing clock signals of lc circuit through capacitor C 3 after, synchronous clock is incorporated into the pin IO1 of MCU, the mode of capacitive coupling synchronous clock is with respect to the mode of available technology adopting electric resistance partial pressure synchronous clock, its clock output attenuatoin is littler, influence of fluctuations to modulation signal is littler, thereby has improved the job stability of chip.
Description of drawings
Fig. 1 is the circuit structure diagram of existing process box chip.
Fig. 2 is the circuit structure diagram of the utility model embodiment.
The utility model is described in further detail below in conjunction with embodiment and accompanying drawing thereof.
1 ', 1-process box chip, 2 ', the 2-LC circuit, 3 ', 3-parasite power circuit, 4 ', 4-MCU, 41-MCU first timer internal, 42-MCU second timer internal, 43-MCU internal oscillator, 5 ', 5-sub-carrier modulation circuit, 6 ', the 6-synchronous clock circuit, 7 '-frequency divider, 8 '-clock reference.
Embodiment
Referring to Fig. 2, process box chip 1 comprises: the LC circuit 2 that is used to receive and dispatch electromagnetic wave signal; Be connected LC circuit 2 output terminals, be used for electromagnetic wave signal is converted to the parasite power circuit 3 of chip operation supply voltage; Be connected the synchronous clock circuit 6 of LC circuit 2 output terminals; Be connected lc circuit 2 output terminals, the chip internal information modulated and outwards sent the sub-carrier modulation circuit 5 of electromagnetic wave signal by LC circuit 2; The MCU4 that is connected with synchronous clock circuit 6 and sub-carrier modulation circuit 5 respectively.
Wherein, lc circuit 2 comprises inductance L 1 and capacitor C 1 in parallel, and the electromagnetic signal that lc circuit 2 induction main equipments or card reading module are sent becomes electric signal to field signal; When modulation signal returned, this circuit was transformed into field signal to the electric signal of modulation again, thereby main equipment or card reading module receive behind this field signal and it to be changed into electric signal and handle the back and obtain the data that chip returns.
Synchronous clock circuit 6 comprises capacitor C 3 and resistance R 2, output terminal of one end of capacitor C 3 and lc circuit and the anode of diode D1, diode D3 link to each other, the other end of capacitor C 3 and an end of resistance R 2 are connected and are connected to the pin IO1 of MCU4, the other end ground connection of resistance R 2.By above-mentioned structure, synchronous clock circuit 6 is incorporated into the synchronizing clock signals of lc circuit 2 the pin IO1 of MCU4 after capacitor C 3 couplings, therefore substituted the mode of existing use electric resistance partial pressure synchronous clock, make that the clock decay is littler, influence of fluctuations to modulation signal is littler, has improved the stability of chip.
Owing to when the timer internal of MCU4 is in timer pattern following time, increase progressively in each instruction cycle, when the timer internal of MCU4 is in count mode following time, externally each rising edge or the negative edge imported of clock increases progressively.Therefore, present embodiment is set at count mode with first timer internal 41 of MCU4, external clock to MCU4 pin IO1 is counted, utilize the counting properties of this MCU first timer internal 41 to carry out frequency division, the fractional frequency signal that obtains is exported to MCU second timer internal 42 is read MCU second timer internal 42 as startup signal; This MCU second timer internal 42 is connected with MCU internal oscillator 43, MCU second timer internal 42 is set at timing mode, the clock that MCU4 internal oscillator 43 is produced is as the system clock of MCU work and the timer clock of MCU second timer internal 42, n system clock formed an instruction cycle clock, thereby the clock value of MCU second timer internal 42 increased progressively under each instruction cycle; After MCU first timer internal 41 obtains fractional frequency signal by count mode, MCU4 utilizes fractional frequency signal to start to read the value of MCU second timer internal 42, this value is relevant with instruction cycle number in the fractional frequency signal cycle, promptly relevant with the clock number of MCU internal oscillator 43, can demodulate the data 0 and the data 1 of fsk signal by the number of clock, as: at a frequency division of MCU first timer internal 41 output in the cycle, the clock reference number of MCU second timer internal 42 meterings was greater than 50 o'clock, restituted signal is 0, when the clock reference of MCU second timer internal 42 metering less than 50 the time, restituted signal is 1; Omit existing frequency divider 7 ' and clock reference 8 ' in the foregoing circuit structure, greatly reduce power consumption, improved the stability of chip.
Sub-carrier modulation circuit 5 comprises triode Q1, resistance R 3, R4, diode D3 and D4, resistance R 4 is connected between the base stage of the pin IO2 of MCU4 and triode Q1, resistance R 3 is connected on the collector of triode Q1 and the negative electrode of diode D3, diode D4, the anode of diode D3 and diode D4 is connected on the two ends of lc circuit 2 respectively, the grounded emitter of triode Q1.By said structure, MCU4 directly provides modulated subcarrier signal by its pin IO2, makes circuit reduction, power consumption reduce.
The inside of MCU4 is provided with program, and the pin VDD of MCU4 meets power supply VCC, pin GND ground connection.
As a kind of conversion of the utility model embodiment, synchronous clock circuit 6 can adopt the mode that includes only capacitor C 3, equally also can realize goal of the invention of the present utility model.
As another conversion of the utility model embodiment, sub-carrier modulation circuit 5 can adopt following connected mode: the anode of diode D3 is connected between diode D1 negative electrode and the resistance R 1, equally also can realize goal of the invention of the present utility model.
As the another conversion of the utility model embodiment, parasite power circuit 2 can also adopt bridge rectifier filtering, and this conversion can realize that equally also the utility model improves the goal of the invention of chip reliability and stability.
The utility model is not limited to the foregoing description and conversion, and other also should be included in the protection domain of the utility model claim based on technical solutions of the utility model and without prejudice to the structural change of the present utility model purpose.
Claims (8)
1. process box chip comprises:
Be used to receive and dispatch the LC circuit of electromagnetic wave signal;
Be connected described LC circuit output end, be used for electromagnetic wave signal is converted to the parasite power circuit of chip operation supply voltage;
Be connected the synchronous clock circuit of described LC circuit output end;
Be connected described LC circuit output end, the chip internal information modulated and outwards sent by described LC circuit the sub-carrier modulation circuit of electromagnetic wave signal;
The MCU that is connected with described synchronous clock circuit and described sub-carrier modulation circuit input end respectively;
It is characterized in that:
MCU first timer internal, described MCU first timer internal is connected with described synchronous clock circuit by described MCU pin IO1, and is connected to the output terminal of described lc circuit, is used for the signal of described lc circuit output is carried out frequency division;
MCU second timer internal is used to measure the clock reference quantity in the described first timer internal frequency division output signal cycle of MCU; And
The built-in oscillator of MCU that is connected with MCU second timer internal is used for providing clock reference to described MCU second timer internal;
The described MCU first timer internal frequency division output signal reads the value of described MCU second timer internal with startup.
2. process box chip according to claim 1 is characterized in that:
Described sub-carrier modulation circuit comprises triode Q1, resistance R 3, R4, diode D3 and D4, resistance R 4 is connected between the base stage of the pin IO2 of described MCU and triode Q1, resistance R 3 is connected on the collector of triode Q1 and the negative electrode of diode D3, diode D4, the grounded emitter of triode Q1, the anode of diode D3 and diode D4 is connected on the two ends of described lc circuit respectively.
3. process box chip according to claim 1 and 2 is characterized in that:
Described synchronous clock circuit comprises capacitor C 3 and resistance R 2, one end of capacitor C 3 links to each other with the anode of an end of described lc circuit and diode D1, diode D3, the other end of capacitor C 3 and an end of resistance R 2 are connected and are connected to the pin IO1 of described MCU, the other end ground connection of resistance R 2.
4. process box chip according to claim 1 and 2 is characterized in that:
Described synchronous clock circuit comprises capacitor C 3, and an end of capacitor C 3 links to each other with the anode of an end of described lc circuit and diode D1, diode D3, and the other end of capacitor C 3 is connected to the pin IO1 of described MCU.
5. process box chip according to claim 3 is characterized in that:
Described parasite power circuit comprises diode D1, diode D2, resistance R 1 and capacitor C 2, the anode of diode D1 is connected with an end of described lc circuit, negative electrode is connected with an end of resistance R 1, the other end of resistance R 1 is connected with power supply VCC with an end of capacitor C 2, the other end ground connection of capacitor C 2, the plus earth of diode D2, negative electrode is connected with the other end of described lc circuit.
6. process box chip according to claim 4 is characterized in that:
Described parasite power circuit comprises diode D1, diode D2, resistance R 1 and capacitor C 2, the anode of diode D1 is connected with an end of described lc circuit, negative electrode is connected with an end of resistance R 1, the other end of resistance R 1 is connected with power supply VCC with an end of capacitor C 2, the other end ground connection of capacitor C 2, the plus earth of diode D2, negative electrode is connected with the other end of described lc circuit.
7. process box chip according to claim 5 is characterized in that:
Described lc circuit comprises inductance L 1 and capacitor C 1 in parallel.
8. process box chip according to claim 6 is characterized in that:
Described lc circuit comprises inductance L 1 and capacitor C 1 in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205278133U CN201773278U (en) | 2010-09-14 | 2010-09-14 | Processing box chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205278133U CN201773278U (en) | 2010-09-14 | 2010-09-14 | Processing box chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201773278U true CN201773278U (en) | 2011-03-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205278133U Expired - Fee Related CN201773278U (en) | 2010-09-14 | 2010-09-14 | Processing box chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201773278U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
| WO2014201949A1 (en) * | 2013-06-20 | 2014-12-24 | 珠海天威技术开发有限公司 | Consumable chip and operating method thereof, and consumable container |
| CN114236991A (en) * | 2017-12-27 | 2022-03-25 | 兄弟工业株式会社 | Image forming apparatus with a toner supply device |
-
2010
- 2010-09-14 CN CN2010205278133U patent/CN201773278U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103389644A (en) * | 2013-06-19 | 2013-11-13 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
| CN103389644B (en) * | 2013-06-19 | 2017-02-08 | 杭州士兰微电子股份有限公司 | Timing system and timing method |
| WO2014201949A1 (en) * | 2013-06-20 | 2014-12-24 | 珠海天威技术开发有限公司 | Consumable chip and operating method thereof, and consumable container |
| CN114236991A (en) * | 2017-12-27 | 2022-03-25 | 兄弟工业株式会社 | Image forming apparatus with a toner supply device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110323 Termination date: 20180914 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |