CN201754585U - Driving testing device for wire train bus of UIC gateway - Google Patents

Driving testing device for wire train bus of UIC gateway Download PDF

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Publication number
CN201754585U
CN201754585U CN2009202480370U CN200920248037U CN201754585U CN 201754585 U CN201754585 U CN 201754585U CN 2009202480370 U CN2009202480370 U CN 2009202480370U CN 200920248037 U CN200920248037 U CN 200920248037U CN 201754585 U CN201754585 U CN 201754585U
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CN
China
Prior art keywords
switch
pin
resistance
capacitor
interface
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009202480370U
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Chinese (zh)
Inventor
武生国
王�锋
刘瑞
陈玉飞
于明
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CRRC Dalian R&D Co Ltd
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CNR Dalian Electric Traction R& D Center Co Ltd
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Priority to CN2009202480370U priority Critical patent/CN201754585U/en
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Publication of CN201754585U publication Critical patent/CN201754585U/en
Anticipated expiration legal-status Critical
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Abstract

The utility model discloses a driving tool for a wire train bus of a UIC (international union of railways) gateway, which comprises a shell and a circuit board. The circuit board is connected with a physical interface and a switch on the shell by a lead wire. When in real testing, only the interface on the shell needs to be connected and the switch needs to be turned on. With the characteristics of novel design, high reliability, high flexibility and low cost, the testing tool which meets the UIC 556 and IEC 61375 standards can effectively test the driving of the wire train bus of the UIC gateway and is indispensable in the testing experiment of the UIC gateway. As the UIC gateway is already used on many rapid railways and subways at present, the testing tool has wide application prospect in the field.

Description

UIC gateway wired train bus drives testing apparatus
Technical field
The utility model relates to a kind of UIC gateway wired train bus and drives testing tool.
Background technology
International Union of Railways has formulated UIC556 TCN transmission standard at present, and the data on the train bus-line are carried out standard.Dissimilar, the locomotive of different manufacturers, the vehicle that meet the UIC556 standard can be realized interoperability after heavily joining.The critical component of UIC TCN is the UIC gateway, and the UIC gateway is to have added the UIC application component to realize on the basis of TCN gateway, is the node of control data transmission between wired train bus and the multifunction vehicle bus.At present, all using the UIC gateway on a lot of high-speed railways and railcar, whether wired train bus operate as normal, is related to the communication of whole train network.And wired train bus driving test is a more complicated, and reliability is also very low.Drive the existing problem of test at present UIC gateway wired train bus, at existing problem in the above-mentioned prior art, a kind of novel UIC gateway wired train bus of research and design drives testing apparatus, and existing problem is very necessary in the prior art thereby overcome.
Summary of the invention
In view of existing problem in the above-mentioned prior art, the purpose of this utility model is that a kind of novel UIC gateway wired train bus of research and design drives testing apparatus, problems such as thereby the solution wired train bus drives the test more complicated, and reliability is also very low.UIC gateway wired train bus described in the utility model drives testing apparatus and is made up of circuit board, shell, physical interface and switch.Physical interface and switch are housed on the panel of described shell, circuit board is housed in the shell.Physical interface on the housing face-plate is connected with circuit board by line with switch.
Circuit board described in the utility model is made up of the chip GAL22V10 of chip 74HC4060 and Lattice semiconductor company.By resistance R 1, crystal oscillator BX1, the signal that the clock circuit that capacitor C 1 and capacitor C 2 are formed produces, be transported to the pin one 0 and 11 of chip 74HC4060, chip 74HC4060 produces the input signal of the signal of 10 different frequencies as chip GAL22V10 then, the output Q4 of chip 74HC4060, Q5, Q6, Q7, Q8, Q9, Q10, Q12, Q13 and Q14 be the input 2 of corresponding chip GAL22V10 respectively, 3,4,5,6,7,1,8,9 and 10, the pin two 1 of GAL22V10,22 and 23 output to three ports of physical interface respectively, at last by 4 of interface X2,3,2 pins are exported to basic equipment; Pin 4 ground connection of the switch TXRX that is connected with circuit board; The pin one connecting resistance R15 of switch TXRX and capacitor C 12, the other end ground connection of resistance R 15, the other end of capacitor C 12 is by connection interface GEN again after the resistance R 3; The pin two connection interface OX of switch TXRX and 1 end of interface X1; The pin 5 connection interface OY of switch TXRX and 3 ends of interface X1.In parallel with resistance R 9 again behind resistance R 10 and capacitor C 6 polyphones, wherein the other end of capacitor C 6 is received the pin 6 of switch TXRX, and the other end of resistance R 10 is received the pin one of switch HEAVY, and the pin two of switch HEAVY is received the pin 3 of switch TXRX; In parallel with resistance R 8 again behind resistance R 7 and capacitor C 5 polyphones, wherein the other end of capacitor C 5 is received the pin 6 of switch TXRX, and the other end of resistance R 7 is received the pin 3 of switch TXRX; After resistance R 14, R13 and capacitor C 7, the C8 parallel connection, connect with resistance R 12 again, the other end of resistance R 12 connects resistance R 11 and capacitor C 3, the other end of resistance R 11 is received the pin two of capacitor C 4 and switch LINE, the pin one of final switch LINE is received the pin 3 of switch TXRX, and wherein the other end of resistance R 13 and R14 and capacitor C 7, C8, C3 and C4 is all received the pin 6 of switch TXRX.
Circuit board described in the utility model is by the Kai Heguan of switch TX-RX, entire circuit is divided into the two large divisions, and TX-RX opens when switch, 1 and 4 and 2 and 5 of switch TX-RX connects at this moment, when TX, LINE and HEAVY close, be used for the test of WTB link receiver, GEN receives from the signal of signal generator output, through R3 and C12, export to the OX interface of basic equipment at last from the OX interface, the OY interface is connected with ground in equipment, and externally, it is connected with the OY interface of basic equipment; TX-RX closes when switch, and 3 and 6 and 2 and 5 of switch TX-RX connects, and TX opens and LINE and HEAVY when closing, and this moment, this testing equipment was used for the test of WTB link transmitter.
Acp chip on the circuit board described in the utility model adopts the GAL22V10 of Lattice semiconductor company, and it is carried out certain configuration, its input is connected with the output of chip 74HC4060, and output directly is connected with physical interface, draws (drop-down) resistance but added; In this testing tool, what chip 74HC4060 adopted is external timing signal, and clock signal is input to chip 74HC4060 from OSC1, RES ground connection.The signal that signal generator produces, is exported from physical interface OX and OY behind testing tool from physical interface GEN input, during, by the opening and closing of switch, make signal pass through different paths, thus the difference in functionality of test UIC gateway.
Described circuit board is the core that whole UIC gateway wired train bus drives testing tool, mainly is responsible for the function of conversion of signals.
The material of described shell is hard plastics, carries lightly and dexterous, is easy to dismounting and maintenance; Physical interface and switch are all thereon.
Described physical interface is the external interface circuit of whole testing tool, and it is input to the signal that signal generator produces on the circuit board, and then the signal after will changing outputs to next unit.
Described switch determines the flow direction of whole signal, thereby makes the signal difference of output that circuit board is changed.
Above-mentioned four parts are combined, just formed a kind of UIC gateway wired train bus and driven testing tool, make it have reliability, flexibility, versatility, low cost and other advantages.
Description of drawings
The utility model has three width of cloth accompanying drawings, wherein:
Fig. 1 is a layout structure schematic diagram of the present utility model;
Fig. 2 is an application schematic diagram of the present utility model
Fig. 3 is the structural representation of electric wiring of the present utility model.
Among the figure: 1, circuit board 2, shell 3, physical interface 4, switch
Embodiment
Specific embodiment of the utility model as shown in Figure 1, UIC gateway wired train bus drives testing apparatus, is made up of circuit board 1, shell 2, physical interface 3 and switch 4.Physical interface 3 and switch 4 are housed on the panel of described shell 2, circuit board 1 is housed in the shell 2.Physical interface 3 on shell 2 panels is connected with circuit board 1 by line with switch 4.
Accompanying drawing 3 is depicted as circuit board 1 described in the utility model and is made up of the chip 6AL22V10 of chip 74HC4060 and Lattice semiconductor company; By R1, BX1, the signal that the clock circuit that C1 and C2 form produces, be transported to the pin one 0 and 11 of chip 74HC4060, chip 74HC4060 produces the input signal of the signal of 10 different frequencies as chip GAL22V10 then, the output Q4 of chip 74HC4060, Q5, Q6, Q7, Q8, Q9, Q10, Q12, Q13 and Q14 be the input 2 of corresponding chip GAL22V10 respectively, 3,4,5,6,7,1,8,9 and 10, the pin two 1 of GAL22V10,22 and 23 output to the SHORT of physical interface 3 respectively, nENO and MANO are at last by 4 of interface X2,3,2 pins are exported to basic equipment; Pin 4 ground connection of the described switch TXRX that is connected with circuit board 1; The pin one connecting resistance R15 of switch TXRX and capacitor C 12, the other end ground connection of resistance R 15, the other end of capacitor C 12 meets GEN after by resistance R 3 again; The pin two of switch TXRX connects 1 end of OX and interface X1; The pin 5 of switch TXRX connects 3 ends of OY and interface X1.In parallel with resistance R 9 again behind resistance R 10 and capacitor C 6 polyphones, wherein the other end of capacitor C 6 is received the pin 6 of switch TXRX, and the other end of resistance R 10 is received the pin one of switch HEAVY, and the pin two of switch HEAVY is received the pin 3 of switch TXRX; In parallel with resistance R 8 again behind resistance R 7 and capacitor C 5 polyphones, wherein the other end of capacitor C 5 is received the pin 6 of switch TXRX, and the other end of resistance R 7 is received the pin 3 of switch TXRX; After resistance R 14, R13 and capacitor C 7, the C8 parallel connection, connect with resistance R 12 again, the other end of resistance R 12 connects resistance R 11 and capacitor C 3, the other end of resistance R 11 is received the pin two of capacitor C 4 and switch LINE, the pin one of final switch LINE is received the pin 3 of switch TXRX, and wherein the other end of resistance R 13 and R14 and capacitor C 7, C8, C3 and C4 is all received the pin 6 of switch TXRX.
Circuit board 1 described in the utility model is by the Kai Heguan of switch TX-RX, entire circuit is divided into the two large divisions, and TX-RX opens when switch, 1 and 4 and 2 and 5 of switch TX-RX connects at this moment, when TX, LINE and HEAVY close, be used for the test of WTB link receiver, GEN receives from the signal of signal generator output, through R3 and C12, export to the OX interface of basic equipment at last from the OX interface, the OY interface is connected with ground in equipment, and externally, it is connected with the OY interface of basic equipment; TX-RX closes when switch, and 3 and 6 and 2 and 5 of switch TX-RX connects, and TX opens and LINE and HEAVY when closing, and this moment, this testing equipment was used for the test of WTB link transmitter.
Concrete application of the present utility model as shown in Figure 2, the circuit among Fig. 2 is to be used for WTB link receiver test.Operating procedure is as follows:
(1) the connector A of basic equipment (CAN female) is connected to the DIRA1 of UIC gateway MAU circuit board 1, and the connector B of basic equipment (CAN male) is connected to the DIRA2 of UIC gateway MAU circuit board 1;
(2) check and to remove AFRITn and BFRITn outside the state of opening, the position whether all switches of all the other of basic equipment are all closing;
(3) switch the HEAVY that UIC gateway wired train bus drives testing tool, LINE and TX switch TX/RX to the position of opening to off-position;
(4) the switch A1RELDIR of switching basic equipment and A2RELDIR are to the position of opening;
(5) open oscilloscope and signal generator, the signalization generator is to triangular wave, frequency 100KHZ, as far as possible little amplitude; Connect the signal generator UIC gateway wired train bus of popping one's head in and drive the GEN and the GND of testing tool, oscillographic first passage connects the OX (just) and the OY (bearing) of basic equipment, and oscillographic second channel connects the test point OSC_A of basic equipment and regulates pin is GND;
(6) power supply 5V ± 250mY and current limliting 1000mA are set, connect power supply to UIC gateway MAU circuit board 1;
(7) the oscilloscope first passage is measured triangular wave amplitude between OX and OY, increase the triangular wave amplitude gradually and square-wave waveform clearly occurs up to second channel, read the range value of triangular wave in the first passage, check its range value whether in the regulation allowed band, whether the polarity of its spike is correct;
(8) process similar to the A road done on the B road of UIC gateway MAU circuit board 1.

Claims (3)

1. a UIC gateway wired train bus drives testing apparatus, is made up of circuit board (1), shell (2), physical interface (3) and switch (4); It is characterized in that on the panel of described shell (2) physical interface (3) and switch (4) being housed, circuit board (1) is housed in the shell (2); Physical interface (3) on shell (2) panel is connected with circuit board (1) by line with switch (4).
2. UIC gateway wired train bus according to claim 1 drives testing apparatus, it is characterized in that described circuit board (1) is made up of the chip GAL22V10 of chip 74HC4060 and Lattice semiconductor company; By resistance R 1, crystal oscillator BX1, the signal that the clock circuit that capacitor C 1 and capacitor C 2 are formed produces, be transported to the pin one 0 and 11 of chip 74HC4060, chip 74HC4060 produces the input signal of the signal of 10 different frequencies as chip GAL22V10 then, the output Q4 of chip 74HC4060, Q5, Q6, Q7, Q8, Q9, Q10, Q12, Q13 and Q14 be the input 2 of corresponding chip GAL22V10 respectively, 3,4,5,6,7,1,8,9 and 10, the pin two 1 of GAL22V10,22 and 23 output to three ports of physical interface (3) respectively, at last by 4 of interface X2,3,2 pins are exported to basic equipment; Pin 4 ground connection of the switch TXRX that is connected with circuit board (1); The pin one connecting resistance R15 of switch TXRX and capacitor C 12, the other end ground connection of resistance R 15, the other end of capacitor C 12 is by connection interface GEN again after the resistance R 3; The pin two connection interface OX of switch TXRX and 1 end of interface X1; The pin 5 connection interface OY of switch TXRX and 3 ends of interface X1; In parallel with resistance R 9 again behind resistance R 10 and capacitor C 6 polyphones, wherein the other end of capacitor C 6 is received the pin 6 of switch TXRX, and the other end of resistance R 10 is received the pin one of switch HEAVY, and the pin two of switch HEAVY is received the pin 3 of switch TXRX; In parallel with resistance R 8 again behind resistance R 7 and capacitor C 5 polyphones, wherein the other end of capacitor C 5 is received the pin 6 of switch TXRX, and the other end of resistance R 7 is received the pin 3 of switch TXRX; After resistance R 14, R13 and capacitor C 7, the C8 parallel connection, connect with resistance R 12 again, the other end of resistance R 12 connects resistance R 11 and capacitor C 3, the other end of resistance R 11 is received the pin two of capacitor C 4 and switch LINE, the pin one of final switch LINE is received the pin 3 of switch TXRX, and wherein the other end of resistance R 13 and R14 and capacitor C 7, C8, C3 and C4 is all received the pin 6 of switch TXRX.
3. UIC gateway wired train bus according to claim 1 (WTB) drives testing apparatus, it is characterized in that the Kai Heguan of described circuit board (1) by switch TX-RX, entire circuit is divided into the two large divisions, TX-RX opens when switch, 1 and 4 and 2 and 5 of switch TX-RX connect at this moment, work as TX, when LINE and HEAVY close, be used for the test of WTB link receiver, GEN receives from the signal of signal generator output, through R3 and C12, export to the OX interface of basic equipment at last from the OX interface, the OY interface is connected with ground in equipment, externally, it is connected with the OY interface of basic equipment; TX-RX closes when switch, and 3 and 6 and 2 and 5 of switch TX-RX connects, and TX opens and LINE and HEAVY when closing, and this moment, this testing equipment was used for the test of WTB link transmitter.
CN2009202480370U 2009-11-11 2009-11-11 Driving testing device for wire train bus of UIC gateway Expired - Fee Related CN201754585U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009202480370U CN201754585U (en) 2009-11-11 2009-11-11 Driving testing device for wire train bus of UIC gateway

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Application Number Priority Date Filing Date Title
CN2009202480370U CN201754585U (en) 2009-11-11 2009-11-11 Driving testing device for wire train bus of UIC gateway

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Publication Number Publication Date
CN201754585U true CN201754585U (en) 2011-03-02

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103457804A (en) * 2013-09-11 2013-12-18 青岛四方车辆研究所有限公司 Consistency testing platform of train network communication products
CN106603120A (en) * 2016-12-21 2017-04-26 株洲中车时代电气股份有限公司 Anti-interference system of train WTB communication cable detection apparatus, and control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103457804A (en) * 2013-09-11 2013-12-18 青岛四方车辆研究所有限公司 Consistency testing platform of train network communication products
CN106603120A (en) * 2016-12-21 2017-04-26 株洲中车时代电气股份有限公司 Anti-interference system of train WTB communication cable detection apparatus, and control method thereof

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110302

Termination date: 20131111