CN201717856U - GSM digital wireless repeater capable of automatically setting carrier frequency - Google Patents
GSM digital wireless repeater capable of automatically setting carrier frequency Download PDFInfo
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- CN201717856U CN201717856U CN2010202645412U CN201020264541U CN201717856U CN 201717856 U CN201717856 U CN 201717856U CN 2010202645412 U CN2010202645412 U CN 2010202645412U CN 201020264541 U CN201020264541 U CN 201020264541U CN 201717856 U CN201717856 U CN 201717856U
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Abstract
The utility model provides a GSM digital wireless repeater capable of automatically setting carrier frequency, which comprises a donor end duplexer, a downlink low-noise amplifier, an uplink low-noise amplifier, a first frequency conversion module, a data processing module, a second frequency conversion module, a downlink power amplifier circuit, an uplink power amplifier circuit, a re-transmitting end duplexer, a monitoring unit and a power supply unit, wherein the donor end duplexer, the downlink low-noise amplifier, the first frequency conversion module, the data processing module, the second frequency conversion module, the downlink power amplifier circuit and the re-transmitting end duplexer are sequentially connected to form a downlink; and the re-transmitting end duplexer, the uplink low-noise amplifier, the second frequency conversion module, the data processing module, the first frequency conversion module, the uplink power amplifier circuit and the donor end duplexer are sequentially connected to form an uplink. Parameters configured for carriers of the repeater can change along with the change of the parameters configured for the carriers of a sector of an information source base station, so as to reduce the engineering maintenance of the repeater and ensure the normal and stable working of the system.
Description
[technical field]
The utility model relates to a kind of covering system of mobile communication signal, particularly relates to the GSM digital radio repeater that a kind of carrier frequency is provided with automatically.
[background technology]
In today that mobile communication develops rapidly; no matter the overlay area of which kind of radio communication is because blocking of radio frequency signal propagation characteristics and artificial or natural forms; blind area, weak signal area appear through regular meeting; these zones occur easily that call completing rate is low, roaming is smooth, call drop even do not receive phenomenon such as signal, make troubles for the GSM mobile handset user.This is because traditional gsm wireless repeater is generally simulation at present, its principle is fairly simple, uplink downlink is by active radiofrequency signal amplification module, passive filtering module and simulation frequency-selecting module are formed, its work carrier wave can use after being provided with and needing the people manually to be provided with, base station information source carrier wave configuration need be known in advance can open station work, if information source base station section carrier wave configuration changes and engineers and technicians not at the scene the time in the middle of practical application, will make the work carrier wave of gsm wireless repeater can't obtain upgrading, and then make gsm wireless repeater cisco unity malfunction, cause for the GSM network coverage and have a strong impact on.
This just requires to possess the GSM digital radio repeater equipment that carrier frequency is provided with automatically, make when information source base station section carrier wave configuration parameter changes, the GSM digital radio repeater can upgrade and be provided with the carrier wave configuration parameter automatically, guarantees the normal steady operation of system.And the GSM digital radio repeater can effectively solve this type of problem, it possesses that volume is little, cost is low, easy for installation, be convenient to advantages such as maintenance, become extremely important network optimization means, to improve communication quality, solve the problems such as call drop of weak signal area and blind area, bring great convenience to networking.
[utility model content]
The technical problems to be solved in the utility model is to provide a kind of GSM digital radio repeater that carrier frequency is set automatically, the carrier wave configuration parameter that can make the repeater carrier wave configuration parameter of source base station sector with the letter changes and changes and greatly alleviate the engineering maintenance pressure of repeater, greatly reduce the cost of network operation, guarantee the normal steady operation of system.
The utility model is achieved in that a kind of GSM digital radio repeater that carrier frequency is set automatically, comprises that an alms giver holds duplexer, a descending low noise amplifier, a up low noise amplifier, one first frequency-variable module, a data processing module, one second frequency-variable module, a descending power amplifier, a up power amplifier, to retransmit end duplexer, a monitoring unit and a power subsystem; Described alms giver holds duplexer, descending low noise amplifier, first frequency-variable module, data processing module, second frequency-variable module, descending power amplifier, repeating transmission end duplexer to be connected to down link successively; Described repeating transmission end duplexer, up low noise amplifier, second frequency-variable module, data processing module, first frequency-variable module, up power amplifier, alms giver hold duplexer to be connected to up link successively.
Further, described data processing module comprises that respectively an interconnective MCU unit, a FPGA (Field-Programmable Gate Array field programmable gate array) chip, a clock produce and distribution module, and a descending A/D module that is connected with this fpga chip, MCU unit, clock generating and distribution module respectively, a up A/D module, a descending D/A module, a up D/A module; And described descending A/D module all is connected with described first frequency-variable module with up D/A module; Described descending D/A module all is connected with described second frequency-variable module with up A/D module.
Further, described first frequency-variable module comprises a descending dielectric filter, a descending high linear mixer, descending first intermediate frequency amplifier, a descending intermediate frequency Surface Acoustic Wave Filter, descending second intermediate frequency amplifier that connects successively, and the descending phase-locked loop that is connected with described descending high linear mixer; Described first frequency-variable module also comprises a up intermediate frequency Surface Acoustic Wave Filter, a up intermediate frequency amplifier, a up high linear mixer, up first dielectric filter, a upward signal amplifier, up second dielectric filter that connects successively, and the up phase-locked loop that is connected with described up high linear mixer; Described first frequency-variable module also comprises a CPU who is connected between described descending phase-locked loop and the up phase-locked loop.
Further, described second frequency-variable module comprises a up intermediate frequency Surface Acoustic Wave Filter, a up intermediate frequency amplifier, a up high linear mixer, a up dielectric filter, a upward signal amplifier that connects successively, and the up phase-locked loop that is connected with described up high linear mixer; Described second frequency-variable module also comprises a descending dielectric filter, a descending high linear mixer, descending first intermediate frequency amplifier, a descending intermediate frequency Surface Acoustic Wave Filter, descending second intermediate frequency amplifier that connects successively, and the descending phase-locked loop that is connected with described descending high linear mixer; Described second frequency-variable module also comprises a CPU who is connected between described descending phase-locked loop and the up phase-locked loop.
Further, described descending phase-locked loop and up phase-locked loop all adopt the LMX2531 chip, and this LMX2531 chip integrated chip that is VCO+PLL.
Advantage of the present utility model is: carry out demodulation and channel decoding by the GSM broadcast channel of the powerful FPGA device of data processing module language function after to digitlization, extract the synchronised clock of gsm system time slot, according to the GSM standard standard data are carried out deinterleaving again, deconvolution, computational processes such as CRC, extract this sub-district relevant BCCH frequency and TCH frequency point information at last, thereby make the GSM digital radio repeater can obtain all carrier channels of this sub-district current time number in real time, in case the information source base station section carrier wave configuration equipment of changing can upgrade and be provided with the carrier wave configuration parameter automatically, this technology is utilized the FPGA fast operation and is had the hardware structure of parallel processing capability, handles need not to design numerous and diverse loop control when can be easy to realize to multi-class data.
[description of drawings]
In conjunction with the embodiments the utility model is further described with reference to the accompanying drawings.
Fig. 1 is the theory structure block diagram of the utility model GSM digital radio repeater.
Fig. 2 is the theory structure block diagram of data processing module in the utility model.
Fig. 3 is the theory structure block diagram of first frequency-variable module in the utility model.
Fig. 4 is the theory structure block diagram of second frequency-variable module in the utility model.
Fig. 5 is the utility model GSM digital radio repeater networking mode schematic diagram.
[embodiment]
See also Fig. 1, the GSM digital radio repeater 10 that carrier frequency is set automatically of the present utility model comprises that an alms giver holds duplexer 11, one descending low noise amplifier 21, one up low noise amplifier 22, one first frequency-variable module 3, a data processing module 4, one second frequency-variable module, 5, one descending power amplifier 61, one up power amplifier 62, to retransmit end duplexer 12, a monitoring unit 7 and a power subsystem 8; Described alms giver holds duplexer 11, descending low noise amplifier 21, first frequency-variable module 3, data processing module 4, second frequency-variable module 6, descending power amplifier 61, retransmits and hold duplexer 12 to be connected to down link successively; Described repeating transmission end duplexer 12, up low noise amplifier 22, second frequency-variable module 5, data processing module 4, first frequency-variable module 3, up power amplifier 62, alms giver hold duplexer 11 to be connected to down link successively.Described monitoring unit 7 is in order to monitor the working condition of above-mentioned down link and each unit of down link, and described power subsystem 8 is above-mentioned down link and each unit power supply of down link.
As shown in Figure 2, described data processing module 4 comprises that an interconnective MCU unit 41, a FPGA (Field-Programmable Gate Array field programmable gate array) chip 42, a clock produce and distribution module 43 respectively, and descending A/D module 44, one up A/D module 45, one descending D/A module 46, one a up D/A module 47 that is connected with this MCU unit 41, fpga chip 42, clock generating and distribution module 43 respectively; And described descending A/D module 44 all is connected with described first frequency-variable module 3 with up D/A module 47; Described descending D/A module 46 all is connected with described second frequency-variable module 6 with up A/D module 45.Clock generating and distribution module 43 are responsible for providing reference clock to modules such as descending A/D module 44, up A/D module 45, descending D/A module 46, up D/A module 47 and fpga chips 42, and MCU unit 41 is responsible for each functional unit is carried out data configuration and effective monitoring.
As shown in Figure 3, described first frequency-variable module 3 comprises descending dielectric filter 311, one descending high linear mixer 312, one descending first intermediate frequency amplifier, 313, one descending intermediate frequency Surface Acoustic Wave Filter 314, one descending second intermediate frequency amplifier 315 that connects successively, and the descending phase-locked loop 316 that is connected with described descending high linear mixer 312; Described first frequency-variable module 3 also comprises up intermediate frequency Surface Acoustic Wave Filter 321, one up intermediate frequency amplifier 322, one up high linear mixer 323, one up first dielectric filter 324, a upward signal amplifier 325, one up second dielectric filter 326 that connects successively, and the up phase-locked loop 327 that is connected with described up high linear mixer 323; Described first frequency-variable module 3 also comprises a CPU33 who is connected between described descending phase-locked loop 316 and the up phase-locked loop 327.
As shown in Figure 4, described second frequency-variable module 5 comprises up intermediate frequency Surface Acoustic Wave Filter 511, one up intermediate frequency amplifier 512, one up high linear mixer 513, one a up dielectric filter 514, a upward signal amplifier 515 that connects successively, and the up phase-locked loop 516 that is connected with described up high linear mixer 513; Described second frequency-variable module 5 also comprises descending dielectric filter 521, one descending high linear mixer 522, one descending first intermediate frequency amplifier, 523, one descending intermediate frequency Surface Acoustic Wave Filter 524, one descending second intermediate frequency amplifier 525 that connects successively, and the descending phase-locked loop 526 that is connected with described descending high linear mixer 522; Described second frequency-variable module 5 also comprises a CPU who is connected between described up phase-locked loop 516 and the descending phase-locked loop 526.
Described descending phase-locked loop 316 (526) and up phase-locked loop 327 (516) all adopt the LMX2531 chip, and this LMX2531 chip integrated chip that is VCO+PLL.
As shown in Figure 5, GSM (BTS) base station 20 is transmitted into the overlay area by antenna with this sector base stations signal, to reach weak signal area and signal blind zone are carried out high-quality signal covering, lay GSM digital radio repeater 10 of the present utility model in the boder district of base station coverage cell (being the weak signal zone) strengthening the signal strength signal intensity of former base station, thereby enlarge the area coverage of base station signal.
Extremely shown in Figure 5 in conjunction with Fig. 1, down link: downstream signal holds 11 pairs of descending RF radio frequency unwanted signals of duplexer to carry out Filtering Processing through donor antenna by the alms giver, the descending low noise amplifier 21 of process amplifies the intermediate-freuqncy signal that downconverts to first frequency-variable module 3, but carry out the AD bandpass sampling by 44 pairs of intermediate-freuqncy signals of descending A/D module of digital signal processing module 4 then and reach opereating specification, use the intermediate-freuqncy signal after 42 pairs of digitlizations of fpga chip to carry out base band demodulating again, extract the synchronised clock of gsm system by clock generating and distribution module 43, according to the GSM standard standard data are carried out deinterleaving again, deconvolution, computational processes such as CRC, extract this sub-district relevant BCCH frequency and TCH frequency point information at last, and then calculate base station section carrier wave configuration parameter, downstream signal is through multistage low-pass filtering treatment simultaneously, by descending D/A module 46 it is reverted to intermediate-freuqncy signal again, fade to radiofrequency signal through the up-conversion of second frequency-variable module 5 on it again, last radiofrequency signal is amplified through linear power amplifier and is emitted to the overlay area through duplexer filtering from retransmitting antenna again;
Up link: upward signal is by after retransmitting end duplexer 12 Filtering Processing, the up low noise amplifier 22 of process amplifies the intermediate-freuqncy signal that is down-converted to second frequency-variable module 5, by the up A/D module 45 of digital signal processing module 4 it is carried out the AD bandpass sampling then, intermediate-freuqncy signal after 42 pairs of digitlizations of fpga chip is carried out multistage low-pass filtering treatment again, by up D/A module 47 it is reverted to intermediate-freuqncy signal again, up-conversion through first frequency-variable module 3 returns to radiofrequency signal again, holds duplexer 11 filtering that the GSM upward signal is emitted to base station 20 upward signal receiving terminals from donor antenna through the alms giver again after up power amplifier 62 amplifies.
As previously mentioned, GSM digital radio repeater of the present utility model 10 is owing to can obtain all carrier channels of this sub-district current time number in real time, can working channel be set automatically according to current carrier wave configuration, therefore the equipment work carrier frequency will be consistent constantly with 20 sectors, GSM (BTS) base station, make wireless discharging-directly station possess intelligent functions, can greatly alleviate the engineering maintenance pressure of GSM digital radio repeater 10, greatly reduce the cost of network operation, guarantee the normal steady operation of system.
Claims (5)
1. the GSM digital radio repeater that carrier frequency is set automatically is characterized in that: comprise that an alms giver holds duplexer, a descending low noise amplifier, a up low noise amplifier, one first frequency-variable module, a data processing module, one second frequency-variable module, a descending power amplifier, a up power amplifier, to retransmit end duplexer, a monitoring unit and a power subsystem; Described alms giver holds duplexer, descending low noise amplifier, first frequency-variable module, data processing module, second frequency-variable module, descending power amplifier, repeating transmission end duplexer to be connected to down link successively; Described repeating transmission end duplexer, up low noise amplifier, second frequency-variable module, data processing module, first frequency-variable module, up power amplifier, alms giver hold duplexer to be connected to up link successively.
2. a kind of GSM digital radio repeater that carrier frequency is set automatically as claimed in claim 1, it is characterized in that: described data processing module comprises that respectively an interconnective MCU unit, a fpga chip, a clock produce and distribution module, and a descending A/D module that is connected with this fpga chip, MCU unit, clock generating and distribution module respectively, a up A/D module, a descending D/A module, a up D/A module; And
Described descending A/D module all is connected with described first frequency-variable module with up D/A module;
Described descending D/A module all is connected with described second frequency-variable module with up A/D module.
3. a kind of GSM digital radio repeater that carrier frequency is set automatically as claimed in claim 1 is characterized in that:
Described first frequency-variable module comprises a descending dielectric filter, a descending high linear mixer, descending first intermediate frequency amplifier, a descending intermediate frequency Surface Acoustic Wave Filter, descending second intermediate frequency amplifier that connects successively, and the descending phase-locked loop that is connected with described descending high linear mixer;
Described first frequency-variable module also comprises a up intermediate frequency Surface Acoustic Wave Filter, a up intermediate frequency amplifier, a up high linear mixer, up first dielectric filter, a upward signal amplifier, up second dielectric filter that connects successively, and the up phase-locked loop that is connected with described up high linear mixer;
Described first frequency-variable module also comprises a CPU who is connected between described descending phase-locked loop and the up phase-locked loop.
4. a kind of GSM digital radio repeater that carrier frequency is set automatically as claimed in claim 1 is characterized in that:
Described second frequency-variable module comprises a up intermediate frequency Surface Acoustic Wave Filter, a up intermediate frequency amplifier, a up high linear mixer, a up dielectric filter, a upward signal amplifier that connects successively, and the up phase-locked loop that is connected with described up high linear mixer;
Described second frequency-variable module also comprises a descending dielectric filter, a descending high linear mixer, descending first intermediate frequency amplifier, a descending intermediate frequency Surface Acoustic Wave Filter, descending second intermediate frequency amplifier that connects successively, and the descending phase-locked loop that is connected with described descending high linear mixer;
Described second frequency-variable module also comprises a CPU who is connected between described descending phase-locked loop and the up phase-locked loop.
5. a kind of GSM digital radio repeater that carrier frequency is set automatically as claimed in claim 1, it is characterized in that: described descending phase-locked loop and up phase-locked loop all adopt the LMX2531 chip, and this LMX2531 chip integrated chip that is VCO+PLL.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010202645412U CN201717856U (en) | 2010-07-20 | 2010-07-20 | GSM digital wireless repeater capable of automatically setting carrier frequency |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010202645412U CN201717856U (en) | 2010-07-20 | 2010-07-20 | GSM digital wireless repeater capable of automatically setting carrier frequency |
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| CN201717856U true CN201717856U (en) | 2011-01-19 |
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| CN2010202645412U Expired - Fee Related CN201717856U (en) | 2010-07-20 | 2010-07-20 | GSM digital wireless repeater capable of automatically setting carrier frequency |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291750A (en) * | 2011-09-20 | 2011-12-21 | 华为技术有限公司 | Checking method and device for network configuration parameters |
| CN102711151A (en) * | 2012-05-02 | 2012-10-03 | 京信通信系统（中国）有限公司 | Intelligent digital radio-frequency repeater and control method thereof |
| CN102790640A (en) * | 2012-07-05 | 2012-11-21 | 深圳市华普特科技有限公司 | Field programmable gate array (FPGA) based multi-system, multi-band and multi-carrier digital repeater |
| CN104009764A (en) * | 2013-02-27 | 2014-08-27 | 联想(北京)有限公司 | Signal processing method and electronic equipment |
| CN104519518A (en) * | 2013-09-26 | 2015-04-15 | 北京锐安科技有限公司 | Portable WCDMA (Wideband Code Division Multiple Access) wireless signal field intensity measuring device |
-
2010
- 2010-07-20 CN CN2010202645412U patent/CN201717856U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291750A (en) * | 2011-09-20 | 2011-12-21 | 华为技术有限公司 | Checking method and device for network configuration parameters |
| CN102711151A (en) * | 2012-05-02 | 2012-10-03 | 京信通信系统（中国）有限公司 | Intelligent digital radio-frequency repeater and control method thereof |
| CN102711151B (en) * | 2012-05-02 | 2014-11-12 | 京信通信系统（中国）有限公司 | Control method of intelligent digital radio-frequency repeater and intelligent digital radio-frequency repeater |
| CN102790640A (en) * | 2012-07-05 | 2012-11-21 | 深圳市华普特科技有限公司 | Field programmable gate array (FPGA) based multi-system, multi-band and multi-carrier digital repeater |
| CN102790640B (en) * | 2012-07-05 | 2015-05-06 | 深圳市华普特科技有限公司 | Field programmable gate array (FPGA) based multi-system, multi-band and multi-carrier digital repeater |
| CN104009764A (en) * | 2013-02-27 | 2014-08-27 | 联想(北京)有限公司 | Signal processing method and electronic equipment |
| CN104519518A (en) * | 2013-09-26 | 2015-04-15 | 北京锐安科技有限公司 | Portable WCDMA (Wideband Code Division Multiple Access) wireless signal field intensity measuring device |
| CN104519518B (en) * | 2013-09-26 | 2019-07-30 | 北京锐安科技有限公司 | A kind of portable WCDMA wireless signal field measuring device |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110119 Termination date: 20130720 |