CN201663603U - High-performance monitoring device for reducing hardware realization cost of E-AGCH - Google Patents
High-performance monitoring device for reducing hardware realization cost of E-AGCH Download PDFInfo
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- CN201663603U CN201663603U CN2009201682619U CN200920168261U CN201663603U CN 201663603 U CN201663603 U CN 201663603U CN 2009201682619 U CN2009201682619 U CN 2009201682619U CN 200920168261 U CN200920168261 U CN 200920168261U CN 201663603 U CN201663603 U CN 201663603U
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Abstract
The utility model provides a high-performance monitoring device for reducing the hardware realization cost of an E-AGCH, which comprises a merge output module, a local storage module, a relevant operation module, a numeric value sequencing module, a judging module and a DSP module. Soft bit values with specific length obtained by the merger output module from the E-AGCH and all sequences with specific length locally stored in the local storage module are merged and output to the relevant operation module; after the relevant operation module conducts relevant operation, operation results are transmitted to the numeric value sequencing module; the numeric value sequencing module sequences and averages the operation results and transmits the operation results to the judging module; the judging module transmits numeric values which satisfy judgment conditions to the DSP module; and the DSP module finds out sequence numeric values in all sequences corresponding to the numeric values to obtain bit information which corresponds to the specific length and E-RNT1 to which the sequence numeric values belong, and then transmits the bit information and the E-RNT1 to a high layer protocol stack. The utility model realizes decoding tasks by a small amount of calculation and reaches the effect of hardware simplification.
Description
Technical field
The utility model relates to the high-performance monitoring device of the simplification hardware realization cost of a kind of E-AGCH of being used for.
Background technology
During WCDMA (access of Wideband Code Division Multiple Access Wideband Code Division Multiple Access (WCDMA)) high speed uplink packet inserts, defined an absolute grant channel, carried the information of three classes on it, the absolute grant value information of the first 5 bits, it two is 1 bit absolute grant range information, and it three is by CRC (Cyclical Redundancy Check CRC) part being added the identity identification information that the difference covered is carried.Go up the absolute grant value information and the 1 bit absolute grant range information of 5 bits of carrying at wireless base station NodeB a kind of address of wireless base station (in the WCDMA system to) lining E-AGCH (absolute grant channel of E-DCH Absolute Grant Channel enhancement type special channel), behind process CRC check computing module, obtain the CRC check bit of 16 bits, to use length then be the master of 16 bits or auxilliary E-RNTI (E-DCH Radio Network TemporaryIdentifier network temporary identifier) pursues bit to the CRC check bit of this 16 bit and adds and cover, having formed length altogether is that 22 bit informations carry out chnnel coding, through having obtained length after the convolutional encoding is the encoding block of 90 bits, is left 60 bits by sending through the punching back again.
In terminal UE (User Equipment subscriber equipment) side, generally be to go punching to obtain 90 bit soft values in the existing reception technique to 60 the bit soft value that receives, carry out the decoding of convolution code then, thereby recover the information of transmission.The step of prior art as shown in Figure 1, merge length that output module 1 gets access to E-AGCH and be 60 bit soft value, and should soft value send to matching module 8 and separate rate-matched, fill out 0 on the position of coding back punching in corresponding to NodeB, obtaining length and be 90 sequence sends to viterbi (Viterbi) decoding that decoding module 9 carries out convolution code and handles, to obtain length be 22 bit sequence and send to calibration mode piece 10, two E-RNTI (length is 16) sequence of using DSP (Digital Signal Processor digital signal processor) module 3 to dispose in the verification module 10 by register module 2, back 16 that carry out one by one 22 bits are carried out XOR, to handle the back entire length then is that 22 sequence is sent to the CRC check device, send to DSP module 3 after finishing CRC check, DSP module 3 these sequences of contrast, if the CRC result of two E-RNTI correspondences is wrong, represent that then this information do not issue this UE; If have one right, then expression is a information at this two E-RNTI, with preceding 6 bit informations be that the information of which E-RNTI sends to higher-layer protocols.
Because employed in the decode procedure is (3,1,9) sign indicating number, constraint length is 9, therefore when Viterbi deciphers, 29-1=256 kind state transitions will be arranged,, be equivalent to about needs and do comparison that 256 length is 90 related operation and corresponding number of times and Path selection, back tracking operation in adding of whole Viterbi decoding than selecting in the process.And the result of whole decoding receiving course only is to be the information of main or auxilliary E-RNTI casual network sign for the information that obtains 6 bits altogether and a bit.That is to say that having carried out 256 length for the effective information that obtains 7 bits is 90 related operation, operation efficiency is very low in general.And because calculate, comparing element is many, the hardware that needs realizes that resource is bigger.In addition, traditional in theory Viterbi decoding algorithm is a kind of approximate maximum-likelihood sequence estimation.
The utility model content
The technical problems to be solved in the utility model provides a kind of decoded information that receives and obtains the high-performance checkout gear that the high simplification hardware that is used for E-AGCH of efficient height, decoding performance is realized cost.
In order to address the above problem, the utility model provides the simplification hardware of a kind of E-AGCH of being used for to realize the high-performance monitoring device of cost, comprise: merge output module, local memory module, related operation module, numerical ordering module, judge module and DSP module, wherein:
The bit soft value of the length-specific that described merging output module gets access to from E-AGCH, and should soft value merge and output to described related operation module;
Described local memory module is stored the sequence of all described length-specifics in this locality, and this sequence is sent to described related operation module successively;
Described related operation module receives the data message that described merging output module and described local memory module are sent respectively, and the sequence that all described length-specifics are stored in the bit soft value of the length-specific that described merging output module is sent and this locality that described local memory module is sent carries out related operation, at last this operation result sent to described numerical ordering module;
Described numerical ordering module receives the operation result that described related operation module is sent, and this operation result is sorted with average, and sends to described judge module;
Described judge module receives process ordering and the average numerical value that described numerical ordering module is sent, and after the decision threshold of setting and send to described judge module in this numerical value and the described DSP module compared, the numerical value that will meet judgment condition sent to described DSP module;
Described DSP module receives the numerical value that meets judgment condition that described judge module sends, and according to the sequence index of the maximum correspondence in this numerical value number, find out sequence numerical value corresponding in all sequences with this call number of sequence, obtain the E-RNTI of the bit information corresponding and institute's subordinate thereof at last, and bit information that will this described length-specific correspondence and the E-RNTI of institute's subordinate thereof send to higher-layer protocols with described length-specific.
Further, described related operation module comprise the Data Receiving unit, to preface unit and arithmetic element, wherein:
Described Data Receiving unit is adaptive with described merging output module and described local memory module interface respectively, receive the sequence that all described length-specifics are stored in the bit soft value of the length-specific that described merging output module sends and this locality that described local memory module is sent respectively, send to described in the lump the preface unit;
Described the preface unit is received two groups of data that described Data Receiving unit sends, and send to described arithmetic element after these two groups of data are arranged according to same order is corresponding;
Described arithmetic element receive described to the preface unit send to two groups of data after the preface, and with these two groups of data one by one correspondence carry out related operation, then operation result is transported to described numerical ordering module.
Further, described numerical ordering module comprises Data Receiving allocation units, sequencing unit and average calculation unit, wherein:
Described Data Receiving allocation units receive the operation result that described related operation module is sent, and send to described sequencing unit and described average calculation unit respectively;
Described sequencing unit receives the operation result that described Data Receiving allocation units send, and this operation result is sorted according to numerical values recited, and the maximum after will sorting and second largest value send to described judge module;
Described average calculation unit receives the operation result that described Data Receiving allocation units send, and this operation result value of averaging is calculated, and will calculate the averaging of income value at last and send to described judge module.
The utlity model has following advantage:
1, the utility model adopts local memory module, related operation module and numerical ordering module, can very simply calculate contrast number, and the utility model has just been realized finishing decoding task with low amount of calculation, reaches the effect of simplifying hardware.
2, the utility model adopts related operation module and numerical ordering module, and this computing is simple in structure, reliable, has improved decoding performance greatly.
Below in conjunction with accompanying drawing execution mode of the present utility model is described further:
Fig. 1 shows current decoder operation principle schematic diagram;
Description of drawings
Fig. 2 shows the high-performance monitoring device operation principle schematic diagram of the simplification hardware realization cost of a kind of E-AGCH of being used for of the utility model.
As shown in Figure 2, the utility model comprises merging output module 1, local memory module 4, related operation module 5, numerical ordering module 6, judge module 7 and DSP module 3 wherein:
Merge the bit soft value of the length-specific that output module 1 gets access to from E-AGCH, and should soft value merging output to related operation module 5;
Embodiment
4 li of local memory modules have been preserved the DSP module and have been calculated the sequence of all length-specifics according to two kinds of E-RNTI that issue from high level, and this sequence is sent to related operation module 5 successively;
In the utility model, merging output module 1 is Rake (a kind of energy separating multiple diameter signal and effective receiver that merges the multipath signal energy).
In the utility model, it is 60 sequence (these sequences of depositing are DSP configurations according to higher-layer protocols, calculate) that local memory module 4 has been deposited length corresponding under 128 kinds of possible situations of 7 all bit informations in advance.128 length that local memory module 4 is deposited are that to send to length in the related operation module be that 60 bit soft value carries out related calculation with merging output module 1 successively for 60 sequence, the amount of calculation that needs approximately only be 1/3rd of Viterbi deciphers in the prior art a related operation, and do not had comparison and selection repeatedly and gone punching, CRC check and go the computing of mask operation.Therefore saved amount of calculation greatly.In addition, owing to be to find out the optimum Match person of institute in might sequence, therefore receptivity of the present utility model is equivalent to maximum-likelihood sequence estimation in theory, the processing method deciphered of Viterbi that has been higher than the available technology adopting tradition.
In the utility model, related operation module 5 comprises Data Receiving unit 51, to preface unit 52 and arithmetic element 53, wherein:
In the utility model, numerical ordering module 6 comprises Data Receiving allocation units 61, sequencing unit 62 and average calculation unit 63, wherein:
Data Receiving allocation units 61 receive the operation result that related operation module 5 is sent, and send to sequencing unit 62 and average calculation unit 63 respectively;
In the utility model, the bit soft value length that merging output module 1 gets access to from E-AGCH is 60.Local memory module 4 is 128 in the sequence number of this locality storage, and each sequence length also is 60.
In the utility model, DSP module 3 is very long to the time interval that local memory module 4 sends sequence numerical value, has only when change has taken place Serving cell and just can dispose and carry out once.The time interval of other information calculations and transmission is 2ms or 10ms in the utility model.
In sum; it below only is preferred embodiment of the present utility model; be not to be used to limit protection range of the present utility model; therefore; all any modifications of within spirit of the present utility model and principle, being done, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (3)
1. a simplification hardware that is used for E-AGCH is realized the high-performance monitoring device of cost, it is characterized in that: comprise merging output module (1), local memory module (4), related operation module (5), numerical ordering module (6), judge module (7) and DSP module (3)
The bit soft value of the length-specific that described merging output module (1) gets access to from E-AGCH, and should soft value merge and output to described related operation module (5);
Described local memory module (4) is stored the sequence of all described length-specifics in this locality, and this sequence is sent to described related operation module (5) successively;
Described related operation module (5) receives the data message that described merging output module (1) and described local memory module (4) are sent respectively, and the sequence that all described length-specifics are stored in the bit soft value of the length-specific that described merging output module (1) is sent and this locality that described local memory module (4) is sent carries out related operation, at last this operation result sent to described numerical ordering module (6);
Described numerical ordering module (6) receives the operation result that described related operation module (5) is sent, and this operation result is sorted with average, and sends to described judge module (7);
Described judge module (7) receives process ordering and the average numerical value that described numerical ordering module (6) is sent, and after the decision threshold of setting and send to described judge module (7) in this numerical value and the described DSP module (3) compared, the numerical value that will meet judgment condition sent to described DSP module (3);
Described DSP module (3) receives the numerical value that meets judgment condition that described judge module (7) sends, and according to the sequence index of the maximum correspondence in this numerical value number, find out sequence numerical value corresponding in all sequences with this call number of sequence, obtain the E-RNTI of the bit information corresponding and institute's subordinate thereof at last, and bit information that will this described length-specific correspondence and the E-RNTI of institute's subordinate thereof send to higher-layer protocols with described length-specific.
2. the simplification hardware that is used for E-AGCH as claimed in claim 1 is realized the high-performance monitoring device of cost, it is characterized in that: described related operation module (5) comprises Data Receiving unit (51), to preface unit (52) and arithmetic element (53), wherein,
Described Data Receiving unit (51) is adaptive with described merging output module (1) and described local memory module (4) interface respectively, receive the sequence that all described length-specifics are stored in the bit soft value of the length-specific that described merging output module (1) sends and this locality that described local memory module (4) is sent respectively, send to described in the lump preface unit (52);
Described preface unit (52) are received two groups of data that described Data Receiving unit (51) send, and send to described arithmetic element (53) after these two groups of data are arranged according to same order is corresponding;
Described arithmetic element (53) receive described to preface unit (52) send to two groups of data after the preface, and with these two groups of data one by one correspondence carry out related operation, then operation result is transported to described numerical ordering module (6).
3. the simplification hardware that is used for E-AGCH as claimed in claim 2 is realized the high-performance monitoring device of cost, it is characterized in that: described numerical ordering module (6) comprises Data Receiving allocation units (61), sequencing unit (62) and average calculation unit (63), wherein
Described Data Receiving allocation units (61) receive the operation result that described related operation module (5) is sent, and send to described sequencing unit (62) and described average calculation unit (63) respectively;
Described sequencing unit (62) receives the operation result that described Data Receiving allocation units (61) send, and this operation result is sorted according to numerical values recited, and the maximum after will sorting and second largest value send to described judge module (7);
Described average calculation unit (63) receives the operation result that described Data Receiving allocation units (61) send, and this operation result value of averaging is calculated, and will calculate the averaging of income value at last and send to described judge module (7).
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104617961A (en) * | 2014-12-30 | 2015-05-13 | 中山大学花都产业科技研究院 | Low hardware complexity of interleaver |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104617961A (en) * | 2014-12-30 | 2015-05-13 | 中山大学花都产业科技研究院 | Low hardware complexity of interleaver |
CN104617961B (en) * | 2014-12-30 | 2018-05-25 | 中山大学花都产业科技研究院 | A kind of interleaver of low hardware complexity |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101201 Termination date: 20130902 |