CN201662699U - Control circuit for outputting synchronized signals through Spider 8 data collection system - Google Patents
Control circuit for outputting synchronized signals through Spider 8 data collection system Download PDFInfo
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- CN201662699U CN201662699U CN201020176666XU CN201020176666U CN201662699U CN 201662699 U CN201662699 U CN 201662699U CN 201020176666X U CN201020176666X U CN 201020176666XU CN 201020176666 U CN201020176666 U CN 201020176666U CN 201662699 U CN201662699 U CN 201662699U
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Abstract
The utility model relates to a control circuit for outputting synchronized signals through a Spider 8 data collection system, which comprises a 12-bit binary system counter CD4040, an analog switch CD4051 and a frequency division factor selection socket connector, wherein a 18th lead pin and a 19th lead pin of the Spider 8 data collection system are connected to a 1st pin and a 2nd pin of a circuit board port, the circuit board port is connected with the input end of the binary system counter CD4040, the output end of the binary system counter CD4040 is respectively connected with the analog switch CD4051, the 3-bit selection signal end of the analog switch CD4051 is connected with the frequency division factor selection socket connector, and the output end of the analog switch CD4051 is connected with a synchronized signal output port. The utility model provides the control circuit, which can ensure the sampling precision and synchronization of the data exchange and uses the Spider 8 data collection system for outputting synchronized signals.
Description
Technical field
The utility model relates to the control circuit of Spider8 data acquisition system (DAS) output synchronizing signal.
Background technology
Germany HMB company is with the most famous sensor in the whole world and amplifier manufacturer, the first-selected company during sensors such as at present domestic each Measuring and testing mechanism selection power, moment.Spider8 is the hyperchannel PC data acquisition system (DAS) that is used for Dynamic Data Acquiring that HBM company produces.Each passage of Spider8 all is provided to sensor, amplifier, the excitation of wave filter and the digital to analog converter of oneself.Stable and jamproof carrier wave measuring amplifier makes Spider8 can be applied to power, displacement, pressure and other mechanical value measuring (adopting strain and inductance sensor).For measurement, can 3 line interconnection techniques-3 an optional compensating resistance be provided and shunt demarcation for each passage with strain 1/4 electric bridge.16 digital input and output, and have an external trigger input.Spider8 can expand to 8 passages or 8 Spider8 totally 64 channels.The expansion of 2 embedded module is arranged: one as the CF amplifier, and one as direct current amplifier: adopt electricity independently to export, be applied to thermoelectric occasionally temperature survey or voltage, electric current and the impedance measurement of Pt100.The digital to analog converter energy synchronous operation of all passages of Spider8, each passage calibration is 16bit, speed was for 9600 measurement/seconds to the maximum.The signal of the 9600Hz that Spider8 can provide according to system realizes that by frequency division the sample frequency of many gears selects for the user.
But, if whole measuring system comprises when other can not insert the digital signal of Spider8 such as code device signal etc., perhaps need by other proving installation or capture card (as the Various types of data capture card of NI company), and must and each passage of Spider8 when realizing synchronized sampling Spider8 just have significant limitation.Because Spider8 does not provide the clock signal output identical with inner sample frequency, the external timing signal input that does not also provide frequency to be provided with simultaneously.Owing to lack monolithic clock signal,, but, As time goes on will inevitably cause the confusion of sampled signal owing to the fine difference that exists between the clock source even be arranged to identical sample frequency between the different mining truck.This is fatal problem in the Dynamic High-accuracy acquisition system.
Fig. 1 is the Spider8 back wiring diagram, and wherein 8 15 needle interfaces in left side, 8 passages that are Spider8 are used to connect sensor.25 needle interfaces above middle are " PRINTER/Slave ", are used to connect printer or as the Spider8 of Slave connection group as Master.25 needle interfaces below it are " PC/Master ", and this interface is used to connect computer or as the Spider8 of Master, thereby the Spider8 that connects as Slave realizes many Spider8 series connection.The 18th pin of above-mentioned two interfaces is respectively " Clock out (Synchronization) " and " Clock in (Synchronization) ".The user can think that at first these two pin are as the synchronizing signal input and output, but regrettably these two interfaces are to be specifically designed to be connected with computer or the interface of two Spider8 special use when being connected, the signal frequency of " Clock in (Synchronization) " and " Clockout (Synchronization) " is fixed as 9600Hz, not controlled by the user.Even it is 300Hz that the user is provided with sample frequency, " Clock out (Synchronization) " output signal still is 9600Hz, i.e. the highest sample frequency of system, and user-selected divide ratio is inoperative to this port.The HBM company clock signal output function that also do not provide exportable user to select sample frequency simultaneously.
Summary of the invention
Poor synchronization, deficiency that precision is low when overcoming existing Spider8 data acquisition system (DAS) and other proving installations or capture card swap data, the utility model provide a kind of control circuit with Spider8 data acquisition system (DAS) output synchronizing signal of the sampling precise synchronization can guarantee exchanges data the time.
The technical scheme that proposes in order to solve the problems of the technologies described above is:
A kind of control circuit with Spider8 data acquisition system (DAS) output synchronizing signal, comprise 12 binary counter CD4040, analog switch CD4051 and divide ratio are selected connector, the 1st of the 18th pin of Spider8 data acquisition system (DAS) and the 19th pin connection line plate port, 2 pin, described wiring board port connects the input end of described binary counter CD4040, the output terminal of described binary counter CD4040 connects analog switch CD4051 respectively, select signal end and divide ratio to select connector to be connected for three of described analog switch CD4051, the output terminal of described analog switch CD4051 connects the synchronous signal output end mouth.
Further, there is " DigitalI/O " interface of one 25 pin on " PC/Master " interface right side of described Spider8, and the 13rd pin, 25 pin and 12 pin of described " Digital I/O " interface select the synchronizing signal divide ratio option interface of connector to be connected with divide ratio.
The utility model is a switching value signal output function of utilizing " Clock out (Synchronization) " signal that Spider8 provides and Spider8 to provide, the circuit of simplicity of design is realized the controlled sample-synchronous signal output function of user, thereby satisfies the synchronized sampling function between Spider8 and other data acquisition system (DAS).
The frequency dividing circuit realization, as shown in Figure 2.J1 input 9600Hz signal, frequency division effect through 12 2 system counter CD4040, Q1 to Q7 exports 9600Hz, 4800Hz, 2400Hz, 1200Hz, 600Hz, 300Hz, 150Hz signal respectively, J3 is that divide ratio is selected connector, connect analog switch CD4051, can perhaps can directly realize fractional frequency signal output selection by external control by wire jumper.The CD4051 input signal selects 000 to 110 pair of signal of signal to select by 3, is no signal output in 111 o'clock.Connector J2 output frequency division signal.
" Digital I/O " interface that one 25 pin is arranged on Spider8 " PC/Master " interface right side.Utilize the 13rd pin (Output0), 25 pin (Output1) and 12 pin (Output2) of this mouthful to select as the synchronizing signal divide ratio.The user is according to the sample frequency of the Spider8 that has selected, and promptly divide ratio is controlled the frequency division of the signal output realization of this mouthful to 9600Hz " Clock out " signal, realizes the synchronous fully of sampled signal thereby export other acquisition system then to.
Technique effect of the present utility model is: the sampling precise synchronization in the time of can guaranteeing exchanges data.
Description of drawings
Fig. 1 is the wiring diagram of Spider8 data acquisition system (DAS).
Fig. 2 is the circuit diagram with the control circuit of Spider8 data acquisition system (DAS) output synchronizing signal.
Embodiment
Below in conjunction with accompanying drawing the utility model is further described.
See figures.1.and.2, a kind of control circuit with Spider8 data acquisition system (DAS) output synchronizing signal, comprise 12 binary counter CD4040, analog switch CD4051 and divide ratio are selected connector, the 1st of the 18th pin of Spider8 data acquisition system (DAS) and the 19th pin connection line plate port, 2 pin, described wiring board port connects the input end of described binary counter CD4040, the output terminal of described binary counter CD4040 connects analog switch CD4051 respectively, select signal end and divide ratio to select connector to be connected for three of described analog switch CD4051, the output terminal of described analog switch CD4051 connects the synchronous signal output end mouth.
There is " Digital I/O " interface of one 25 pin on " PC/Master " interface right side of described Spider8, and the 13rd pin, 25 pin and 12 pin of described " Digital I/O " interface select the synchronizing signal divide ratio option interface of connector to be connected with divide ratio.
The frequency dividing circuit realization, as shown in Figure 2.J1 input 9600Hz signal, frequency division effect through 12 2 system counter CD4040, Q1 to Q7 exports 9600Hz, 4800Hz, 2400Hz, 1200Hz, 600Hz, 300Hz, 150Hz signal respectively, J3 is that divide ratio is selected connector, connect analog switch CD4051, can perhaps can directly realize fractional frequency signal output selection by external control by wire jumper.The CD4051 input signal selects 000 to 110 pair of signal of signal to select by 3, is no signal output in 111 o'clock.Connector J2 output frequency division signal.
" Digital I/O " interface that one 25 pin is arranged on Spider8 " PC/Master " interface right side.Utilize the 13rd pin (Output0), 25 pin (Output1) and 12 pin (Output2) of this mouthful to select as the synchronizing signal divide ratio.The user is according to the sample frequency of the Spider8 that has selected, and promptly divide ratio is controlled the frequency division of the signal output realization of this mouthful to 9600Hz " Clock out " signal, realizes the synchronous fully of sampled signal thereby export other acquisition system then to.
Implementation: " PRINTER/Slave " the 18th pin (" Clock out ") and the 19th pin (" Ground ") are connected to the 1st, 2 pin of wiring board port " J1 ".
" PC/Master " the 1st pin (" VCC "), the 13rd pin (Output0), 25 pin (Output1), 12 pin (Output2) and the 2nd pin (" Ground ") are connected to the 1st to 5 pin of wiring board port " J3 ".
The synchronizing signal that " J2 " port output user of wiring board selects.
Claims (2)
1. control circuit with Spider8 data acquisition system (DAS) output synchronizing signal, it is characterized in that: described control circuit comprises 12 binary counter CD4040, analog switch CD4051 and divide ratio are selected connector, the 1st of the 18th pin of Spider8 data acquisition system (DAS) and the 19th pin connection line plate port, 2 pin, described wiring board port connects the input end of described binary counter CD4040, the output terminal of described binary counter CD4040 connects analog switch CD4051 respectively, select signal end and divide ratio to select connector to be connected for three of described analog switch CD4051, the output terminal of described analog switch CD4051 connects the synchronous signal output end mouth.
2. the control circuit with Spider8 data acquisition system (DAS) output synchronizing signal as claimed in claim 1, it is characterized in that: there is " Digital I/O " interface of one 25 pin on " PC/Master " interface right side of described Spider8, and the 13rd pin, 25 pin and 12 pin of described " Digital I/O " interface select the synchronizing signal divide ratio option interface of connector to be connected with divide ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020176666XU CN201662699U (en) | 2010-04-30 | 2010-04-30 | Control circuit for outputting synchronized signals through Spider 8 data collection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020176666XU CN201662699U (en) | 2010-04-30 | 2010-04-30 | Control circuit for outputting synchronized signals through Spider 8 data collection system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201662699U true CN201662699U (en) | 2010-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201020176666XU Expired - Fee Related CN201662699U (en) | 2010-04-30 | 2010-04-30 | Control circuit for outputting synchronized signals through Spider 8 data collection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201662699U (en) |
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2010
- 2010-04-30 CN CN201020176666XU patent/CN201662699U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101201 Termination date: 20130430 |