CN201623050U - 基岛露出芯片正装倒t型散热块全包覆封装结构 - Google Patents

基岛露出芯片正装倒t型散热块全包覆封装结构 Download PDF

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CN201623050U
CN201623050U CN 201020117652 CN201020117652U CN201623050U CN 201623050 U CN201623050 U CN 201623050U CN 201020117652 CN201020117652 CN 201020117652 CN 201020117652 U CN201020117652 U CN 201020117652U CN 201623050 U CN201623050 U CN 201623050U
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heat sink
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

本实用新型涉及一种基岛露出芯片正装倒T型散热块全包覆封装结构，包含有芯片(3)、芯片下方的所承载的金属基岛(1)、金属内脚(4)、芯片到金属内脚的信号互连的金属丝(5)、芯片与金属基岛之间的导电或不导电的导热粘结物质I(2)和塑封体(8)，所述金属基岛(1)露出塑封体(8)，其特征在于在所述芯片(3)上方设置有散热块(7)，该散热块(7)与所述芯片(3)之间嵌置有导电或不导电的导热粘结物质II(6)；该散热块(7)被完全包覆在所述塑封体(8)内；该散热块(7)呈倒置的“T”型结构。本实用新型通过在芯片上方增置散热块，来担任高热量的散热的功能，能够提供散热的能力强，使芯片的热量能快速的传导到封装体外界。避免了芯片的寿命快速老化甚至烧伤或烧坏。

Description

基岛露出芯片正装倒T型散热块全包覆封装结构
(一)技术领域
本实用新型涉及一种基岛露出芯片正装倒T型散热块全包覆封装结构。属于半导体封装技术领域。
(二)背景技术
传统的芯片封装形式的散热方式，主要是采用了芯片下方的金属基岛作为散热传导工具或途径，而这种传统封装方式的散热传导存在以下的不足点：
1、金属基岛体积太小
金属基岛在传统封装形式中，为了追求封装体的可靠性安全，几乎都采用了金属基岛埋入在封装体内，而在有限的封装体内，同时要埋入金属基岛及信号、电源传导用的金属内脚(如图1及图2所示)，所以金属基岛的有效面积与体积就显得非常的小，而同时金属基岛还要来担任高热量的散热的功能，就会显得更为的不足了。
2、埋入型金属基岛(如图1及图2所示)
金属基岛在传统封装形式中，为了追求封装体的可靠性安全，几乎都采用了金属基岛埋入在封装体内，而金属基岛是依靠左右或是四个角落细细的支撑杆来固定或支撑金属基岛，也因为这细细的支撑杆的特性，导致了金属基岛从芯片上所吸收到的热量，无法快速的从细细的支撑杆传导出来，所以芯片的热量无法或快速的传导到封装体外界，导致了芯片的寿命快速老化甚至烧伤或烧坏。
3、金属基岛露出型(如图3及图4所示)
虽然金属基岛是露出的，可以提供比埋入型的散热功能还要好的散热能力，但是因为金属基岛的体积及面积在封装体内还是非常的小，所以能够提供散热的能力，还是非常有限。
(三)发明内容
本实用新型的目的在于克服上述不足，提供一种能够提供散热的能力强的基岛露出芯片正装倒T型散热块全包覆封装结构。
本实用新型的目的是这样实现的：一种基岛露出芯片正装倒T型散热块全包覆封装结构，包含有芯片、芯片下方的所承载的金属基岛、金属内脚、芯片到金属内脚的信号互连的金属丝、芯片与金属基岛之间的导电或不导电的导热粘结物质I和塑封体，所述金属基岛露出塑封体，其特征在于在所述芯片上方设置有散热块，该散热块与所述芯片之间嵌置有导电或不导电的导热粘结物质II；该散热块被完全包覆在所述塑封体内；该散热块呈倒置的“T”型结构。
本实用新型的有益效果是：
本实用新型通过在芯片上方增置散热块，来担任高热量的散热的功能，能够提供散热的能力强，使芯片的热量能快速的传导到封装体外界。可以应用在一般的封装形式的封装体及封装工艺上使其成为高或是超高散热(High Thermal or Super High Thermal)能力，如FBP可以成为SHT-FBP/QFN可以成为SHT-QFN/BGA可以成为SHT-BGA/CSP可以成为SHT-CSP……。避免了芯片的寿命快速老化甚至烧伤或烧坏。
(四)附图说明
图1为以往金属基岛埋入型芯片封装结构示意图。
图2为图1的俯视图。
图3为以往金属基岛露出型芯片封装结构示意图。
图4为图3的俯视图。
图5为本实用新型基岛露出芯片正装倒T型散热块全包覆封装结构示意图。
图中附图标记：
金属基岛1、导电或不导电的导热粘结物质I 2、芯片3、金属内脚4、金属丝5、导电或不导电的导热粘结物质II 6、散热块7、塑封体8。
(五)具体实施方式
参见图5，图5为本实用新型基岛露出芯片正装倒T型散热块全包覆封装结构示意图。由图5可以看出，本实用新型基岛露出芯片正装倒T型散热块全包覆封装结构，包含有芯片3、芯片下方的所承载的金属基岛1、金属内脚4、芯片到金属内脚的信号互连的金属丝5、芯片与金属基岛之间的导电或不导电的导热粘结物质I 2和塑封体8，所述金属基岛1露出塑封体8，在所述芯片3上方设置有散热块7，该散热块7与所述芯片3之间嵌置有导电或不导电的导热粘结物质II 6；该散热块7被完全包覆在所述塑封体8内；该散热块7呈倒置的“T”型结构。
所述散热块7的材质可以是铜、铝、陶瓷或合金等。

Claims (2)

1.一种基岛露出芯片正装倒T型散热块全包覆封装结构，包含有芯片(3)、芯片下方的所承载的金属基岛(1)、金属内脚(4)、芯片到金属内脚的信号互连的金属丝(5)、芯片与金属基岛之间的导电或不导电的导热粘结物质I(2)和塑封体(8)，所述金属基岛(1)露出塑封体(8)，其特征在于在所述芯片(3)上方设置有散热块(7)，该散热块(7)与所述芯片(3)之间嵌置有导电或不导电的导热粘结物质II(6)；该散热块(7)被完全包覆在所述塑封体(8)内；该散热块(7)呈倒置的“T”型结构。
2.根据权利要求1所述的一种基岛露出芯片正装倒T型散热块全包覆封装结构，其特征在于所述散热块(7)的材质是铜、铝、陶瓷或合金。
CN 201020117652 2010-01-26 2010-01-26 基岛露出芯片正装倒t型散热块全包覆封装结构 Expired - Fee Related CN201623050U (zh)

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