CN201601675U - Small-sized satellite beacon receiver - Google Patents
Small-sized satellite beacon receiver Download PDFInfo
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- CN201601675U CN201601675U CN2009202827668U CN200920282766U CN201601675U CN 201601675 U CN201601675 U CN 201601675U CN 2009202827668 U CN2009202827668 U CN 2009202827668U CN 200920282766 U CN200920282766 U CN 200920282766U CN 201601675 U CN201601675 U CN 201601675U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The utility model relates to a small-sized satellite beacon receiver, comprising a beacon signal input processing unit, a digitization unit and a control signal output unit; after the beacon signal input processing unit processes a satellite signal received by a tuner, the signal is digitized by the digitization unit to obtain an output control signal, and after the output control signal is amplified, an automatic gain control signal needed by outputting is obtained. The digitization unit comprises an A/D conversion circuit, an MCU1 microprocessor, a memory unit and a D/A conversion circuit; the signal from the beacon signal input processing unit is introduced to the MCU1 through the A/D conversion circuit, the MCU1 outputs a digitization control signal according to the input signal, and then the digitization control signal outputs an analog control signal through the D/A conversion circuit, and the MCU is connected with the memory unit, thereby ensuring relevant parameter such as power-down storage frequency point and the like.
Description
Technical field
The utility model belongs to wireless communication technology field, specifically is a kind of miniaturization satellite beacon receiver.
Background technology
Beacon receiver is used for the total motion tracking system of satellite communication earth station.Its task is to catch the beacon signal that synchronous satellite sends, and to its down-conversion, be transformed into intermediate-freuqncy signal, detect the direct voltage that is directly proportional with beacon signal intensity then, provide the relative and antenna pairing signal strength signal intensity voltage when the different angles position of satellite beacon signals (being target), give with the direct voltage form and to raise the clothes control system, thus finish antenna to satellite from motion tracking.But in the prior art, Radio Beacon all is not well solved to the identification of relevant parameter power down preservations such as frequency, beacon signal and miniaturization portability etc.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the utility model proposes a kind of miniaturization satellite beacon receiver, concrete technical scheme is as follows:
A kind of miniaturization satellite beacon receiver, comprise beacon signal input processing unit, digital unit and control signal output unit, after the satellite-signal that described beacon signal input processing unit receives tuner is handled, obtain exporting control signal again after digital unit carries out digitlization, this output control signal obtains exporting required automatic gaining controling signal after amplifying.Described digital unit comprises A/D change-over circuit, MCU1 microprocessor, memory cell and D/A change-over circuit, described signal from the beacon signal input processing unit imports MCU1 into behind the A/D change-over circuit, MCU1 exports digital controlled signal according to input signal, and this digital controlled signal is exported analog control signal behind the D/A change-over circuit; Described MCU is connected with memory cell.Can guarantee relevant parameters such as power down preservation frequency like this.
Described beacon signal input processing unit comprises RF circuit part, local oscillator LO1 and local oscillator LO2 circuit part; The RF circuit part comprises an intermediate-freuqncy signal generation unit, two intermediate-freuqncy signal generation units and d. c. voltage signal generation unit; The output one intermediate-freuqncy signal satellite-signal that described tuner receives carries out down-converted with the local oscillation signal of local oscillator LO1 circuit part in an intermediate-freuqncy signal generation unit after; Output two intermediate-freuqncy signals this intermediate-freuqncy signal is carried out down-converted with the local oscillation signal of local oscillator LO2 circuit part in two intermediate-freuqncy signal generation units after; This two intermediate-freuqncy signal obtains the d. c. voltage signal that is directly proportional with described two intermediate-freuqncy signal amplitudes after the d. c. voltage signal generation unit is handled.
A described intermediate-freuqncy signal is the point-frequency signal of 831.08MHZ, and two intermediate-freuqncy signals are the intermediate-freuqncy signal commonly used of 21.4MHZ.
A described intermediate-freuqncy signal generation unit comprises Z1 coupling equalizing circuit, A1 one-level radio frequency amplifier, Z2 coupling equalizing circuit, A2 secondary radio frequency amplifier, Z3 coupling equalizing circuit and the MIX1 frequency mixer that connects successively; The local oscillator LO1 signal of described local oscillator LO1 circuit part imports this MIX1 frequency mixer into.
Described two intermediate-freuqncy signal generation units comprise F1 one-level one intermediate-frequency filter, A3 one intermediate frequency amplifier, F2 secondary one intermediate-frequency filter and the MIX2 frequency mixer that connects successively; The local oscillator LO2 signal of described local oscillator LO2 circuit part imports this MIX2 frequency mixer into.
The d. c. voltage signal generation unit comprises F3 one-level two intermediate-frequency filters, A4 one-level two intermediate frequency amplifiers, Z4 coupling equalizing circuit, A5 secondary two intermediate frequency amplifiers, F3 secondary two intermediate-frequency filters and the D1 wave detector that connects successively.
Described local oscillator LO1 circuit part comprises vibration magnifier of VCO1 voltage controlled oscillator, A7 and the Z5 coupling equalizing circuit that connects successively, and the input of described VCO1 also is connected with the first control voltage generation circuit; Described Z5 coupling equalizing circuit is by path capacitance, to earth resistance and power splitter, and power splitter is carrying out not waiting the merit branch through path capacitance and the signal after the earth resistance processing, obtains main signal and from signal, main signal is exported as local oscillator LO1 signal;
The described first control voltage generation circuit comprises MCU2 microprocessor, PD1 phase discriminator, F5 active power filtering amplifier and standard oscillator signal source circuit; Describedly import the PD1 phase discriminator into, and under the control of MCU2, carry out than mutually with signal from standard oscillator signal source circuit from signal; The control signal of PD1 output enters F5 amplifies, and sends into VCO1 at last as control voltage;
Standard oscillator signal source circuit in the first control voltage generation circuit comprises C1 crystal oscillating circuit and DDS1 Direct Digital Frequency Synthesizers; The oscillator signal of C1 crystal oscillating circuit output imports in the DDS1 Direct Digital Frequency Synthesizers after filtering is amplified, and generates reference signal under the control of described MCU1, and this reference signal is output after filtering is amplified; The input of described MCU1 also is connected with the external control unit, for example PC control or PC control etc.
Described local oscillator LO2 circuit part comprises two vibration magnifiers of VCO2 voltage controlled oscillator, A10 and the Z6 coupling equalizing circuit that connects successively, and the input of described VCO2 also is connected with the second control voltage generation circuit; Described Z6 coupling equalizing circuit is by path capacitance, to earth resistance and power splitter, and power splitter is carrying out not waiting the merit branch through path capacitance and the signal after the earth resistance processing, obtains main signal and from signal, main signal is exported as local oscillator LO2 signal;
The described second control voltage generation circuit comprises MCU3 microprocessor, PD2 phase discriminator, F10 active power filtering amplifier and standard oscillator signal source circuit; Describedly import the PD2 phase discriminator into from signal, described standard source oscillation signal circuit output signal also imports PD2 into, and carries out under the control of MCU3 than phase; The control signal of PD2 output enters F10 amplifies, and sends into VCO2 at last as control voltage.
The standard oscillator signal source circuit of the described second control voltage generation circuit is the C1 crystal oscillating circuit in the described first control voltage generation circuit.
But the utlity model has power down preserve the function of the function identification beacon signal of frequency, anti-interference height, good linearity, highly sensitive, response speed is fast and low in energy consumption, size is little, advantage such as in light weight.
Description of drawings
Fig. 1 is a theory diagram of the present utility model;
Fig. 2 is the signal path principle schematic of this receiver among the embodiment;
Fig. 3 is the local oscillator LO1 circuit part principle schematic of this receiver among the embodiment;
Fig. 4 is the local oscillator LO2 circuit part principle schematic of this receiver among the embodiment.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing and embodiment.
As Fig. 1, a kind of miniaturization satellite beacon receiver, comprise beacon signal input processing unit, digital unit and control signal output unit, after the satellite-signal that described beacon signal input processing unit receives tuner is handled, obtain exporting control signal again after digital unit carries out digitlization, this output control signal obtains exporting required automatic gaining controling signal after amplifying.Described digital unit comprises A/D change-over circuit, MCU1 microprocessor, memory cell and D/A change-over circuit, described signal from the beacon signal input processing unit imports MCU1 into behind the A/D change-over circuit, MCU1 exports digital controlled signal according to input signal, and this digital controlled signal is exported analog control signal behind the D/A change-over circuit; Described MCU is connected with memory cell.In this example, specify as follows:
One, RF circuit part
1, signal path schematic circuit explanation (as Fig. 2)
The satellite-signal of the 950-1750MHZ that gets off from LNB enters the RF circuit,
Earlier through Z1 coupling equalizing circuit, Z1 is made up of to earth resistance a path capacitance and one, and the value by control capacittance and resistance makes the signal flatness of 950-1750MHZ reach desired value and takes into account impedance matching simultaneously; The RF signal that advanced balanced coupling enters the A1 amplifier and amplifies about 15dB, and A1 is the ERA-8SM or the ERA-5SM of MINI company; Signal after amplifying enters Z2 and carries out equilibrium and coupling (Z2 is identical with the Z1 circuit form), makes its signal smooth, and satisfies the standing wave requirement; Entering A2 after Z2 comes out again carries out entering Z3 then and carrying out again balanced and coupling (Z3 is identical with the Z1 circuit form) about secondary amplification 15dB (A2 is identical with A1); Treated afterwards 950-1750MHZ signal enters the MIX1 frequency mixer and carries out down-conversion (MIX1 is the EMRS-25MH frequency mixing module of MINI company) from the local oscillation signal (signal of LO1 is any variable signal of 1781.08～2581.08MHZ) of LO1, exports the point-frequency signal that an intermediate-freuqncy signal is 831.08MHZ;
This signal enters F1 first intermediate-frequency filter after MIX1 frequency mixer output carries out filtering (F1 is a NDF8082 type Surface Acoustic Wave Filter,), spurious signal outside the filtering 831.08MHZ, enter A3 through the filtered intermediate-freuqncy signal of F1 and amplify (A3 is the ERA-8SM amplification module of MINI company) about 22dB, intermediate-freuqncy signal after A3 amplifies enters F2 again and carries out secondary filtering (F2 is identical with F1), the spurious signal outside the filtering 831.08MHZ; Amplify an intermediate frequency 831.08MHZ signal after the filtering again through filtering and enter MIX2 (MIX2 is the HMC207S8 frequency mixing module of HITTITE company) and carry out down-conversion with the signal that comes from the two local oscillator 852.48MHZ of LO2, exporting two intermediate-freuqncy signals is the intermediate-freuqncy signal commonly used of 21.4MHZ;
Two intermediate-freuqncy signals of MIX2 frequency mixer output enter other signals outside F3 (F3 is the separate type crystal filter of 21.4MHZ) the filtering 21.4MHZ, enter A4 (A4 is identical with A3) through filtered two intermediate-freuqncy signals of F3, amplify about 25dB, entering Z4 (Z4 is identical with the Z1 circuit form) then mates and gain-adjusted, entering A5 (A5 is identical with A3) afterwards again amplifies about 25dB again, two intermediate-freuqncy signals after A5 amplifies enter F4 (F4 is identical with F3) and carry out filtering, other signals outside the filtering 21.4; Entering D1 wave detector (D1 is the AD8310 detection amplification module of ADI company) through two intermediate-freuqncy signals of F4 output carries out detection and amplifies the d. c. voltage signal that output is directly proportional with the two intermediate-freuqncy signal amplitudes of input;
Direct current signal after the D1 output enters MCU1 (MCU1 is the C8051F330 of dragon company of Xinhua), carry out A/D and be transformed into digital signal, carry out carrying out D/A again after the Digital Signal Processing then and be transformed into the analog DC voltage signal, export A6 (A6 is the LM2904 dc operational amplifier of state half) afterwards to and carry out the direct current amplification, make its direct voltage be amplified to desired value, this direct voltage exports external tapping at last.
Two, LO1 and LO2 circuit part
1, LO1 circuit description (as Fig. 3)
The signal of VCO1 (VCO1 is the V600ME10 type voltage controlled oscillator of Z-COMM company) exports A7 (A7 is the ERA-5SM of MINI company) to and is amplified to that to make its power output be about 15dBm, (three resistance are formed star-like power splitter to enter Z5 then, path capacitance with mate with balanced to earth resistance) mate the balanced merit that do not wait and divide main signal afterwards to export the LO port of MIX1 to, another road exports the 6th pin of PD1 (PD1 is the ADF4113 digital frequency synthesizer of ADI company) frequency synthesizer to; The stabilization signal of the 30.72MHZ of C1 (crystal oscillator of 30.72MHZ) output is through the harmonic signal of F8 (LC low pass filter) filtering 30.72MHZ, entering A9 (A9 is identical with A3) then amplifies, make its power output greater than 0dBm, enter F9 (manying the LC low pass filter of one-level) afterwards again and carry out filtering than F8, the harmonic signal of filtering 30.72MHZ, filtered 30.72MHZ signal merit divides two-way to enter the 9th pin of DDS1 (DDS1 is the AD9850 Direct Digital Frequency Synthesizers of ADI company), as the reference signal of DDS1, another road enters 8 pin of PD2; MCU1 passes to DDS1 after receiving frequency instruction that the user sends and it being changed into the instruction of control DDS1, make any reference signal of DDS1 output 1-20MHZ, reference signal enters F6 (LC low pass filter) and carries out filtering, other signals that filtering 7MHZ is above, enter A8 (with A3) then and amplify 20dB, make its output signal greater than 0dBm, enter F7 (manying the LC low pass filter of one-level) other above signals of filtering 7MHZ once more afterwards than F6, last reference signal enters the 8th pin of PD1 frequency synthesizer, under the control of MCU2 (PIC12F508A single-chip microcomputer), carry out than mutually with LO1 signal from Z5, the control signal of PD1 output enters F5 (the active power filtering amplifier that OP07 amplifier and RC low pass filter constitute) carry out the active power filtering amplification after, export the VT end of VCO1 to, make VCO1 export a stable LO1 signal.
2, LO2 circuit description (as Fig. 4)
The signal of VCO2 (voltage controlled oscillator that ATF-41586 and LC form) output enters A10 (A10 and A3 are identical) and is amplified to that to make its power output be about 13dBm, (three resistance are formed star-like power splitter to enter Z6 then, path capacitance with mate with balanced to earth resistance) mate the balanced merit that do not wait and divide main signal afterwards to export the LO port of MIX2 to, another road exports the 5th pin of PD2 (PD2 is the ADF4113 digital frequency synthesizer of ADI company) frequency synthesizer to; Enter the 8th pin of PD2 from the reference signal of the 30.72MHZ of C1, under the control of MCU3, carry out than phase, the control signal of PD2 output enters F10 (the active power filtering amplifier that OP07 amplifier and RC low pass filter constitute) carry out the active power filtering amplification after, export the VT end of VCO2 to, make VCO2 export a stable LO2 signal.
Claims (10)
1. miniaturization satellite beacon receiver, comprise the beacon signal input processing unit, digital unit and control signal output unit, after the satellite-signal that described beacon signal input processing unit receives tuner is handled, after carrying out digitlization, digital unit obtains exporting control signal again, this output control signal obtains exporting required automatic gaining controling signal after amplifying, it is characterized in that described digital unit comprises the A/D change-over circuit, the MCU1 microprocessor, memory cell and D/A change-over circuit, described signal from the beacon signal input processing unit imports MCU1 into behind the A/D change-over circuit, MCU1 exports digital controlled signal according to input signal, and this digital controlled signal is exported analog control signal behind the D/A change-over circuit; Described MCU is connected with memory cell.
2. miniaturization satellite beacon receiver according to claim 1 is characterized in that described beacon signal input processing unit comprises RF circuit part, local oscillator LO1 and local oscillator LO2 circuit part; The RF circuit part comprises an intermediate-freuqncy signal generation unit, two intermediate-freuqncy signal generation units and d. c. voltage signal generation unit; The output one intermediate-freuqncy signal satellite-signal that described tuner receives carries out down-converted with the local oscillation signal of local oscillator LO1 circuit part in an intermediate-freuqncy signal generation unit after; Output two intermediate-freuqncy signals this intermediate-freuqncy signal is carried out down-converted with the local oscillation signal of local oscillator LO2 circuit part in two intermediate-freuqncy signal generation units after; This two intermediate-freuqncy signal obtains the d. c. voltage signal that is directly proportional with described two intermediate-freuqncy signal amplitudes after the d. c. voltage signal generation unit is handled.
3. miniaturization satellite beacon receiver according to claim 2 is characterized in that a described intermediate-freuqncy signal is the point-frequency signal of 831.08MHZ, and two intermediate-freuqncy signals are the intermediate-freuqncy signal commonly used of 21.4MHZ.
4. according to claim 2 or 3 described miniaturization satellite beacon receivers, it is characterized in that a described intermediate-freuqncy signal generation unit comprises Z1 coupling equalizing circuit, A1 one-level radio frequency amplifier, Z2 coupling equalizing circuit, A2 secondary radio frequency amplifier, Z3 coupling equalizing circuit and the MIX1 frequency mixer that connects successively; The local oscillator LO1 signal of described local oscillator LO1 circuit part imports this MIX1 frequency mixer into.
5. miniaturization satellite beacon receiver according to claim 4 is characterized in that described two intermediate-freuqncy signal generation units comprise F1 one-level one intermediate-frequency filter, A3 one intermediate frequency amplifier, F2 secondary one intermediate-frequency filter and the MIX2 frequency mixer that connects successively; The local oscillator LO2 signal of described local oscillator LO2 circuit part imports this MIX2 frequency mixer into.
6. according to claim 2 or 3 described miniaturization satellite beacon receivers, it is characterized in that the d. c. voltage signal generation unit comprises F3 one-level two intermediate-frequency filters, A4 one-level two intermediate frequency amplifiers, Z4 coupling equalizing circuit, A5 secondary two intermediate frequency amplifiers, F3 secondary two intermediate-frequency filters and the D1 wave detector that connects successively.
7. miniaturization satellite beacon receiver according to claim 5, it is characterized in that described local oscillator LO1 circuit part comprises vibration magnifier of VCO1 voltage controlled oscillator, A7 and the Z5 coupling equalizing circuit that connects successively, the input of described VCO1 also is connected with the first control voltage generation circuit; Described Z5 coupling equalizing circuit is by path capacitance, to earth resistance and power splitter, and power splitter is carrying out not waiting attacking branch through path capacitance and the signal after the earth resistance processing, obtains main signal and from signal, main signal is exported as local oscillator LO1 signal;
The described first control voltage generation circuit comprises MCU2 microprocessor, PD1 phase discriminator, F5 active power filtering amplifier and standard oscillator signal source circuit; Describedly import the PD1 phase discriminator into, and under the control of MCU2, carry out than mutually with signal from standard oscillator signal source circuit from signal; The control signal of PD1 output enters F5 amplifies, and sends into VCO1 at last as control voltage;
8. miniaturization satellite beacon receiver according to claim 7 is characterized in that the standard oscillator signal source circuit in the first control voltage generation circuit comprises C1 crystal oscillating circuit and DDS1 Direct Digital Frequency Synthesizers; The oscillator signal of C1 crystal oscillating circuit output imports in the DDS1 Direct Digital Frequency Synthesizers after filtering is amplified, and generates reference signal under the control of described MCU1, and this reference signal is output after filtering is amplified; The input of described MCU1 also is connected with the external control unit.
9. miniaturization satellite beacon receiver according to claim 8, it is characterized in that described local oscillator LO2 circuit part comprises two vibration magnifiers of VCO2 voltage controlled oscillator, A10 and the Z6 coupling equalizing circuit that connects successively, the input of described VCO2 also is connected with the second control voltage generation circuit; Described Z6 coupling equalizing circuit is by path capacitance, to earth resistance and power splitter, and power splitter is carrying out not waiting the merit branch through path capacitance and the signal after the earth resistance processing, obtains main signal and from signal, main signal is exported as local oscillator LO2 signal;
The described second control voltage generation circuit comprises MCU3 microprocessor, PD2 phase discriminator, F10 active power filtering amplifier and standard oscillator signal source circuit; Describedly import the PD2 phase discriminator into from signal, described standard source oscillation signal circuit output signal also imports PD2 into, and carries out under the control of MCU3 than phase; The control signal of PD2 output enters F10 amplifies, and sends into VCO2 at last as control voltage.
10. miniaturization satellite beacon receiver according to claim 9 is characterized in that the standard oscillator signal source circuit of the described second control voltage generation circuit is the described first C1 crystal oscillating circuit of controlling in the voltage generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202827668U CN201601675U (en) | 2009-12-31 | 2009-12-31 | Small-sized satellite beacon receiver |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009202827668U CN201601675U (en) | 2009-12-31 | 2009-12-31 | Small-sized satellite beacon receiver |
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| CN201601675U true CN201601675U (en) | 2010-10-06 |
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| CN2009202827668U Expired - Fee Related CN201601675U (en) | 2009-12-31 | 2009-12-31 | Small-sized satellite beacon receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461995A (en) * | 2014-11-24 | 2015-03-25 | 成都盛军电子设备有限公司 | Intermediate-frequency signal panel with memory function |
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- 2009-12-31 CN CN2009202827668U patent/CN201601675U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461995A (en) * | 2014-11-24 | 2015-03-25 | 成都盛军电子设备有限公司 | Intermediate-frequency signal panel with memory function |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101006 Termination date: 20121231 |