CN201576429U - Plasma display power supply time sequence control device - Google Patents
Plasma display power supply time sequence control device Download PDFInfo
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- CN201576429U CN201576429U CN 200920306195 CN200920306195U CN201576429U CN 201576429 U CN201576429 U CN 201576429U CN 200920306195 CN200920306195 CN 200920306195 CN 200920306195 U CN200920306195 U CN 200920306195U CN 201576429 U CN201576429 U CN 201576429U
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Abstract
The utility model relates to a plasma display power supply time sequence control device which comprises a microprocessor IC 1, a signal control unit and a voltage output end, wherein the microprocessor IC 1 is used for receiving a control signal of the signal control unit for controlling the voltage output of the voltage output end; and the signal control unit is used for receiving a power command signal and controlling the power supply voltage to be output according to the power supply voltage time sequence set in the IC 1 based on the power command signal. The plasma display power supply time sequence control device adopts the microprocessor IC 1 for centralized control, accurately controls the power supply time sequence when a plasma display is switched on or off, and provides the functions of overvoltage protection, under-voltage protection and output short circuit protection for the voltage output by a power module. The technical scheme adopts fewer elements, thus having low fault rate and low cost.
Description
Technical field
The utility model relates to a kind of power control, relates in particular to a kind of plasma display power supply timing control device.
Background technology
Plasma display (PlasmaDisplayPanel is called for short " PDP ") is showing the field widespread use.The principle of work of PDP is to inject mixed gas between two ultra-thin glass plates, and applies the equipment that voltage utilizes the light-emitting phosphor imaging.Compare with the CRT crt display unit, have the resolution height, screen is big, and is ultra-thin, the characteristics that rich color is bright-coloured.Compare with LCD, have the brightness height, the contrast height, visible angle is big, characteristics such as rapid dynamic response speed.
Because the high pressure VS backlight and the backlight drive VA of the PDP module in the plasma TV, and the supply voltage of master control borad and logic card must satisfy 5VSB, 5V_CTR, 15.5V the voltage sequential, that is: 5VSB is the working voltage of the start power supply of power module and total system, 5V_CTR is for supplying with the voltage of mainboard, and 15.5V is the logic card driving voltage.Will satisfy such sequential between starting-up signal STB and screen board backlight drive and the high pressure starting-up signal VS_ON backlight could normal boot-strap.Prior art adopts timer and capacitor charge and discharge to come the mimic channel of control timing to carry out switching on and shutting down; adopt analogue technique will reach the requirement of the multichannel output of control PDP power module; circuit is too complicated; adopt the electric capacity time to be difficult to control in allowed limits; adopt timer to control; circuit complexity, and also more complicated and use inconvenient of the overvoltage of output and the circuit of short-circuit protection.
The utility model content
The technical matters that the utility model solves is: make up a kind of plasma display power supply timing control device, overcome in the prior art with mimic channel control power switch machine and can not accurately control technical matters with the logical relation of the complexity of the switching on and shutting down of each road output.
The technical scheme of the utility model technical solution problem is: make up a kind of plasma display power supply timing control device, comprise: microprocessor IC1, signaling control unit, output voltage control module, described signaling control unit is sent the external power source signal that receives into described microprocessor IC1, and described microprocessor IC1 instructs the output voltage control module by the supply voltage sequential output voltage sequential that is provided with among the IC1 according to the power supply signal that receives.
Further technical scheme of the present utility model is: described signaling control unit comprises remote-controlled start-up and off signal control circuit and mainboard starting-up signal control circuit.
Further technical scheme of the present utility model is: described signaling control unit comprises mainboard starting-up signal control circuit, described mainboard starting-up signal control circuit comprises mainboard starting-up signal receiving end VS _ ON, resistance R S74, resistance R S73, NPN triode QS20, described resistance R S74 one termination starting-up signal receiving end, other end resistance in series RS73, be connected with NPN triode QS20 base stage simultaneously, described resistance R S73 one end is connected with resistance R S74, be connected with NPN triode QS20 base stage simultaneously, the other end connects the emitter of NPN triode QS20, and the collector of described NPN triode QS20 connects 6 pin of microprocessor IC1.
Further technical scheme of the present utility model is: described signaling control unit comprises remote-controlled start-up and off signal control circuit, described remote-controlled start-up and off signal control circuit comprise remote-controlled start-up and off signal receiving end STB, resistance R S14, resistance R S15, NPN triode QS19, described resistance R S14 one termination starting-up signal receiving end, other end resistance in series RS15, be connected with NPN triode QS19 base stage simultaneously, described resistance R S15 one end is connected with resistance R S14, be connected with NPN triode QS19 base stage simultaneously, the other end connects the emitter of NPN triode QS19, and the collector of described NPN triode QS19 connects 5 pin of microprocessor IC1.
Further technical scheme of the present utility model is: also comprise the alternating current signal detection unit, described alternating current signal detection unit comprises light lotus root IC5B, resistance R S160, resistance R S77, capacitor C S83, described resistance R S77 one end loads 5V voltage, another termination light lotus root IC5B, another termination parallel resistor RS160 of light lotus root IC5B and capacitor C S83 connect microprocessor 7 pin simultaneously.
Further technical scheme of the present utility model is: also comprise the output voltage control module, described output voltage control module comprises pressure sampling circuit that the voltage of output is sampled and the voltage protection module of carrying out circuit protection when sampled voltage is unusual.
Further technical scheme of the present utility model is: described pressure sampling circuit comprises the resistance of two series connection, and electric capacity is in parallel with one of them resistance, and output voltage connects the microprocessor respective foot after by the dividing potential drop of the resistance of two series connection and samples respectively.
Further technical scheme of the present utility model is: also comprise discharge cell, described discharge cell comprises microprocessor IC1, resistance R S129, resistance R S128, resistance R S125, triode QS10 and metal-oxide-semiconductor QS15,11 pin of described IC1 connect the base stage of triode QS10 by resistance R 129, the base stage of resistance R S128 resistance in series RS129 and connection triode QS10, described resistance R S125 connects the grid of described triode QS10 collector and metal-oxide-semiconductor QS15, the voltage of described resistance R S125 other end input 12V.
The technique effect that technical solutions of the utility model produce is: the utility model is by making up a kind of plasma display power supply timing control device; adopt microprocessor IC1 centralized control; the power supply sequential is accurately controlled during the plasma display switching on and shutting down, and the voltage of power module output is provided the function of overvoltage protection, under-voltage protection and output short circuit protection.The element that the technical program adopts is few, and failure rate is low, and cost is low.
Description of drawings
Fig. 1 is a johning knot composition of the present utility model.
Fig. 2 is a circuit connection diagram of the present utility model.
Fig. 3 is AC signal control circuit figure of the present utility model.
Fig. 4 is output voltage controlling circuit figure of the present utility model.
Fig. 5 is a discharge cell circuit diagram of the present utility model.
Fig. 6 is a power switch machine sequential chart of the present utility model.
Embodiment
Below in conjunction with specific embodiment, technical solutions of the utility model are further specified.
As Fig. 1, shown in Figure 6, the utility model makes up a kind of plasma display power supply timing control device, comprise: microprocessor IC1, signaling control unit, voltage output end, described microprocessor IC1 receives the control signal of described signaling control unit, controls the voltage output of described voltage output end; Signaling control unit receives the power supply command signal, exports by the supply voltage sequential that is provided with among the IC1 according to power supply command signal control supply voltage.Among the embodiment of the utility model patent, described signaling control unit comprises remote-controlled start-up and off signal control circuit and mainboard starting-up signal control circuit, described plasma display power supply timing control device receives the starting-up signal or the start control signal of described signaling control unit by microprocessor IC1, and described microprocessor IC1 instructs described voltage output end output voltage chronologically.In the present embodiment, microprocessor IC1 is S3F84k4 or S3F9454 single-chip microcomputer.
As Fig. 2, shown in Figure 6, preferred implementation of the present utility model is: described signaling control unit comprises mainboard starting-up signal control circuit, described mainboard starting-up signal control circuit comprises mainboard starting-up signal receiving end VS _ ON, resistance R S74, resistance R S73, NPN triode QS20, described resistance R S74 one termination starting-up signal receiving end, other end resistance in series RS73, be connected with NPN triode QS20 base stage simultaneously, described resistance R S73 one end is connected with resistance R S74, be connected with NPN triode QS20 base stage simultaneously, the other end connects the emitter of NPN triode QS20, and the collector of described NPN triode QS20 connects 6 pin of microprocessor IC1.When VS_ON has starting-up signal, starting-up signal is added in the base stage of described triode QS20 after by resistance R S74 and resistance R S73 dividing potential drop, described triode QS20 conducting, 6 pin that connect the microprocessor IC1 of described triode QS20 collector become low level by high level, 6 pin of IC1 are that starting-up signal detects mouth, after microprocessor IC1 received the starting-up signal of 6 pin, 12 pin of microprocessor IC1,13 pin required to export the high level of 5V, 12V, 15.5V chronologically.After receiving starting-up signal, because 12 pin of IC1 are the control signal end of 5V_CTR and 5V output, 13 pin of IC1 are the control signal end of 12V and 15.5V output, and 12 pin of IC1,13 pin require to export the voltage of 5V, 12V, 15.5V chronologically, and the PDP plasma display just can normal boot-strap.
As Fig. 2, shown in Figure 6, preferred implementation of the present utility model is: described signaling control unit comprises remote-controlled start-up and off signal control circuit, described remote-controlled start-up and off signal control circuit comprise that remote-controlled start-up signal and off signal receiving end STB, STB are that high level is a starting-up signal, and STB is that low level is an off signal.Resistance R S14, resistance R S15, NPN triode QS19, described resistance R S14 one termination starting-up signal receiving end or off signal receiving end STB, other end resistance in series RS15, be connected with NPN triode QS19 base stage simultaneously, described resistance R S15 one end is connected with resistance R S14, be connected with NPN triode QS19 base stage simultaneously, the other end connects the emitter of NPN triode QS19, and the collector of described NPN triode QS19 connects 5 pin of microprocessor IC1.When STB has starting-up signal or off signal, starting-up signal end or off signal end STB are added in the base stage of described triode QS19 after by resistance R S14 and resistance R S15 dividing potential drop, described triode QS19 conducting, 5 pin that connect the microprocessor IC1 of described triode QS19 collector become low level by high level, 5 pin of IC1 are that remote-controlled start-up signal or off signal detect mouth, after microprocessor IC1 receives the remote-controlled start-up signal of 5 pin, 12 pin of control IC1, the high level that 13 pin require to export 5V, 12V, 15.5V chronologically.After receiving remote-controlled start-up signal or off signal, because 12 pin of IC1 are the control signal end of 5V_CTR and 5V output, 13 pin of IC1 are the control signal end of 12V and 15.5V output, 12 pin of IC1,13 pin require to export the voltage of 5V, 12V, 15.5V chronologically, and the PDP plasma display just can remote-controlled start-up, shutdown.
As shown in Figure 3, preferred implementation of the present utility model is: described plasma display power supply timing control device also comprises the alternating current signal detection unit, described alternating current signal detection unit comprises light lotus root IC5B, resistance R S160, resistance R S77, capacitor C S83, described resistance R S77 one end loads 5V voltage, another termination light lotus root IC5B, another termination parallel resistor RS160 of light lotus root IC5B and capacitor C S83 connect microprocessor 7 pin simultaneously.In the present embodiment, 7 pin of IC1 are used for detecting AC-input voltage, when alternating voltage is lower than 70V, optocoupler IC5B can conducting, at this moment to detect 7 pin be low level to microprocessor IC1, low excessively in order to prevent input voltage, causes that input current is excessive, the protection power module, this moment, power module can not start work; When alternating voltage during greater than 70V, optocoupler IC5B conducting, the 5V voltage that loads produces high level after by resistance R S77, resistance R S160 dividing potential drop, the high level that is produced loads 7 pin of microprocessor IC1, at this moment to detect 7 pin be high level to microprocessor IC1, and the 3 pin output 5V of microprocessor IC1 prepares for starting whole power module.
As shown in Figure 4, preferred implementation of the present utility model is: described plasma display power supply timing control device also comprises the output voltage control module, described output voltage control module comprises pressure sampling circuit, described pressure sampling circuit comprises the resistance of two series connection, electric capacity is in parallel with one of them resistance, and output voltage connects microprocessor IC1 respective foot after by the dividing potential drop of the resistance of two series connection and samples respectively.In the present embodiment; the 5VSB end is the output terminal of the start power supply of power module and total system; the voltage of 5VSB end output outputs to 19 pin (P_5VSB shown in figure six) of described microprocessor IC1 after by resistance R S25 and resistance R S168 dividing potential drop; 19 pin of IC1 are the data sampling end of 5VSB aanalogvoltage; embedded digital simulation (A/D) converter by processor IC1; the voltage transitions of simulation is become the scope contrast that sets in advance in digital quantity and the system; if then normal output voltage in scope, if not at scope trigger voltage protection module then.Described voltage protection module is the voltage protection program, that is: instruction microprocessor IC1 shutdown chronologically earlier, and detection failure is removed situation again, removes as fault and then restarts again, if fault is not removed, then keeps off-mode, does not have normal output voltage.
As shown in Figure 4; preferred implementation of the present utility model is: the 5V_CTR end is the mainboard voltage supply side; the 5V voltage of 5V_CTR end output outputs to 15 pin (P_5V_CTR shown in figure six) of described microprocessor IC1 after by resistance R S93 and resistance R S92 dividing potential drop; 15 pin are the sampling end of 5V_CTR mainboard voltage; data sampling end for 5V_CTR motherboard power supply service voltage; embedded digital simulation (A/D) converter by processor IC1; the voltage transitions of simulation is become the scope contrast that is provided with in digital quantity and the program; if mainboard voltage is supplied with in then normal output in scope, if not at scope trigger voltage protection module then.Described voltage protection module is the voltage protection program, that is: instruction microprocessor IC1 shutdown chronologically earlier, and detection failure is removed situation again, removes as fault and then restarts again, if fault is not removed, then keeps off-mode, does not have normal output voltage.
As shown in Figure 4; preferred implementation of the present utility model is: the 15.5V end is the logic card driving voltage; 15.5V the 15.5V voltage of end output outputs to 16 pin (P_15.5V shown in figure six) of described microprocessor IC1 after by resistance R S95 and resistance R S94 dividing potential drop; described microprocessor IC1 samples to output voltage by 16 pin; embedded digital simulation (A/D) converter by processor IC1; the voltage transitions of simulation is become the scope contrast that is provided with in digital quantity and the program; if if then normally output in scope is not at scope trigger voltage protection module then.Described voltage protection module is the voltage protection program, that is: instruction microprocessor IC1 shutdown chronologically earlier, and detection failure is removed situation again, removes as fault and then restarts again, if fault is not removed, then keeps off-mode, does not have normal output voltage.
As shown in Figure 4; preferred implementation of the present utility model is: the Va end is the voltage of backlight drive signal end output; the voltage of Va end output outputs to 17 pin (P_Va shown in figure six) of described microprocessor IC1 after by resistance R S95 and resistance R S94 dividing potential drop; described microprocessor IC1 samples to output voltage by 17 pin; embedded digital simulation (A/D) converter by processor IC1; the voltage transitions of simulation is become digital quantity; with the scope contrast that is provided with in the program; if if then normally output in scope is not at scope trigger voltage protection module then.Described voltage protection module is the voltage protection program, that is: instruction microprocessor IC1 shutdown chronologically earlier, and detection failure is removed situation again, removes as fault and then restarts again, if fault is not removed, then keeps off-mode, does not have normal output voltage.
As shown in Figure 4; preferred implementation of the present utility model is: the Vs end is the voltage of high-voltage signal end output backlight; the voltage of Vs end output outputs to 18 pin (P_Vs shown in figure six) of described microprocessor IC1 after by resistance R S31 and resistance R S33 dividing potential drop; described microprocessor IC1 samples to output voltage by 18 pin; embedded digital simulation (A/D) converter by processor IC1; the voltage transitions of simulation is become the scope contrast that is provided with in digital quantity and the program; if if then normally output in scope is not at scope trigger voltage protection module then.Described voltage protection module is the voltage protection program, that is: instruction microprocessor IC1 shutdown chronologically earlier, and detection failure is removed situation again, removes as fault and then restarts again, if fault is not removed, then keeps off-mode, does not have normal output voltage.
As shown in Figure 5, preferred implementation of the present utility model is: also comprise discharge cell, described discharge cell comprises microprocessor IC1, resistance R S129, resistance R S128, resistance R S125, triode QS10 and metal-oxide-semiconductor QS15,11 pin of described IC1 connect the base stage of triode QS10 by resistance R 129, the base stage of resistance R S128 resistance in series RS129 and connection triode QS10, described resistance R S125 connects the grid of described triode QS10 collector and metal-oxide-semiconductor QS15, the voltage of described resistance R S125 other end input 12V.In normal operation, 11 pin of microprocessor IC1 output high level, triode QS10 conducting, metal-oxide-semiconductor QS15 ends, and the electric capacity of output voltage terminal can not be by cement resistor RS121 and RS122 discharge.When starting-up signal or off signal, microprocessor IC1 turn-offs high pressure VS backlight and backlight drive VA, the 11 pin output low levels of microprocessor IC1, QS10 is ended, the voltage of 12V is added in the grid of metal-oxide-semiconductor QS15 by RS125, make metal-oxide-semiconductor QS15 conducting, thereby make high pressure VS backlight and backlight drive VA, play the purpose of quick judgement PDP module voltage by cement resistor RS121 and RS122 discharge.
Above content be in conjunction with concrete preferred implementation to further describing that the utility model is done, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be considered as belonging to protection domain of the present utility model.
Claims (8)
1. plasma display power supply timing control device, it is characterized in that, comprise: microprocessor IC1, signaling control unit, output voltage control module, described signaling control unit is sent the external power source signal that receives into described microprocessor IC1, and described microprocessor IC1 instructs the output voltage control module by the supply voltage sequential output voltage sequential that is provided with among the IC1 according to the power supply signal that receives.
2. plasma display power supply timing control device according to claim 1 is characterized in that: described IC1 is S3F84k4 or S3F9454 single-chip microcomputer.
3. plasma display power supply timing control device according to claim 2, it is characterized in that: described signaling control unit comprises mainboard starting-up signal control circuit, described mainboard starting-up signal control circuit comprises mainboard starting-up signal receiving end VS__ON, resistance R S74, resistance R S73, NPN triode QS20, described resistance R S74 one termination starting-up signal receiving end, other end resistance in series RS73, be connected with NPN triode QS20 base stage simultaneously, described resistance R S73 one end is connected with resistance R S74, be connected with NPN triode QS20 base stage simultaneously, the other end connects the emitter of NPN triode QS20, and the collector of described NPN triode QS20 connects 6 pin of microprocessor IC1.
4. plasma display power supply timing control device according to claim 2, it is characterized in that: described signaling control unit comprises remote-controlled start-up and off signal control circuit, described remote-controlled start-up and off signal control circuit comprise starting-up signal receiving end STB, resistance R S14, resistance R S15, NPN triode QS19, described resistance R S14 one termination starting-up signal receiving end, other end resistance in series RS15, be connected with NPN triode QS19 base stage simultaneously, described resistance R S15 one end is connected with resistance R S14, be connected with NPN triode QS19 base stage simultaneously, the other end connects the emitter of NPN triode QS19, and the collector of described NPN triode QS19 connects 5 pin of microprocessor IC1.
5. plasma display power supply timing control device according to claim 2, it is characterized in that: also comprise the alternating current signal detection unit, described alternating current signal detection unit comprises light lotus root IC5B, resistance R S160, resistance R S77, capacitor C S83, described resistance R S77 one end loads 5V voltage, another termination light lotus root IC5B, another termination parallel resistor RS160 of light lotus root IC5B and capacitor C S83 connect microprocessor 7 pin simultaneously.
6. plasma display power supply timing control device according to claim 2; it is characterized in that: also comprise the output voltage control module, described output voltage control module comprises pressure sampling circuit that the voltage of output is sampled and the protection control module of carrying out circuit protection when sampled voltage is unusual.
7. plasma display power supply timing control device according to claim 6, it is characterized in that: described pressure sampling circuit comprises the resistance of two series connection, electric capacity is in parallel with one of them resistance, and output voltage connects the microprocessor respective foot after by the dividing potential drop of the resistance of two series connection and samples respectively.
8. plasma display power supply timing control device according to claim 2, it is characterized in that: also comprise discharge cell, described discharge cell comprises microprocessor IC1, resistance R S129, resistance R S128, resistance R S125, triode QS10 and metal-oxide-semiconductor QS15,11 pin of described IC1 connect the base stage of triode QS10 by resistance R 129, the base stage of resistance R S128 resistance in series RS129 and connection triode QS10, described resistance R S125 connects the grid of described triode QS10 collector and metal-oxide-semiconductor QS15, the voltage of described resistance R S125 other end input 12V.
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| CN 200920306195 CN201576429U (en) | 2009-07-14 | 2009-07-14 | Plasma display power supply time sequence control device |
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| CN 200920306195 CN201576429U (en) | 2009-07-14 | 2009-07-14 | Plasma display power supply time sequence control device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101609642B (en) * | 2009-07-14 | 2011-07-20 | 深圳晶辰电子科技股份有限公司 | Plasma display power supply timing control device |
| CN102169674A (en) * | 2011-01-21 | 2011-08-31 | 青岛海信电器股份有限公司 | Dynamic load adjusting module, liquid crystal display device and voltage adjusting method |
| CN102426818A (en) * | 2010-09-30 | 2012-04-25 | 四川虹欧显示器件有限公司 | Upward ramp signal generating circuit and plasma display |
-
2009
- 2009-07-14 CN CN 200920306195 patent/CN201576429U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101609642B (en) * | 2009-07-14 | 2011-07-20 | 深圳晶辰电子科技股份有限公司 | Plasma display power supply timing control device |
| CN102426818A (en) * | 2010-09-30 | 2012-04-25 | 四川虹欧显示器件有限公司 | Upward ramp signal generating circuit and plasma display |
| CN102426818B (en) * | 2010-09-30 | 2013-09-25 | 四川虹欧显示器件有限公司 | Upward ramp signal generating circuit and plasma display |
| CN102169674A (en) * | 2011-01-21 | 2011-08-31 | 青岛海信电器股份有限公司 | Dynamic load adjusting module, liquid crystal display device and voltage adjusting method |
| CN102169674B (en) * | 2011-01-21 | 2013-06-05 | 青岛海信电器股份有限公司 | Dynamic load adjusting module, liquid crystal display device and voltage adjusting method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20100908 Effective date of abandoning: 20090714 |