CN201570282U

CN201570282U - Media player with low clock jitter

Info

Publication number: CN201570282U
Application number: CN 200920261235
Authority: CN
Inventors: 万山
Original assignee: Shenzhen Colorful Technology And Development Co Ltd
Current assignee: Shenzhen Colorful Technology And Development Co Ltd
Priority date: 2009-12-08
Filing date: 2009-12-08
Publication date: 2010-09-01
Anticipated expiration: 2019-12-08
Also published as: WO2011069353A1

Abstract

The utility model relates to a media player with low clock jitter. The media player comprises a central controller for decoding media data, a storage module connected with the central controller and used for storing the media data, a digital-to-analog conversion module for converting the media data decoded by the central controller into analog signals, and an external clock module connected with the central controller and used for supplying clock signals to the central controller. The media player with low clock jitter provided by the utility model has the benefits that since the external clock module is provided with active crystal oscillators with lower oscillation errors, as well as a programmable logic component capable of clock processing, the clock signals supplied by the external clock module has small errors and lower clock jitter.

Description

Media player with low time base flutter

Technical field

The utility model relates to media play field, more particularly, relates to a kind of media player with low time base flutter.

Background technology

General player is because DAB is exported the deterioration that exists too much time base error (jitter) to cause tonequality, so a high-quality player primarily is the time base error that minimizing and elimination DSP etc. export through decoding.Usually, audio decoder chip clock is provided by its internal digital phaselocked loop (PLL), and the error of digital PLL is very big generally 100 to more than the 200PPM, and such error is an acceptable for the player of popular style, still, for comparatively high-end player, because it is to the having relatively high expectations of signal of output, if the scheme of stating in the use, owing to there is bigger time base error on its digital output signal, its output signal tonequality deterioration is more, just can not reach its requirement.Therefore, existing audio decoder chip can export have just necessary than hanging down the time base error digital signal.

The utility model content

The technical problems to be solved in the utility model is, at the higher defective of the above-mentioned time base flutter of prior art, provides a kind of media player of low time base flutter.

The technical scheme that its technical matters that solves the utility model adopts is: construct a kind of media player with low time base flutter, comprise the central controller that is used for media data is decoded, be connected with described central controller and be used to deposit the memory module of described media data and be the D/A converter module of simulating signal by digital-to-analog conversion described central controller decoded media data, also comprise with described central controller being connected, be used to described central controller that the external clock module of clock signal is provided.

In the media player with low time base flutter described in the utility model, described external clock module comprises the first frequency conversion module that is transformed to the needed clock of described central controller after handling as the first active crystal oscillator of oscillation source with the clock that the first active crystal oscillator produces.

In the media player with low time base flutter described in the utility model, described first frequency converter unit comprises frequency divider or frequency multiplier or the frequency translation unit that programmable logic device (PLD) forms.

In the media player with low time base flutter described in the utility model, described external clock module output decoder serial clock and code translator left and right acoustic channels data latching clock are to described central controller.

In the media player with low time base flutter described in the utility model, described external clock module also comprises the second frequency converter unit that is converted to the needed clock signal of described D/A converter module after handling as the second active crystal oscillator of oscillation source and with the clock that the described second active crystal oscillator is produced.

In the media player with low time base flutter described in the utility model, described second frequency converter unit comprises frequency divider or frequency multiplier or the frequency translation unit that programmable logic device (PLD) forms.

In the media player with low time base flutter described in the utility model, described external clock module output digital-to-analog conversion major clock, digital-to-analog conversion serial clock and digital-to-analog conversion left and right acoustic channels data latching clock are to described D/A converter module.

In the media player with low time base flutter described in the utility model, the shared programmable logic device (PLD) of described first frequency converter unit and second frequency converter unit, described programmable logic device (PLD) also comprise the media data passage that connects described central controller and described D/A converter module.

Implement the media player with low time base flutter of the present utility model, has following beneficial effect: owing to adopted external clock module, and this clock module employing itself has the source crystal device being arranged and using programmable logic device (PLD) to carry out the clock processing of low oscillation error, therefore, the error of the clock signal that this external clock module provides is little, and its time base flutter is lower.

Description of drawings

Fig. 1 is the structural representation that the utlity model has the media player embodiment of low time base flutter;

Fig. 2 is the structural representation of external clock module among the described embodiment;

Fig. 3 is a clock part high-level schematic functional block diagram in the described embodiment external clock module.

Embodiment

Below in conjunction with accompanying drawing the utility model embodiment is described further.

As shown in Figure 1, in the media player embodiment that the utlity model has low time base flutter, this media player comprises central controller 1, external clock module 2 and D/A converter module 3, wherein, central controller 1 will be sent to media data decoding wherein, and decoded data are passed 2 by the external clock module deliver to D/A converter module 3, simultaneously, external clock module 2 produces a plurality of clock signals, and sends it to respectively on above-mentioned central controller 1 and the D/A converter module 3.The core of above-mentioned central controller 1 is a demoder that media data is decoded and some control device, interface or the like.In addition, above-mentioned central controller 1 also (is used to control the operation of central controller 1 with the memory storage (not shown) that is used for the medium data, button, not shown) and LCD screen (be used to show above-mentioned media data information and operation information, not shown) etc. parts connect so that realize the function of media player.Because the content relation that these parts and present embodiments disclosed is little, does not also have too big difference in these parts and the prior art in the present embodiment, does not repeat them here.

Fig. 2 shows the general configuration of external clock module 2 in the present embodiment, in Fig. 2, clock module 2 comprises programmable logic device (PLD) 21 and the first active crystal oscillator 23 that is connected with this programmable logic device (PLD) 21 and the second active crystal oscillator 25, wherein, programmable logic device (PLD) 21 is divided into data channel 22, first frequency converting unit 24 and second frequency converting unit 26 again.Wherein, after the above-mentioned first active crystal oscillator 23 produces oscillator signal, be sent to first frequency converting unit 24, first frequency converting unit 24 is handled this oscillator signal, obtain above-mentioned demoder 1 needed various clock signals, and these clock signals are sent to demoder 1, for its use.Above-mentioned processing comprises that the oscillator signal that the first active crystal oscillator 23 is produced carries out frequency division, frequency multiplication or frequency transformation.In above-mentioned first frequency converting unit 24, frequency divider, frequency multiplier or frequency conversion unit can be set as required.After the above-mentioned second active crystal oscillator 25 produces oscillator signal, be sent to second frequency converting unit 26, second frequency converting unit 26 is handled this oscillator signal, obtain above-mentioned D/A converter module 3 needed various clock signals, and these clock signals are sent to D/A converter module 3, for its use.Above-mentioned processing comprises that the oscillator signal that the second active crystal oscillator 25 is produced carries out frequency division, frequency multiplication or frequency transformation.In above-mentioned second frequency converting unit 26, frequency divider, frequency multiplier or frequency conversion unit can be set as required.In addition, above-mentioned data channel 22 is used for transmitting data between the demoder of above-mentioned central controller 1 and D/A converter module 3, these data are got the media data decoding by the demoder in the central controller 1, and being sent to D/A converter module 3 carries out digital to analog conversion, obtains simulating signal and output.

Fig. 3 is a clock part high-level schematic functional block diagram in the present embodiment external clock module, and in Fig. 3, clock division device (CPLD) and SRC MODUAL (sample rate conversion chip) form, and wherein SRC MODUAL is a selectable unit.Wherein, TCX01, TCX02 are respectively first crystal oscillator 23 and second crystal oscillator 25 among Fig. 2, in Fig. 3, the first frequency converter unit 24 and the second frequency converter unit 26 of expression are expressed as a CLOCK MOUDAL respectively among Fig. 2, wherein, high more then JITTER is low more for above-mentioned crystal oscillator precision, and the clock division device adopt CPLD and FPGA all can, they in this module only as programmable frequency division device.The retardation ratio FPGA of CPLD is littler, and it is few to take resource, so select CPLD more excellent.

Because general multimedia player can adapt to the audio file of different sampling rates,, provide the output of SPDI F simultaneously so this clock module can adapt to the input of DAB of the sampling rate of 8KHZ-192Khz.

In Fig. 3, frequency division device and active crystal oscillator produce the reference clock of audio frequency DAC, and the BitClock of I2S output is undertaken synchronously by the clock of crystal oscillator, and I2S receives and output is provided with FIFO, isolate the form of the jitter convertible digital audio interface of while of input, the figure place of output etc. can be set.Because the output clock of I2S is synchronous with crystal oscillator clock source fully, the transfer clock of SPDIF directly is active crystal oscillator frequency division acquisition, avoided general integrated circuit produce the jitter deterioration problem that the TX clock causes by PLL.Can support 192kHZ/24bit output.

In addition, in the present embodiment, the support scope of sampling rate can reach 8KHZ-192Khz, the broadcast of compatible various sampling rate log files.In the present embodiment, cooperating by the SRC module, can select to use the SRC function, is common 44.1Khz/16bit file conversion maximum 192kHZ/24bit output, and the different sampling rate of output can be set.Can be exporting by SPDIF through the DAB of SRC conversion.

In the present embodiment, use the TCXO of two 1PPM errors and a CPLD to constitute clock module, the SRC chip is a selectable unit, and ultralow error clock is provided, and reaches the effect of effective elimination shake.

The above embodiment has only expressed several embodiment of the present utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model claim.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be as the criterion with claims.

Claims

1. media player with low time base flutter, comprise the central controller that is used for media data is decoded, be connected with described central controller and be used to deposit the memory module of described media data and be the D/A converter module of simulating signal by digital-to-analog conversion described central controller decoded media data, it is characterized in that, also comprise with described central controller being connected, be used to described central controller that the external clock module of clock signal is provided.

2. the media player with low time base flutter according to claim 1, it is characterized in that described external clock module comprises as the first frequency conversion module that is transformed to the needed clock of described central controller after first active crystal oscillator of oscillation source and the clock processing with the first active crystal oscillator generation.

3. the media player with low time base flutter according to claim 2 is characterized in that, described first frequency converter unit comprises frequency divider or frequency multiplier or the frequency translation unit that programmable logic device (PLD) forms.

4. the media player with low time base flutter according to claim 3 is characterized in that, described external clock module output decoder serial clock and code translator left and right acoustic channels data latching clock are to described central controller.

5. the media player with low time base flutter according to claim 4, it is characterized in that described external clock module also comprises the second frequency converter unit that is converted to the needed clock signal of described D/A converter module after the clock that is produced as the second active crystal oscillator of oscillation source and with the described second active crystal oscillator is handled.

6. the media player with low time base flutter according to claim 5 is characterized in that, described second frequency converter unit comprises frequency divider or frequency multiplier or the frequency translation unit that programmable logic device (PLD) forms.

7. the media player with low time base flutter according to claim 6, it is characterized in that described external clock module output digital-to-analog conversion major clock, digital-to-analog conversion serial clock and digital-to-analog conversion left and right acoustic channels data latching clock are to described D/A converter module.

8. the media player with low time base flutter according to claim 7, it is characterized in that, the shared programmable logic device (PLD) of described first frequency converter unit and second frequency converter unit, described programmable logic device (PLD) also comprise the media data passage that connects described central controller and described D/A converter module.