CN201549510U - Integrated inductor structure - Google Patents
Integrated inductor structure Download PDFInfo
- Publication number
- CN201549510U CN201549510U CN2009201783605U CN200920178360U CN201549510U CN 201549510 U CN201549510 U CN 201549510U CN 2009201783605 U CN2009201783605 U CN 2009201783605U CN 200920178360 U CN200920178360 U CN 200920178360U CN 201549510 U CN201549510 U CN 201549510U
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- Prior art keywords
- layer
- integrated inductance
- inductance structure
- integrated
- via hole
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides an integrated inductor structure, which comprises a coil. The coil comprises an aluminum layer located on a passivation layer, wherein the aluminum layer does not extend into the passivation layer, and the thickness of the aluminum layer is not lower than 2.0 micrometers. The integrated inductor structure has relatively high quality factor Q.
Description
Technical field
The utility model designs relevant for semiconducter IC, especially relevant for integrated inductor (integrated inductor) structure.
Background technology
The wireless communications market that develops rapidly is more and more higher to having multi-purpose little and cheap handheld device demand.A main trend of circuit design be as far as possible more circuit is carried out integrated so that reduce the cost of each wafer (wafer).
Inductance on the semiconductor wafer is widely used in based on the radio frequency of complementary metal oxide semiconductors (CMOS) (CMOS) (Radio Frequency, RF) circuit, for example low noise amplifier, voltage controlled oscillator and power amplifier.Inductance is a kind of passive (passive) electronic component with the field form storage power, and inductance can be resisted the variation of the electric current of the inductance of flowing through.
A key property of inductance is a quality factor q, and quality factor q is relevant with the performance of RF circuit or other circuit and system.The quality factor q of IC (Integrated Circuit) is limited by parasitism (parasitic) loss of its substrate (substrate) itself.These losses comprise the high impedance that metal level brought of inductance.Therefore, in order to reach higher quality factor q, the impedance of inductance should maintain minimum value.A kind of method that minimizes inductive impedance is the thickness that increases in order to the metal of making inductance.
Therefore, owing to the topmost metal layer (for example the superiors of damascene copper interconnect structure) of the integrated inductance structure of being made by RF baseline (baseline) method is thicker, make the impedance of integrated inductance structure be minimized.To those skilled in the art, realize that in topmost metal layer the metal level thickening is easy than other metal level.RF baseline method with 0.13 μ m is an example, and the thickness that topmost metal layer has 3 μ m is very usual.Yet excessively thick metal level usually can cause complicated processing and relative higher cost.
The utility model content
In view of this, need provide a kind of integrated inductance structure with higher figure of merit Q.
The utility model provides a kind of integrated inductance structure, comprises coil, and this coil comprises the aluminium lamination that is positioned on the passivation layer, and wherein, this aluminium lamination does not extend to this passivation layer inside, and the thickness of this aluminium lamination is not less than 2.0 microns.
The integrated inductance structure that the utility model provides has higher figure of merit Q.
Description of drawings
Fig. 1 is the schematic top plan view according to the integrated inductance structure with a plurality of coils 10 of the utility model embodiment;
Fig. 2 is the cross section perspective diagram along the I-I ' line of Fig. 1;
Fig. 3 is the generalized section according to the integrated inductance structure of the quality factor q with further improvement of another embodiment of the utility model and the substrate coupling that reduces.
Embodiment
In the middle of specification, used some vocabulary to censure specific components.The technical staff should understand in the affiliated field, and same assembly may be called with different nouns by manufacturer.This specification is not used as distinguishing the scheme of assembly with the difference of title, but the criterion that is used as distinguishing with the difference of assembly on function.Be an open term mentioned " comprising " and " comprising " in the middle of specification and the follow-up request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect electric connection means that directly reach at this.Indirect electric connection means comprise by other device and connecting.
The utility model belongs to the improvement of integrated inductance structure or transformer device structure, makes it have better quality factor q and reduce unwanted substrate to be coupled, and also can reduce the technology cost.On the one hand, the utility model adopts linear via structure (line-shaped via structure) to replace hole (hole) shape via structure, in order to upper strata metal and lower metal are electrically connected.Traditionally, be arranged at a lot of via hole bolts (via plug) in the conductive layer (conductive layer) of semiconductor equipment in order to electrically connect these conductive layers, uniformity for technology, traditional hole shape via hole bolt has unified shape and size, therefore, in order to reduce impedance, need utilize one group of (array) via hole bolt.
The utility model adopts a metal level (for example aluminium) on the other hand on the passivation layer of IC chip, to make integrated inductance structure, so just can reduce the thickness of IC chip the superiors copper layer.
Place aluminium lamination on the passivation layer usually in order to a joint interface on the copper bond pad to be provided, oxidized to prevent following copper product, wherein, this copper bond pad is formed in the copper layer of the IC chip the superiors.
Below with reference to accompanying drawing the utility model embodiment is described in detail.Label " M in specification and the accompanying drawing
n" metal level of the expression the superiors, the copper layer in the IC chip for example; " M
N-1" expression copper layer M
N-1Only than the copper layer M of the superiors
nLow one deck, the rest may be inferred; Wherein, preferably, the scope of n is between 4 to 8, but the utility model is not limited to this.Via hole bolt layer between two adjacent copper layers of label " V " expression.For instance, V
5Expression is with metal level M
5With metal level M
6The via hole bolt layer V of interconnection
5
Fig. 1 is the schematic top plan view according to the integrated inductance structure 10 with multi-turn coil (multi-turn winding) of the utility model embodiment.Fig. 2 is according to the cross section perspective diagram of preferred embodiment of the utility model along the I-I ' line of Fig. 1.For easy, only show the differential pair (differential pair) of two adjacent windings 12 among Fig. 2.
The integrated inductance structure 10 that should be appreciated that the utility model embodiment adopts octagonal shape, but integrated inductance structure 10 also can adopt other shape that is fit to, and is for example spiral-shaped.The shape or the pattern of inductance are not restricted to this.The utility model is equally applicable to single-ended inductance (single-ended inductor).
As Fig. 1 and shown in Figure 2, each coil 12 of integrated inductance structure 10 all has vertical metal stack (metal stack) layer, and stacked laminations of metal comprises in the following order: metal level M
N-1, via hole bolt layer V
N-1, metal level M
n, via hole bolt layer V
nAnd aluminium lamination 20 (simply being denoted as " aluminium " among Fig. 2).Can pass through via hole bolt layer V
N-1With metal level M
N-1Be electrically connected to metal level M
n, by via hole bolt layer V
nWith metal level M
nBe electrically connected to aluminium lamination 20.According to preferred embodiment of the utility model, the coil 12 of integrated inductance structure 10 does not comprise lower metal level M
1～M
N-2, to reduce the parasitic couplings loss of substrate 100.According to another preferred embodiment of the utility model, coil 12 does not comprise lower metal level M
1～M
2
In an execution mode of the present utility model, via hole bolt layer V
N-1And V
nIt all is linear structure.Preferred implementation is linear structure via hole bolt layer V
N-1And V
nWith metal level M
N-1, metal level M
nAnd aluminium lamination 20 has identical in fact pattern (pattern), and linear structure via hole bolt layer V
N-1And V
nLive width in fact than metal level M
N-1Or metal level M
nLive width smaller.By adopting the via hole bolt layer V of linear structure
N-1And V
n, the resistance value of integrated inductance structure 10 can reduce.
In this embodiment, the via hole bolt layer of less live width is not to be restriction of the present utility model.In other embodiments, the live width of via hole bolt layer can be identical with the live width of metal level or greater than the live width of metal level.Further, the shape of the linear via hole that aforementioned pattern is identical in fact is not restriction of the present utility model yet.In other embodiments, the pattern of linear via hole bolt layer can also be to comprise a plurality of fragments linear (segmented line-shaped) via hole in each coil.
According to preferred embodiment of the utility model, metal level M
N-1, via hole bolt layer V
N-1And metal level M
n(copper damascene method) forms by the traditional copper method for embedding, for example single inlay structure method (single damascene) or dual-damascene structure method (dual damascene).For instance, metal level M
N-1Form metal level M by the single inlay structure method
nAnd whole (integral) via hole bolt layer V
N-1Realize by the dual-damascene structure method.So, metal level M
nWith via hole bolt layer V
N-1Just become as a whole (unitary).
Just as known to persons of ordinary skill in the art, the solution that the copper method for embedding provides a kind of formation one lead and a whole via hole bolt to couple, and do not need dry etching copper (dry etching copper).Single inlay structure all can be in order to be connected device and/or the line (wire) among the IC with dual-damascene structure.
In general, dual-damascene structure can be divided into preferential (trench-first) structure of groove, preferential (via-first) structure of via hole, preferential (partial-via-first) structure of part via hole and self-aligned formula (self-aligned) structure.For instance, a kind of technology of traditional double mosaic texture is at first to etch groove and cross hole (via hole) on insulating barrier (dielectric layer).Cross hole and groove and align, fill copper then with the barrier layer (barrier) of for example tantalum (Ta) or tantalum nitride (TaN).Then use for example chemico-mechanical polishing of flatening process (planarizationprocess) (CMP) with formation inlay metal interconnected.
Multilayer dielectric layer 102～108 and passivation layer 110 are positioned at substrate 100.According to preferred embodiment of the utility model, integrated inductance structure 10 is made in substantially on the insulating barrier 102 between insulating barrier 104 and the substrate 100.Metal level M
N-1Inlay (inlaid) to insulating barrier 104.Metal level M
nAnd whole via hole bolt layer V
N-1Inlay respectively to insulating barrier 108 and insulating barrier 106.
According to a preferred embodiment of the present utility model, via hole bolt layer V
nBe metallic aluminium, and via hole bolt layer V
nBe combined into integral body with aluminium lamination 20.That is to say via hole bolt layer V
nWith aluminium lamination 20 be an integral body.On structure, via hole bolt layer V
nInlay the hole slot excessively (figure does not show) to correspondence, this crosses hole-and-slot one-tenth in passivation layer 110, and aluminium lamination 20 is patterning on passivation layer 110.Via hole bolt layer V
nCan form simultaneously with traditional layer (re-distribution layer) that reroutes (figure does not show) with aluminium lamination 20.Preferably, the thickness h 1 of aluminium lamination 20 can be in 1 micron to 1.5 microns scope, and thickness h 1 usually can be less than 1.5 microns.
Integrated inductance structure 10 complete compatibility standard logic manufacturing process, and because whole via hole bolt layer V
nWith aluminium lamination 20 and be one, integrated inductance structure 10 does not comprise blocked up copper layer.
In other embodiment of the present utility model,, make the impedance of integrated inductance structure reduce by using linear via structure.Can realize having the integrated inductance structure of high quality factor Q by vertical metal stack, wherein, metal stack has following order: metal level M
N-1, via hole bolt layer V
N-1And metal level M
n, perhaps, metal stack also can have following order: top copper layer M
n, via hole bolt layer V
nAnd aluminium lamination.
Along with the continuous development of semiconductor technology, the thickness of each insulating barrier of IC is more and more thinner.This causes the distance between induction structure bottom surface and the semiconductor substrate first type surface to reduce, and therefore the undesirable substrate of generation is coupled and quality factor q is worsened on inductance.The thickness of advanced IC metal interlevel (inter-layer) insulating barrier inevitably dwindles, and causes quality factor q to worsen, and is head it off, and the utility model another embodiment again provides a kind of new integrated inductance structure.
Fig. 3 is according to another embodiment of the present utility model, has the integrated inductance structure generalized section of the quality factor q of further improvement and less parasitic substrate coupling, wherein, represents identical assembly, layer or zone with Fig. 1,2 identical labels.As shown in Figure 3, integrated inductance structure is formed among the induction areas 10a equally, and integrated inductance structure comprises a plurality of coils, and for for purpose of brevity, Fig. 3 only shows the differential pair of two adjacent windings 12.Observe from the integrated inductance structure top, the form of the integrated inductance structure of this embodiment can be octagon, spirality or other any suitable shape.Similar according to the integrated inductance structure exemplary shapes of this embodiment and shape shown in Figure 1.
A copper interconnection structure 202 can be provided outside induction areas 10a.Copper interconnection structure 202 can be at metal level M
1～M
nAny one and via hole bolt V
1～V
N-1Any one in make, copper interconnection structure 202 is inlayed to corresponding insulation layer 102～108.According to this embodiment, do not form copper interconnection structure among the induction areas 10a.Copper interconnection structure 202 can be made by the traditional copper method for embedding.Insulating barrier 102～108 can comprise silica, silicon nitride, carborundum, silicon oxynitride, low-k (low-k) material or ultralow dielectric coefficient (ultra low-k) material for example organic substance (SILK) or inorganic matter (HSQ).
According to this embodiment, each in the integrated inductance structure in adjacent two coils 12 can be made by aluminium lamination 20 ', and not necessarily adopts copper product.That is to say that integrated inductance structure can only be defined by the aluminium lamination 20 ' with big thickness h 2, wherein, the thickness h 2 of aluminium lamination 20 ' is greater than the thickness h 1 of aluminium lamination 20.For example, thickness h 2 approximately can for example can be 3.0 microns or thicker greater than 2.0 microns.Thicker aluminium lamination 20 ' can help to reduce the resistance value of inductance.
In one embodiment, aluminium lamination 20 ' can be the layer that reroutes.The layer that reroutes also can comprise i/o pads and lead cabling (wire trace).Integrated inductance structure can be formed in the IC device with substrate and a plurality of metal levels, and wherein at least one metal level comprises copper.Between integrated inductance structure and substrate, also can form without any metal level.A plurality of metal levels go up most two-layer at least one deck can comprise copper.Distance between the first type surface 100a of the bottom surface 12a of integrated inductance structure and substrate 100 is called distance D.Preferably, distance D is not less than the bottom surface of topmost metal layer and the distance between the substrate 100 first type surface 100a.
Integrated inductance structure comprises coil 12, and coil 12 comprises the aluminium lamination 20 ' that is positioned on the passivation layer 110 ', and wherein, aluminium lamination 20 ' does not extend to passivation layer 110 ' inside, and the thickness of aluminium lamination 20 ' approximately is to be not less than 2.0 microns.Integrated inductance structure is formed on the passivation layer 110 ', and the thickness t 2 of passivation layer 110 ' approximately is to be not less than 0.8 micron.According to this embodiment, the thickness t 2 of passivation layer 110 ' is greater than the thickness t 1 of passivation layer shown in Figure 2 110.And it is one of characteristics of the present utility model that passivation layer 110 ' has bigger thickness.According to present embodiment, passivation layer 110 ' can be silica, silicon nitride, carborundum, silicon oxynitride, polyimides or the like.
By from integrated inductance structure, removing copper and increasing the thickness of passivation layer 110 ', it is big that distance D between the first type surface 100a of induction structure bottom surface 12a and semiconductor substrate 100 becomes, reduced the parasitic substrate coupling thus, in addition, the aluminum layer thickness of increase also helps to improve quality factor q.According to an embodiment of the present utility model, under the preferable situation, for obtaining better quality factor performance, the distance D in the advanced IC chip between induction structure bottom surface 12a and the semiconductor substrate 100 first type surface 100a approximately is greater than 3.0 microns.According to another embodiment, the distance D between the bottom surface 12a of integrated inductance structure and the substrate 100 first type surface 100a can be not more than 10 microns.
Any those skilled in the art, in not breaking away from spirit and scope of the present utility model, when doing a little change and retouching, therefore protection range of the present utility model is when being as the criterion that the right requirement is defined.
Claims (10)
1. an integrated inductance structure is characterized in that, described integrated inductance structure comprises coil, and described coil comprises the aluminium lamination that is positioned on the passivation layer, and wherein, described aluminium lamination does not extend to described passivation layer inside, and the thickness of described aluminium lamination is not less than 2.0 microns.
2. integrated inductance structure as claimed in claim 1 is characterized in that, the thickness of described passivation layer is to be not less than 0.8 micron.
3. integrated inductance structure as claimed in claim 1 is characterized in that described integrated inductance structure is made in the inductor section, and does not form copper interconnection structure in the described inductor section.
4. integrated inductance structure as claimed in claim 1 is characterized in that described aluminium lamination is the layer that reroutes.
5. integrated inductance structure as claimed in claim 1 is characterized in that described coil comprises aluminium.
6. integrated inductance structure as claimed in claim 1 is characterized in that, described integrated inductance structure is formed in the integrated circuit (IC) apparatus with substrate and a plurality of metal levels, in described a plurality of metal levels at least one deck comprise copper.
7. integrated inductance structure as claimed in claim 6 is characterized in that, described a plurality of metal levels all are not formed between integrated inductance structure and the substrate.
8. integrated inductance structure as claimed in claim 6, it is characterized in that the distance between the bottom surface of described integrated inductance structure and the first type surface of described substrate is not less than the distance between the described first type surface of the bottom surface of topmost metal layer in described a plurality of metal level and described substrate.
9. integrated inductance structure as claimed in claim 6 is characterized in that, the distance between the bottom surface of described integrated inductance structure and the first type surface of described substrate is not less than 3 microns.
10. integrated inductance structure as claimed in claim 6 is characterized in that, described a plurality of metal levels go up most two-layer at least one deck be the copper layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US18016409P | 2009-05-21 | 2009-05-21 | |
| US61/180,164 | 2009-05-21 | ||
| US12/493,245 US8860544B2 (en) | 2007-06-26 | 2009-06-29 | Integrated inductor |
| US12/493,245 | 2009-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201549510U true CN201549510U (en) | 2010-08-11 |
Family
ID=42604689
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009201783605U Expired - Lifetime CN201549510U (en) | 2009-05-21 | 2009-11-13 | Integrated inductor structure |
| CN200910222555XA Pending CN101894838A (en) | 2009-05-21 | 2009-11-13 | Integrated inductor |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910222555XA Pending CN101894838A (en) | 2009-05-21 | 2009-11-13 | Integrated inductor |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN201549510U (en) |
| TW (1) | TWI467741B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9224773B2 (en) | 2011-11-30 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal shielding layer in backside illumination image sensor chips and methods for forming the same |
| TWI643216B (en) * | 2017-11-10 | 2018-12-01 | 瑞昱半導體股份有限公司 | Integrated inductor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3898024B2 (en) * | 2001-10-19 | 2007-03-28 | Ｎｅｃエレクトロニクス株式会社 | Integrated circuit and manufacturing method thereof |
| US7663205B2 (en) * | 2004-08-03 | 2010-02-16 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a dummy gate structure below a passive electronic element |
-
2009
- 2009-10-28 TW TW98136495A patent/TWI467741B/en active
- 2009-11-13 CN CN2009201783605U patent/CN201549510U/en not_active Expired - Lifetime
- 2009-11-13 CN CN200910222555XA patent/CN101894838A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TWI467741B (en) | 2015-01-01 |
| TW201042753A (en) | 2010-12-01 |
| CN101894838A (en) | 2010-11-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100811 |
|
| CX01 | Expiry of patent term |